torsdag den 6. oktober 2022 kl. 20.04.09 UTC+2 skrev Phil Hobbs:
> Lasse Langwadt Christensen wrote:
> > torsdag den 6. oktober 2022 kl. 18.51.13 UTC+2 skrev Phil Hobbs:
> >> John Robertson wrote:
> >>> On 2022/10/06 4:41 a.m., Phil Hobbs wrote:
> >>>> John Robertson wrote:
> >>>>> Have a circuit that needs repair. Uses a TIP125 (NPN, Darlington)
> >>>>> emitter tied to Vbb (~20VDC). Collector to load, then to ground. 1K
> >>>>> resistor (R1) pullup on Base to Vbb, and a second 1KR (R2) to the TTL
> >>>>> controller.
> >>>>>
> >>>>> Problem is of course, that R2 puts the ~20VDC to the TTL output gate
> >>>>> on a 74LS138.
> >>>>>
> >>>>> Trying to solve this without a driver transistor. The circuit is for
> >>>>> a 1ms ~20V strobe pulse repeated every ten ms.
> >>>>>
> >>>>> I thought of putting a 10ufd cap in series with R2, but don't like
> >>>>> electrolytics as they fail after a few thousand hours.
> >>>>>
> >>>>> Possible to use a 15V or so Zener Diode, but the Vbb is not regulated
> >>>>> so that won't work reliably.
> >>>>>
> >>>>> Anyone have a single component in mind that will essentially emulate
> >>>>> (isolate) an Open-Collector output for the 138?
> >>>>>
> >>>>> Thanks!
> >>>>>
> >>>>> John :-#)#
> >>>>>
> >>>> Switch it to a 139 and use a 2N7002?
> >>>>
> >>>> Cheers
> >>>>
> >>>> Phil Hobbs
> >>>>
> >>>
> >>> Well, this is to fix 5 x PCBs we are stuck with at the moment, next run
> >>> will fix the drives - either 7445s or 138 with P-Channel MOSFETs and
> >>> drivers.
> >>>
> >>> Circuit I am trying to fix with fewest components - one x two legged
> >>> device preferred per 138 output:
> >>>
> >>> https://www.flippers.com/images/delete/74LS138_Lamp_Driver.png
> >>>
> >>> VLAMP is roughly 20VDC.
> >>>
> >>> Thanks,
> >>>
> >>> John :-#)#
> >> The MOSFET cascode thing is pretty good actually, if you put a diode to
> >> the supply or want to live dangerously and rely on the ESD protection to
> >> discharge the gate. If it's a matter of using the boards or tossing
> >> them, there's not much to lose by using barefoot FETs.
> >>
> >
> > '138 is push-pull, though very wimpy high side
> >
> Sure, but anything above +4ish reverse-biases the upper output transistor.
> Cheers

with the upper transistor on does it ever get there?

Lasse Langwadt Christensen wrote:
> torsdag den 6. oktober 2022 kl. 20.04.09 UTC+2 skrev Phil Hobbs:
>> Lasse Langwadt Christensen wrote:
>>> torsdag den 6. oktober 2022 kl. 18.51.13 UTC+2 skrev Phil Hobbs:
>>>> John Robertson wrote:
>>>>> On 2022/10/06 4:41 a.m., Phil Hobbs wrote:
>>>>>> John Robertson wrote:
>>>>>>> Have a circuit that needs repair. Uses a TIP125 (NPN, Darlington)
>>>>>>> emitter tied to Vbb (~20VDC). Collector to load, then to ground. 1K
>>>>>>> resistor (R1) pullup on Base to Vbb, and a second 1KR (R2) to the TTL
>>>>>>> controller.
>>>>>>>
>>>>>>> Problem is of course, that R2 puts the ~20VDC to the TTL output gate
>>>>>>> on a 74LS138.
>>>>>>>
>>>>>>> Trying to solve this without a driver transistor. The circuit is for
>>>>>>> a 1ms ~20V strobe pulse repeated every ten ms.
>>>>>>>
>>>>>>> I thought of putting a 10ufd cap in series with R2, but don't like
>>>>>>> electrolytics as they fail after a few thousand hours.
>>>>>>>
>>>>>>> Possible to use a 15V or so Zener Diode, but the Vbb is not regulated
>>>>>>> so that won't work reliably.
>>>>>>>
>>>>>>> Anyone have a single component in mind that will essentially emulate
>>>>>>> (isolate) an Open-Collector output for the 138?
>>>>>>>
>>>>>>> Thanks!
>>>>>>>
>>>>>>> John :-#)#
>>>>>>>
>>>>>> Switch it to a 139 and use a 2N7002?
>>>>>>
>>>>>> Cheers
>>>>>>
>>>>>> Phil Hobbs
>>>>>>
>>>>>
>>>>> Well, this is to fix 5 x PCBs we are stuck with at the moment, next run
>>>>> will fix the drives - either 7445s or 138 with P-Channel MOSFETs and
>>>>> drivers.
>>>>>
>>>>> Circuit I am trying to fix with fewest components - one x two legged
>>>>> device preferred per 138 output:
>>>>>
>>>>> https://www.flippers.com/images/delete/74LS138_Lamp_Driver.png
>>>>>
>>>>> VLAMP is roughly 20VDC.
>>>>>
>>>>> Thanks,
>>>>>
>>>>> John :-#)#
>>>> The MOSFET cascode thing is pretty good actually, if you put a diode to
>>>> the supply or want to live dangerously and rely on the ESD protection to
>>>> discharge the gate. If it's a matter of using the boards or tossing
>>>> them, there's not much to lose by using barefoot FETs.
>>>>
>>>
>>> '138 is push-pull, though very wimpy high side
>>>
>> Sure, but anything above +4ish reverse-biases the upper output transistor.
>> Cheers
>
> with the upper transistor on does it ever get there?
>
>

Sure, it's an NPN emitter. If it were a NFET, it would be fine.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510

http://electrooptical.net
http://hobbs-eo.com

On Thu, 6 Oct 2022 09:44:13 -0700, John Robertson <jrr@flippers.com>
wrote:

>On 2022/10/06 7:50 a.m., John Larkin wrote:
>> On Wed, 5 Oct 2022 23:24:26 -0700, John Robertson <jrr@flippers.com>
>> wrote:
>>
>>> Have a circuit that needs repair. Uses a TIP125 (NPN, Darlington)
>>> emitter tied to Vbb (~20VDC). Collector to load, then to ground. 1K
>>> resistor (R1) pullup on Base to Vbb, and a second 1KR (R2) to the TTL
>>> controller.
>>
>> That's not clear. Got a schematic?
>
>Yes:
>
>https://www.flippers.com/images/delet/74LS138_Lamp_Driver.png

404 error.

On 2022/10/06 12:41 p.m., John Larkin wrote:
> On Thu, 6 Oct 2022 09:44:13 -0700, John Robertson <jrr@flippers.com>
> wrote:
>
>> On 2022/10/06 7:50 a.m., John Larkin wrote:
>>> On Wed, 5 Oct 2022 23:24:26 -0700, John Robertson <jrr@flippers.com>
>>> wrote:
>>>
>>>> Have a circuit that needs repair. Uses a TIP125 (NPN, Darlington)
>>>> emitter tied to Vbb (~20VDC). Collector to load, then to ground. 1K
>>>> resistor (R1) pullup on Base to Vbb, and a second 1KR (R2) to the TTL
>>>> controller.
>>>
>>> That's not clear. Got a schematic?
>>
>> Yes:
>>
>> https://www.flippers.com/images/delet/74LS138_Lamp_Driver.png
>
>
> 404 error.
>

sorry:

https://www.flippers.com/images/delete/74LS138_Lamp_Driver.png

Currently wire wrapping up a board to jam a 7445 in place of the 138.

John :-#)#
--
(Please post followups or tech inquiries to the USENET newsgroup)
John's Jukes Ltd.
MOVED to #7 - 3979 Marine Way, Burnaby, BC, Canada V5J 5E3
(604)872-5757 (Pinballs, Jukes, Video Games)
www.flippers.com
"Old pinballers never die, they just flip out."

torsdag den 6. oktober 2022 kl. 18.35.18 UTC+2 skrev Ricky:
> On Thursday, October 6, 2022 at 12:17:08 PM UTC-4, lang...@fonz.dk wrote:
> > torsdag den 6. oktober 2022 kl. 17.51.16 UTC+2 skrev Fred Bloggs:
> > > On Thursday, October 6, 2022 at 11:37:46 AM UTC-4, lang...@fonz.dk wrote:
> > > > torsdag den 6. oktober 2022 kl. 17.29.21 UTC+2 skrev Fred Bloggs:
> > > > > On Thursday, October 6, 2022 at 2:24:33 AM UTC-4, John Robertson wrote:
> > > > > > Have a circuit that needs repair. Uses a TIP125 (NPN, Darlington)
> > > > > > emitter tied to Vbb (~20VDC). Collector to load, then to ground. 1K
> > > > > > resistor (R1) pullup on Base to Vbb, and a second 1KR (R2) to the TTL
> > > > > > controller.
> > > > > >
> > > > > > Problem is of course, that R2 puts the ~20VDC to the TTL output gate on
> > > > > > a 74LS138.
> > > > > >
> > > > > > Trying to solve this without a driver transistor. The circuit is for a
> > > > > > 1ms ~20V strobe pulse repeated every ten ms.
> > > > > >
> > > > > > I thought of putting a 10ufd cap in series with R2, but don't like
> > > > > > electrolytics as they fail after a few thousand hours.
> > > > > >
> > > > > > Possible to use a 15V or so Zener Diode, but the Vbb is not regulated so
> > > > > > that won't work reliably.
> > > > > >
> > > > > > Anyone have a single component in mind that will essentially emulate
> > > > > > (isolate) an Open-Collector output for the 138?
> > > > > The TIP125 is a complementary dual.
> > > > it is? https://www.onsemi.com/pdf/datasheet/tip120-d.pdf
> > > Yeah it is. See Figure 1. All of that is in that TO-220 looking package.
> > and the three missing legs are where?
> >
> > TIP120, TIP121, TIP122 (NPN); is the right drawing
> >
> > TIP125, TIP126, TIP127 (PNP); is the left drawing
> It would seem a combination of a high side PNP driver and a low side NPN level shifter would be a useful, single package device. Is there a reason why this is hard to make on a single die?
>

what package would you put it in? you'd need more than 3 pins

I think the closest is arrays like UDN2981

On Thursday, October 6, 2022 at 12:17:08 PM UTC-4, lang...@fonz.dk wrote:
> torsdag den 6. oktober 2022 kl. 17.51.16 UTC+2 skrev Fred Bloggs:
> > On Thursday, October 6, 2022 at 11:37:46 AM UTC-4, lang...@fonz.dk wrote:
> > > torsdag den 6. oktober 2022 kl. 17.29.21 UTC+2 skrev Fred Bloggs:
> > > > On Thursday, October 6, 2022 at 2:24:33 AM UTC-4, John Robertson wrote:
> > > > > Have a circuit that needs repair. Uses a TIP125 (NPN, Darlington)
> > > > > emitter tied to Vbb (~20VDC). Collector to load, then to ground. 1K
> > > > > resistor (R1) pullup on Base to Vbb, and a second 1KR (R2) to the TTL
> > > > > controller.
> > > > >
> > > > > Problem is of course, that R2 puts the ~20VDC to the TTL output gate on
> > > > > a 74LS138.
> > > > >
> > > > > Trying to solve this without a driver transistor. The circuit is for a
> > > > > 1ms ~20V strobe pulse repeated every ten ms.
> > > > >
> > > > > I thought of putting a 10ufd cap in series with R2, but don't like
> > > > > electrolytics as they fail after a few thousand hours.
> > > > >
> > > > > Possible to use a 15V or so Zener Diode, but the Vbb is not regulated so
> > > > > that won't work reliably.
> > > > >
> > > > > Anyone have a single component in mind that will essentially emulate
> > > > > (isolate) an Open-Collector output for the 138?
> > > > The TIP125 is a complementary dual.
> > > it is? https://www.onsemi.com/pdf/datasheet/tip120-d.pdf
> > Yeah it is. See Figure 1. All of that is in that TO-220 looking package.
> and the three missing legs are where?
>
> TIP120, TIP121, TIP122 (NPN); is the right drawing
>
> TIP125, TIP126, TIP127 (PNP); is the left drawing

STM has the version with both.

fredag den 7. oktober 2022 kl. 02.34.10 UTC+2 skrev Fred Bloggs:
> On Thursday, October 6, 2022 at 12:17:08 PM UTC-4, lang...@fonz.dk wrote:
> > torsdag den 6. oktober 2022 kl. 17.51.16 UTC+2 skrev Fred Bloggs:
> > > On Thursday, October 6, 2022 at 11:37:46 AM UTC-4, lang...@fonz.dk wrote:
> > > > torsdag den 6. oktober 2022 kl. 17.29.21 UTC+2 skrev Fred Bloggs:
> > > > > On Thursday, October 6, 2022 at 2:24:33 AM UTC-4, John Robertson wrote:
> > > > > > Have a circuit that needs repair. Uses a TIP125 (NPN, Darlington)
> > > > > > emitter tied to Vbb (~20VDC). Collector to load, then to ground. 1K
> > > > > > resistor (R1) pullup on Base to Vbb, and a second 1KR (R2) to the TTL
> > > > > > controller.
> > > > > >
> > > > > > Problem is of course, that R2 puts the ~20VDC to the TTL output gate on
> > > > > > a 74LS138.
> > > > > >
> > > > > > Trying to solve this without a driver transistor. The circuit is for a
> > > > > > 1ms ~20V strobe pulse repeated every ten ms.
> > > > > >
> > > > > > I thought of putting a 10ufd cap in series with R2, but don't like
> > > > > > electrolytics as they fail after a few thousand hours.
> > > > > >
> > > > > > Possible to use a 15V or so Zener Diode, but the Vbb is not regulated so
> > > > > > that won't work reliably.
> > > > > >
> > > > > > Anyone have a single component in mind that will essentially emulate
> > > > > > (isolate) an Open-Collector output for the 138?
> > > > > The TIP125 is a complementary dual.
> > > > it is? https://www.onsemi.com/pdf/datasheet/tip120-d.pdf
> > > Yeah it is. See Figure 1. All of that is in that TO-220 looking package.
> > and the three missing legs are where?
> >
> > TIP120, TIP121, TIP122 (NPN); is the right drawing
> >
> > TIP125, TIP126, TIP127 (PNP); is the left drawing
> STM has the version with both.

in a three pin to-220 ?

On Thursday, October 6, 2022 at 8:50:58 PM UTC-4, lang...@fonz.dk wrote:
> fredag den 7. oktober 2022 kl. 02.34.10 UTC+2 skrev Fred Bloggs:
> > On Thursday, October 6, 2022 at 12:17:08 PM UTC-4, lang...@fonz.dk wrote:
> > > torsdag den 6. oktober 2022 kl. 17.51.16 UTC+2 skrev Fred Bloggs:
> > > > On Thursday, October 6, 2022 at 11:37:46 AM UTC-4, lang...@fonz.dk wrote:
> > > > > torsdag den 6. oktober 2022 kl. 17.29.21 UTC+2 skrev Fred Bloggs:
> > > > > > On Thursday, October 6, 2022 at 2:24:33 AM UTC-4, John Robertson wrote:
> > > > > > > Have a circuit that needs repair. Uses a TIP125 (NPN, Darlington)
> > > > > > > emitter tied to Vbb (~20VDC). Collector to load, then to ground. 1K
> > > > > > > resistor (R1) pullup on Base to Vbb, and a second 1KR (R2) to the TTL
> > > > > > > controller.
> > > > > > >
> > > > > > > Problem is of course, that R2 puts the ~20VDC to the TTL output gate on
> > > > > > > a 74LS138.
> > > > > > >
> > > > > > > Trying to solve this without a driver transistor. The circuit is for a
> > > > > > > 1ms ~20V strobe pulse repeated every ten ms.
> > > > > > >
> > > > > > > I thought of putting a 10ufd cap in series with R2, but don't like
> > > > > > > electrolytics as they fail after a few thousand hours.
> > > > > > >
> > > > > > > Possible to use a 15V or so Zener Diode, but the Vbb is not regulated so
> > > > > > > that won't work reliably.
> > > > > > >
> > > > > > > Anyone have a single component in mind that will essentially emulate
> > > > > > > (isolate) an Open-Collector output for the 138?
> > > > > > The TIP125 is a complementary dual.
> > > > > it is? https://www.onsemi.com/pdf/datasheet/tip120-d.pdf
> > > > Yeah it is. See Figure 1. All of that is in that TO-220 looking package.
> > > and the three missing legs are where?
> > >
> > > TIP120, TIP121, TIP122 (NPN); is the right drawing
> > >
> > > TIP125, TIP126, TIP127 (PNP); is the left drawing
> > STM has the version with both.
> in a three pin to-220 ?

They need 5 pins + the heat sink tab for 6 total. It should read "dual complementary":
I must have misread it- not finding it now. Anyway- the TIP125 is a PNP and the TIP120 is its NPN complement- both Darlington. The simplest thing is acquire some TIP120, configure as CE with E GND'ed. Base directly to '138 OUT ( input is 8k which is high for LS and VOL, MAX way below 1V to even begin to turn on Darlington), C to 6.8kR to junction TIP125 B||1k existing base bleed. Figure 2 of typical VBE at even 100mA IC is 1.25V which is about what you would expect- and well within reach LS VOH standard TTL totem pole with some Schottky speedups and self limiting-no protection needed at this small loading. That's two parts, the TIP120 and 6.8kR. This is low power, he can hot melt the one TIP on top of the other, no daughter board necessary. Famous next to last words: It will be just fine. :-)
https://media.digikey.com/pdf/Data%20Sheets/ON%20Semiconductor%20PDFs/TIP120-22.pdf

Mouser has stock for $0.81 in qty <10.
Digikey has them for about same.
NTE TIP120- super widely available at any electronics store- sells for $1.00- that's the same as junk box part in hand.
https://www.nteinc.com/specs/original/TIP120.pdf

On Thursday, October 6, 2022 at 7:45:49 PM UTC-4, lang...@fonz.dk wrote:
> torsdag den 6. oktober 2022 kl. 18.35.18 UTC+2 skrev Ricky:
> > On Thursday, October 6, 2022 at 12:17:08 PM UTC-4, lang...@fonz.dk wrote:
> > > torsdag den 6. oktober 2022 kl. 17.51.16 UTC+2 skrev Fred Bloggs:
> > > > On Thursday, October 6, 2022 at 11:37:46 AM UTC-4, lang...@fonz.dk wrote:
> > > > > torsdag den 6. oktober 2022 kl. 17.29.21 UTC+2 skrev Fred Bloggs:
> > > > > > On Thursday, October 6, 2022 at 2:24:33 AM UTC-4, John Robertson wrote:
> > > > > > > Have a circuit that needs repair. Uses a TIP125 (NPN, Darlington)
> > > > > > > emitter tied to Vbb (~20VDC). Collector to load, then to ground. 1K
> > > > > > > resistor (R1) pullup on Base to Vbb, and a second 1KR (R2) to the TTL
> > > > > > > controller.
> > > > > > >
> > > > > > > Problem is of course, that R2 puts the ~20VDC to the TTL output gate on
> > > > > > > a 74LS138.
> > > > > > >
> > > > > > > Trying to solve this without a driver transistor. The circuit is for a
> > > > > > > 1ms ~20V strobe pulse repeated every ten ms.
> > > > > > >
> > > > > > > I thought of putting a 10ufd cap in series with R2, but don't like
> > > > > > > electrolytics as they fail after a few thousand hours.
> > > > > > >
> > > > > > > Possible to use a 15V or so Zener Diode, but the Vbb is not regulated so
> > > > > > > that won't work reliably.
> > > > > > >
> > > > > > > Anyone have a single component in mind that will essentially emulate
> > > > > > > (isolate) an Open-Collector output for the 138?
> > > > > > The TIP125 is a complementary dual.
> > > > > it is? https://www.onsemi.com/pdf/datasheet/tip120-d.pdf
> > > > Yeah it is. See Figure 1. All of that is in that TO-220 looking package.
> > > and the three missing legs are where?
> > >
> > > TIP120, TIP121, TIP122 (NPN); is the right drawing
> > >
> > > TIP125, TIP126, TIP127 (PNP); is the left drawing
> > It would seem a combination of a high side PNP driver and a low side NPN level shifter would be a useful, single package device. Is there a reason why this is hard to make on a single die?
> >
> what package would you put it in? you'd need more than 3 pins
>
> I think the closest is arrays like UDN2981

I was thinking of a package like the TO220 that is currently in the design, but with an extra pin. I've seen packages like that, some with five pins. I'm pretty sure only four pins are needed, in, out, power, ground.

The UDN2981 package might be too limiting for the power dissipation.

--

Rick C.

--- Get 1,000 miles of free Supercharging
--- Tesla referral code - https://ts.la/richard11209

On 2022-10-06, John Robertson <jrr@flippers.com> wrote:
> Have a circuit that needs repair. Uses a TIP125 (NPN, Darlington)
> emitter tied to Vbb (~20VDC). Collector to load, then to ground. 1K
> resistor (R1) pullup on Base to Vbb, and a second 1KR (R2) to the TTL
> controller.
>
> Problem is of course, that R2 puts the ~20VDC to the TTL output gate on
> a 74LS138.
>
> Trying to solve this without a driver transistor. The circuit is for a
> 1ms ~20V strobe pulse repeated every ten ms.
>
> I thought of putting a 10ufd cap in series with R2, but don't like
> electrolytics as they fail after a few thousand hours.
>
> Possible to use a 15V or so Zener Diode, but the Vbb is not regulated so
> that won't work reliably.
>
> Anyone have a single component in mind that will essentially emulate
> (isolate) an Open-Collector output for the 138?
>
> Thanks!
>
> John :-#)#
>

Yes,

Use a "digital" PNP transitor, base to VCC emitter to 138 output,
collector to the base resistor of the darlington

UNR221900L or similar.

--
Jasen.

On Thursday, October 6, 2022 at 9:30:55 PM UTC-7, Jasen Betts wrote:
> On 2022-10-06, John Robertson <j...@flippers.com> wrote:
> > Have a circuit that needs repair. Uses a TIP125 (NPN, Darlington)
> > emitter tied to Vbb (~20VDC).

(actually, PNP Darlington)

> > Anyone have a single component in mind that will essentially emulate
> > (isolate) an Open-Collector output for the 138?

> Use a "digital" PNP transitor, base to VCC emitter to 138 output,
> collector to the base resistor of the darlington
>
> UNR221900L or similar.

Um... the 138 going active low, you want that emitter to be of an NPN transistor,
not PNP.
For example, ROHM DTC124XE3 HZG
Although, with eight outputs to handle, a dual package might
be good, too.

On Thu, 6 Oct 2022 07:35:27 -0700, John Robertson <jrr@flippers.com>
wrote:

>On 2022/10/06 12:07 a.m., Lasse Langwadt Christensen wrote:
>> torsdag den 6. oktober 2022 kl. 08.24.33 UTC+2 skrev John Robertson:
>>> Have a circuit that needs repair. Uses a TIP125 (NPN, Darlington)
>>
>> PNP ..
>>
>>> emitter tied to Vbb (~20VDC). Collector to load, then to ground. 1K
>>> resistor (R1) pullup on Base to Vbb, and a second 1KR (R2) to the TTL
>>> controller.
>>>
>>> Problem is of course, that R2 puts the ~20VDC to the TTL output gate on
>>> a 74LS138.
>>>
>>> Trying to solve this without a driver transistor. The circuit is for a
>>> 1ms ~20V strobe pulse repeated every ten ms.
>>>
>>> I thought of putting a 10ufd cap in series with R2, but don't like
>>> electrolytics as they fail after a few thousand hours.
>>>
>>> Possible to use a 15V or so Zener Diode, but the Vbb is not regulated so
>>> that won't work reliably.
>>>
>>> Anyone have a single component in mind that will essentially emulate
>>> (isolate) an Open-Collector output for the 138?
>>>
>>
>> mosfet,
>> gate to 5V, source to 138, drain is your output
>
>Can't see that working...this is switching around 20V.
>
>Here is the circuit:
>https://www.flippers.com/images/delete/74LS138_Lamp_Driver.png
>
>What I want to do is add a single component in series with RC0/RC3/RC6's
>1KR to enable the 138 to drive the PNP TIP125 and isolate the output of
>the 138 when output is High. MOSFET could work, but switching surges
>might be excessive. Leaning towards making small PCB to convert 74LS138
>to original 7445 as the simplest solution. Space is a problem around the
>transistors you see, no room for additional drive transistors as this is
> finished PCB.
>
>Thanks,
>
>John :-#)#

Driving the fet source from the 138 will isolate the 138 from the
higher voltage. Fet gate at 138 VCC.

RL

On Thursday, October 6, 2022 at 10:50:15 AM UTC-4, John Larkin wrote:

<snip gibberish>

> That's not clear. Got a schematic?
> >

He's wasting his time, there's nothing wrong with the original circuit.

He's just one of those people who, when they can't understand something, think something is wrong.
LS doesn't have ESD clamp diodes on its outputs, and, in fact, nothing is being avalanched by applying a very current limited 20V to its outputs. Maybe an insignificant elevated leakage is all that happens. The original circuit is well-designed and should be left as is.

On 06/10/2022 07:24, John Robertson wrote:
> Have a circuit that needs repair. Uses a TIP125 (NPN, Darlington)
> emitter tied to Vbb (~20VDC). Collector to load, then to ground. 1K
> resistor (R1) pullup on Base to Vbb, and a second 1KR (R2) to the TTL
> controller.
>
> Problem is of course, that R2 puts the ~20VDC to the TTL output gate on
> a 74LS138.
>
> Trying to solve this without a driver transistor. The circuit is for a
> 1ms ~20V strobe pulse repeated every ten ms.
>
> I thought of putting a 10ufd cap in series with R2, but don't like
> electrolytics as they fail after a few thousand hours.
>
> Possible to use a 15V or so Zener Diode, but the Vbb is not regulated so
> that won't work reliably.
>
> Anyone have a single component in mind that will essentially emulate
> (isolate) an Open-Collector output for the 138?
>
> Thanks!
>
> John :-#)#
>

You can probably omit the R1 E-B resistor, 1k is rather low and all the
TIP125 I saw had on-chip E-B resistors to soak up and leakage currents.

The base drive resistor R2 is also very low value, 1k at 20V is 20mA
which while within 7445 spec is way above the 8mA Iol of 74LS parts. The
darlington has minimum current gain of 1000 so I am sure you can use
very much lower base drive.

If you get base drive to a couple hundred uA then a series 0.47uF cap
could solve the level shift problem. Otherwise you could try lifting the
base end of R2 and wiring an NPN in series - so collector of NPN drives
darlington base and emitter of NPN goes via R2 to the TTL output. The
buss all the bases together to the TTL 5Vcc. 4mA drive should be enough
for up to 4A of lamp loads. The resistor R2 in series with the TTL
output will also cushion the TTL output against the stored charge spikes
Phil Hobbs pointed out.

piglet

On Friday, 7 October 2022 at 18:25:51 UTC+1, Fred Bloggs wrote:
> On Thursday, October 6, 2022 at 10:50:15 AM UTC-4, John Larkin wrote:
>
> <snip gibberish>
> > That's not clear. Got a schematic?
> > >
> He's wasting his time, there's nothing wrong with the original circuit.
>
> He's just one of those people who, when they can't understand something, think something is wrong.
> LS doesn't have ESD clamp diodes on its outputs, and, in fact, nothing is being avalanched by applying a very current limited 20V to its outputs. Maybe an insignificant elevated leakage is all that happens. The original circuit is well-designed and should be left as is.

I can see that the original circuit might work fine, but it does depend on parameters that
are not specified in the data sheet like the breakdown voltage of the output pull-down
transistor, so I wouldn't be comfortable calling it "well designed".

John

John Walliker wrote:
> On Friday, 7 October 2022 at 18:25:51 UTC+1, Fred Bloggs wrote:
>> On Thursday, October 6, 2022 at 10:50:15 AM UTC-4, John Larkin
>> wrote:
>>
>> <snip gibberish>
>>> That's not clear. Got a schematic?
>>>>
>> He's wasting his time, there's nothing wrong with the original
>> circuit.
>>
>> He's just one of those people who, when they can't understand
>> something, think something is wrong. LS doesn't have ESD clamp
>> diodes on its outputs, and, in fact, nothing is being avalanched by
>> applying a very current limited 20V to its outputs. Maybe an
>> insignificant elevated leakage is all that happens. The original
>> circuit is well-designed and should be left as is.
>
> I can see that the original circuit might work fine, but it does
> depend on parameters that are not specified in the data sheet like
> the breakdown voltage of the output pull-down transistor, so I
> wouldn't be comfortable calling it "well designed".
>
> John
>

I'd also be worried about zenering the B-E junction of the top transistor.

Probably fine for a hobby project, but not for a mission-critical
application such as a pinball table in a bar. ;)

Cheers

Phil Hobbs

(Those wizards can cut up rough if their favourite table isn't working.)

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510

http://electrooptical.net
http://hobbs-eo.com

On Friday, October 7, 2022 at 4:41:24 PM UTC-4, John Walliker wrote:
> On Friday, 7 October 2022 at 18:25:51 UTC+1, Fred Bloggs wrote:
> > On Thursday, October 6, 2022 at 10:50:15 AM UTC-4, John Larkin wrote:
> >
> > <snip gibberish>
> > > That's not clear. Got a schematic?
> > > >
> > He's wasting his time, there's nothing wrong with the original circuit.
> >
> > He's just one of those people who, when they can't understand something, think something is wrong.
> > LS doesn't have ESD clamp diodes on its outputs, and, in fact, nothing is being avalanched by applying a very current limited 20V to its outputs. Maybe an insignificant elevated leakage is all that happens. The original circuit is well-designed and should be left as is.
> I can see that the original circuit might work fine, but it does depend on parameters that
> are not specified in the data sheet like the breakdown voltage of the output pull-down
> transistor, so I wouldn't be comfortable calling it "well designed".

Well I would and here's why. The ultra-fast (for its day) rise/fall times of the logic family brought transmission line effects into standard logic design. If the typical LS output gate transitioned a typical high impedance interconnecting trace to 5V, and that 5V pulse meets a high impedance input of another LS gate as its only load. The signal will be reflected 100% positively for 5V traveling back down the trace to the driver. Since the driver pulled high is high impedance, the returning pulse again is reflected positively 100% making the voltage at the driver output 10V. The new +5V transition sends a 10V edge traveling down the line to the LS input and gets clamped at 5V which is a full negative reflection to return back to the driver and reduce the 10V at the output node ideally to 5V etc. So we know for a *fact* the process has to be designed to withstand a repetitive 10V applied to the output. And that's not just withstand to survive, that's withstand with no internal circuit disruption. Typical margins are factor of 2x or more, making a withstanding voltage of 20V a done deal, and that can be verified for the part. That's why I'm saying it's a good design.

>
> John

On Friday, October 7, 2022 at 4:41:24 PM UTC-4, John Walliker wrote:
> On Friday, 7 October 2022 at 18:25:51 UTC+1, Fred Bloggs wrote:
> > On Thursday, October 6, 2022 at 10:50:15 AM UTC-4, John Larkin wrote:
> >
> > <snip gibberish>
> > > That's not clear. Got a schematic?
> > > >
> > He's wasting his time, there's nothing wrong with the original circuit.
> >
> > He's just one of those people who, when they can't understand something, think something is wrong.
> > LS doesn't have ESD clamp diodes on its outputs, and, in fact, nothing is being avalanched by applying a very current limited 20V to its outputs. Maybe an insignificant elevated leakage is all that happens. The original circuit is well-designed and should be left as is.
> I can see that the original circuit might work fine, but it does depend on parameters that
> are not specified in the data sheet like the breakdown voltage of the output pull-down
> transistor, so I wouldn't be comfortable calling it "well designed".

I think you mean the lack of absolute maximum ratings for the outputs, as I'm sure they never expected anyone to think it would be safe to treat a totem pole output to be treated as an open collector.

--

Rick C.

--+ Get 1,000 miles of free Supercharging
--+ Tesla referral code - https://ts.la/richard11209

On Friday, October 7, 2022 at 7:10:22 PM UTC-4, Fred Bloggs wrote:
> On Friday, October 7, 2022 at 4:41:24 PM UTC-4, John Walliker wrote:
> > On Friday, 7 October 2022 at 18:25:51 UTC+1, Fred Bloggs wrote:
> > > On Thursday, October 6, 2022 at 10:50:15 AM UTC-4, John Larkin wrote:
> > >
> > > <snip gibberish>
> > > > That's not clear. Got a schematic?
> > > > >
> > > He's wasting his time, there's nothing wrong with the original circuit.
> > >
> > > He's just one of those people who, when they can't understand something, think something is wrong.
> > > LS doesn't have ESD clamp diodes on its outputs, and, in fact, nothing is being avalanched by applying a very current limited 20V to its outputs.. Maybe an insignificant elevated leakage is all that happens. The original circuit is well-designed and should be left as is.
> > I can see that the original circuit might work fine, but it does depend on parameters that
> > are not specified in the data sheet like the breakdown voltage of the output pull-down
> > transistor, so I wouldn't be comfortable calling it "well designed".
> Well I would and here's why. The ultra-fast (for its day) rise/fall times of the logic family brought transmission line effects into standard logic design. If the typical LS output gate transitioned a typical high impedance interconnecting trace to 5V, and that 5V pulse meets a high impedance input of another LS gate as its only load. The signal will be reflected 100% positively for 5V traveling back down the trace to the driver. Since the driver pulled high is high impedance, the returning pulse again is reflected positively 100% making the voltage at the driver output 10V. The new +5V transition sends a 10V edge traveling down the line to the LS input and gets clamped at 5V which is a full negative reflection to return back to the driver and reduce the 10V at the output node ideally to 5V etc. So we know for a *fact* the process has to be designed to withstand a repetitive 10V applied to the output. And that's not just withstand to survive, that's withstand with no internal circuit disruption. Typical margins are factor of 2x or more, making a withstanding voltage of 20V a done deal, and that can be verified for the part. That's why I'm saying it's a good design.

I thought I was following this ok, until I got to the point of the second wave being clamped at the LS input to the 5V rail. Is that were the case, how could the first reflection be above 5V?

That aside, your whole description is pretty off track. The LS output driving the "high impedance" trace, does not pull up to 5V in the first place. The "high impedance" trace is not high enough to be ignored. The reality is the driver output will only drive hard to maybe 3.5V. Combine that with the trace impedance loading of around 110 ohms, and you get something like a 2V initial edge on the trace. This will be doubled at the far end reflection at the LS input, to about 4V. So there's no need to worry about over voltage from reflections.

It's been too many years since I've looked at waveforms of LSTTL signals on a scope. When I was looking at TTL signals, people didn't understand impedance matching very widely. But things worked pretty well without terminations. It was later that higher clock rates were attempted and people finally figured out that the signals were not reaching the other end of the trace perfectly when there was more than one receiver. Also, CMOS.

--

Rick C.

-+- Get 1,000 miles of free Supercharging
-+- Tesla referral code - https://ts.la/richard11209

On Friday, October 7, 2022 at 4:10:22 PM UTC-7, Fred Bloggs wrote:
> On Friday, October 7, 2022 at 4:41:24 PM UTC-4, John Walliker wrote:
> > On Friday, 7 October 2022 at 18:25:51 UTC+1, Fred Bloggs wrote:

> > > LS doesn't have ESD clamp diodes on its outputs, and, in fact, nothing is being
> > >avalanched by applying a very current limited 20V to its outputs. Maybe an insignificant
> > >elevated leakage is all that happens. The original circuit is well-designed and should be left as is.

> > I can see that the original circuit might work fine, but it does depend on parameters that
> > are not specified in the data sheet like the breakdown voltage of the output pull-down
> > transistor, so I wouldn't be comfortable calling it "well designed".

> Well I would and here's why. The ultra-fast (for its day) rise/fall times of the logic family brought
> transmission line effects into standard logic design. If the typical LS output gate transitioned
>a typical high impedance interconnecting trace to 5V, and that 5V pulse meets a high
>impedance input of another LS gate as its only load. The signal will be reflected 100% positively ...

>Typical margins are factor of 2x or more, making a withstanding voltage of 20V
>a done deal, and that can be verified for the part. That's why I'm saying it's a good design.

Actually, would substituting a 74HCT138 or 74ACT138 be a good solution?
There's certainly protection diodes built into its outputs (MOS body diode).
74ACT138 can take 50 mA into its output pin.

<https://www.ti.com/lit/ds/symlink/cd74act138.pdf>

On Saturday, 8 October 2022 at 05:07:50 UTC+1, whit3rd wrote:
> On Friday, October 7, 2022 at 4:10:22 PM UTC-7, Fred Bloggs wrote:
> > On Friday, October 7, 2022 at 4:41:24 PM UTC-4, John Walliker wrote:
> > > On Friday, 7 October 2022 at 18:25:51 UTC+1, Fred Bloggs wrote:
>
> > > > LS doesn't have ESD clamp diodes on its outputs, and, in fact, nothing is being
> > > >avalanched by applying a very current limited 20V to its outputs. Maybe an insignificant
> > > >elevated leakage is all that happens. The original circuit is well-designed and should be left as is.
>
> > > I can see that the original circuit might work fine, but it does depend on parameters that
> > > are not specified in the data sheet like the breakdown voltage of the output pull-down
> > > transistor, so I wouldn't be comfortable calling it "well designed".
>
> > Well I would and here's why. The ultra-fast (for its day) rise/fall times of the logic family brought
> > transmission line effects into standard logic design. If the typical LS output gate transitioned
> >a typical high impedance interconnecting trace to 5V, and that 5V pulse meets a high
> >impedance input of another LS gate as its only load. The signal will be reflected 100% positively ...
> >Typical margins are factor of 2x or more, making a withstanding voltage of 20V
> >a done deal, and that can be verified for the part. That's why I'm saying it's a good design.
> Actually, would substituting a 74HCT138 or 74ACT138 be a good solution?
> There's certainly protection diodes built into its outputs (MOS body diode).
> 74ACT138 can take 50 mA into its output pin.
>
> <https://www.ti.com/lit/ds/symlink/cd74act138.pdf>

The problem with that is that the darlington would never turn off.

John

On Saturday, 8 October 2022 at 02:52:12 UTC+1, Ricky wrote:
> On Friday, October 7, 2022 at 7:10:22 PM UTC-4, Fred Bloggs wrote:
> > On Friday, October 7, 2022 at 4:41:24 PM UTC-4, John Walliker wrote:
> > > On Friday, 7 October 2022 at 18:25:51 UTC+1, Fred Bloggs wrote:
> > > > On Thursday, October 6, 2022 at 10:50:15 AM UTC-4, John Larkin wrote:
> > > >
> > > > <snip gibberish>
> > > > > That's not clear. Got a schematic?
> > > > > >
> > > > He's wasting his time, there's nothing wrong with the original circuit.
> > > >
> > > > He's just one of those people who, when they can't understand something, think something is wrong.
> > > > LS doesn't have ESD clamp diodes on its outputs, and, in fact, nothing is being avalanched by applying a very current limited 20V to its outputs. Maybe an insignificant elevated leakage is all that happens. The original circuit is well-designed and should be left as is.
> > > I can see that the original circuit might work fine, but it does depend on parameters that
> > > are not specified in the data sheet like the breakdown voltage of the output pull-down
> > > transistor, so I wouldn't be comfortable calling it "well designed".
> > Well I would and here's why. The ultra-fast (for its day) rise/fall times of the logic family brought transmission line effects into standard logic design. If the typical LS output gate transitioned a typical high impedance interconnecting trace to 5V, and that 5V pulse meets a high impedance input of another LS gate as its only load. The signal will be reflected 100% positively for 5V traveling back down the trace to the driver. Since the driver pulled high is high impedance, the returning pulse again is reflected positively 100% making the voltage at the driver output 10V. The new +5V transition sends a 10V edge traveling down the line to the LS input and gets clamped at 5V which is a full negative reflection to return back to the driver and reduce the 10V at the output node ideally to 5V etc. So we know for a *fact* the process has to be designed to withstand a repetitive 10V applied to the output. And that's not just withstand to survive, that's withstand with no internal circuit disruption. Typical margins are factor of 2x or more, making a withstanding voltage of 20V a done deal, and that can be verified for the part. That's why I'm saying it's a good design.
> I thought I was following this ok, until I got to the point of the second wave being clamped at the LS input to the 5V rail. Is that were the case, how could the first reflection be above 5V?
>
> That aside, your whole description is pretty off track. The LS output driving the "high impedance" trace, does not pull up to 5V in the first place. The "high impedance" trace is not high enough to be ignored. The reality is the driver output will only drive hard to maybe 3.5V. Combine that with the trace impedance loading of around 110 ohms, and you get something like a 2V initial edge on the trace. This will be doubled at the far end reflection at the LS input, to about 4V. So there's no need to worry about over voltage from reflections.
>
> It's been too many years since I've looked at waveforms of LSTTL signals on a scope. When I was looking at TTL signals, people didn't understand impedance matching very widely. But things worked pretty well without terminations. It was later that higher clock rates were attempted and people finally figured out that the signals were not reaching the other end of the trace perfectly when there was more than one receiver. Also, CMOS.
>
It has been many years for me too. I spent several months in 1974 building
prototype digital television equipment using 74S devices. I don't recall ever
seeing overshoots of more than about 6V. I had access to excellent test equipment.
However, this was all hand-wired on perforated Veroboard and any signals going
more than a couple of cm were wired as twisted pair. Every chip usually had its own
decoupling capacitor, chosen for low Q so as to absorb switching transients..

John

On 2022/10/08 2:54 a.m., John Walliker wrote:
> On Saturday, 8 October 2022 at 05:07:50 UTC+1, whit3rd wrote:
>> On Friday, October 7, 2022 at 4:10:22 PM UTC-7, Fred Bloggs wrote:
>>> On Friday, October 7, 2022 at 4:41:24 PM UTC-4, John Walliker wrote:
>>>> On Friday, 7 October 2022 at 18:25:51 UTC+1, Fred Bloggs wrote:
>>
>>>>> LS doesn't have ESD clamp diodes on its outputs, and, in fact, nothing is being
>>>>> avalanched by applying a very current limited 20V to its outputs. Maybe an insignificant
>>>>> elevated leakage is all that happens. The original circuit is well-designed and should be left as is.
>>
>>>> I can see that the original circuit might work fine, but it does depend on parameters that
>>>> are not specified in the data sheet like the breakdown voltage of the output pull-down
>>>> transistor, so I wouldn't be comfortable calling it "well designed".
>>
>>> Well I would and here's why. The ultra-fast (for its day) rise/fall times of the logic family brought
>>> transmission line effects into standard logic design. If the typical LS output gate transitioned
>>> a typical high impedance interconnecting trace to 5V, and that 5V pulse meets a high
>>> impedance input of another LS gate as its only load. The signal will be reflected 100% positively ...
>>> Typical margins are factor of 2x or more, making a withstanding voltage of 20V
>>> a done deal, and that can be verified for the part. That's why I'm saying it's a good design.
>> Actually, would substituting a 74HCT138 or 74ACT138 be a good solution?
>> There's certainly protection diodes built into its outputs (MOS body diode).
>> 74ACT138 can take 50 mA into its output pin.
>>
>> <https://www.ti.com/lit/ds/symlink/cd74act138.pdf>
>
> The problem with that is that the darlington would never turn off.
>
> John

Which is why we went back to the original 7445 device for this small run
(Rotation 8 pinball by Midway) replacement MPU board. The open-collector
was needed for allowing the TIP125 to turn off...we are going to make a
simple tiny sub-board to sub the 7445 in for the 138 and use a couple of
extra gates on the MPU to get the select logic right. The initial run
was five PCBs, the next run will have the fix built in of course.

Thanks for all the ideas folks - appreciate your efforts! Reworking
1970s tech can be fun!

John :-#)#
--
(Please post followups or tech inquiries to the USENET newsgroup)
John's Jukes Ltd.
MOVED to #7 - 3979 Marine Way, Burnaby, BC, Canada V5J 5E3
(604)872-5757 (Pinballs, Jukes, Video Games)
www.flippers.com
"Old pinballers never die, they just flip out."

On Friday, October 7, 2022 at 9:52:12 PM UTC-4, Ricky wrote:
> On Friday, October 7, 2022 at 7:10:22 PM UTC-4, Fred Bloggs wrote:
> > On Friday, October 7, 2022 at 4:41:24 PM UTC-4, John Walliker wrote:
> > > On Friday, 7 October 2022 at 18:25:51 UTC+1, Fred Bloggs wrote:
> > > > On Thursday, October 6, 2022 at 10:50:15 AM UTC-4, John Larkin wrote:
> > > >
> > > > <snip gibberish>
> > > > > That's not clear. Got a schematic?
> > > > > >
> > > > He's wasting his time, there's nothing wrong with the original circuit.
> > > >
> > > > He's just one of those people who, when they can't understand something, think something is wrong.
> > > > LS doesn't have ESD clamp diodes on its outputs, and, in fact, nothing is being avalanched by applying a very current limited 20V to its outputs. Maybe an insignificant elevated leakage is all that happens. The original circuit is well-designed and should be left as is.
> > > I can see that the original circuit might work fine, but it does depend on parameters that
> > > are not specified in the data sheet like the breakdown voltage of the output pull-down
> > > transistor, so I wouldn't be comfortable calling it "well designed".
> > Well I would and here's why. The ultra-fast (for its day) rise/fall times of the logic family brought transmission line effects into standard logic design. If the typical LS output gate transitioned a typical high impedance interconnecting trace to 5V, and that 5V pulse meets a high impedance input of another LS gate as its only load. The signal will be reflected 100% positively for 5V traveling back down the trace to the driver. Since the driver pulled high is high impedance, the returning pulse again is reflected positively 100% making the voltage at the driver output 10V. The new +5V transition sends a 10V edge traveling down the line to the LS input and gets clamped at 5V which is a full negative reflection to return back to the driver and reduce the 10V at the output node ideally to 5V etc. So we know for a *fact* the process has to be designed to withstand a repetitive 10V applied to the output. And that's not just withstand to survive, that's withstand with no internal circuit disruption. Typical margins are factor of 2x or more, making a withstanding voltage of 20V a done deal, and that can be verified for the part. That's why I'm saying it's a good design.
> I thought I was following this ok, until I got to the point of the second wave being clamped at the LS input to the 5V rail. Is that were the case, how could the first reflection be above 5V?
>
> That aside, your whole description is pretty off track. The LS output driving the "high impedance" trace, does not pull up to 5V in the first place. The "high impedance" trace is not high enough to be ignored. The reality is the driver output will only drive hard to maybe 3.5V. Combine that with the trace impedance loading of around 110 ohms, and you get something like a 2V initial edge on the trace. This will be doubled at the far end reflection at the LS input, to about 4V. So there's no need to worry about over voltage from reflections.

Not going to get into those details. Theoretically your 4V return pulse would get doubled to 8V at the LS OUT pin, but it doesn't, and here's why. When the LS totem pole gets pushed into back bias, its current is immediately cut off, inducing the superposition of a 2.0V negative going pulse on the line. So the 4V incoming combined with that gets you back to your original 2V, and then the load sees a negative 2V step one line length delay later.

Stuff like shows why you're okay using unterminated lines most of the time for combinatorial inputs- it's the clocked inputs that are the weak link, unterminated line reflections cause the infamous glitchy double clocking problems. TTL drive levels are too weak for a DC termination but they're good enough for an AC termination. The AC termination is a series R+C shunting the line to signal COM at the load. The R is the interconnecting trace/wire characteristic impedance, and C is selected for an RC time constant equal to signal transition time. That one works pretty well. It's only needed in extreme situations where the line has to be run over 18" or so for some reason.

>
> It's been too many years since I've looked at waveforms of LSTTL signals on a scope. When I was looking at TTL signals, people didn't understand impedance matching very widely. But things worked pretty well without terminations. It was later that higher clock rates were attempted and people finally figured out that the signals were not reaching the other end of the trace perfectly when there was more than one receiver. Also, CMOS.
>
> --
>
> Rick C.
>
> -+- Get 1,000 miles of free Supercharging
> -+- Tesla referral code - https://ts.la/richard11209

Fred Bloggs wrote:
> On Friday, October 7, 2022 at 4:41:24 PM UTC-4, John Walliker wrote:
>> On Friday, 7 October 2022 at 18:25:51 UTC+1, Fred Bloggs wrote:
>>> On Thursday, October 6, 2022 at 10:50:15 AM UTC-4, John Larkin
>>> wrote:
>>>
>>> <snip gibberish>
>>>> That's not clear. Got a schematic?
>>>>>
>>> He's wasting his time, there's nothing wrong with the original
>>> circuit.
>>>
>>> He's just one of those people who, when they can't understand
>>> something, think something is wrong. LS doesn't have ESD clamp
>>> diodes on its outputs, and, in fact, nothing is being avalanched
>>> by applying a very current limited 20V to its outputs. Maybe an
>>> insignificant elevated leakage is all that happens. The original
>>> circuit is well-designed and should be left as is.
>> I can see that the original circuit might work fine, but it does
>> depend on parameters that are not specified in the data sheet like
>> the breakdown voltage of the output pull-down transistor, so I
>> wouldn't be comfortable calling it "well designed".
>
> Well I would and here's why. The ultra-fast (for its day) rise/fall
> times of the logic family brought transmission line effects into
> standard logic design.

Don't know that I've ever seen "LS TTL" and "ultrafast" in the same
connection. ;)

> If the typical LS output gate transitioned a typical high impedance
> interconnecting trace to 5V, and that 5V pulse meets a high
> impedance input of another LS gate as its only load. The signal will
> be reflected 100% positively for 5V traveling back down the trace to
> the driver. Since the driver pulled high is high impedance, the
> returning pulse again is reflected positively 100% making the voltage
> at the driver output 10V.

In real life it's never that bad. LS doesn't drive heavy loads (i.e.
50-100 ohms) very fast in the positive direction, and the ~10 ns edges
mean that a normal-size board is too small to give that much
overshoot--the rise is still going on at the driver when the reflection
arrives.

> The new +5V transition sends a 10V edge traveling down the line to
> the LS input and gets clamped at 5V which is a full negative
> reflection to return back to the driver and reduce the 10V at the
> output node ideally to 5V etc. So we know for a *fact* the process
> has to be designed to withstand a repetitive 10V applied to the
> output.

Nah.

> And that's not just withstand to survive, that's withstand with no
> internal circuit disruption. Typical margins are factor of 2x or
> more, making a withstanding voltage of 20V a done deal, and that can
> be verified for the part. That's why I'm saying it's a good design.

Your average NPN BE junction avalanches at about 6V, leading to
progressively reduced beta as well as current loading. The duty cycles
of the lights on that machine are probably less than 50%, so it'll be in
avalanche most of the time.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510

http://electrooptical.net
http://hobbs-eo.com