In one hand-wired proto recently,(*) I was using an LM319N
open-collector dual comparator to drive the !set and !clear inputs of
one section of a 74VHC74A dflop.

The 319 was running off +-15V. By mistake, I wired the pull-up resistor
on one section to +15 rather than +5. The circuit worked perfectly--I
only noticed the blunder when I went to make a slight change to the ramp
current source.

Abs max on both VDD and any input is +7V, which appears to be a fairly
absurd underestimate of what the !clear input can comfortably manage, at
least for a day or two. It didn't seem to be drawing any input current,
either--at most a few dozen microamps.

Cheers

Phil Hobbs

(*) It was that highly linear ramp generator I was talking about in
another thread. Swapping out the mylar cap for a polypropylene reduced
the soakage tail on the ramp, but didn't eliminate it.

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510

http://electrooptical.net
http://hobbs-eo.com

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510

http://electrooptical.net
http://hobbs-eo.com

On Sun, 29 Jan 2023 16:43:36 -0500, Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:

>
>In one hand-wired proto recently,(*) I was using an LM319N
>open-collector dual comparator to drive the !set and !clear inputs of
>one section of a 74VHC74A dflop.
>
>The 319 was running off +-15V. By mistake, I wired the pull-up resistor
>on one section to +15 rather than +5. The circuit worked perfectly--I
>only noticed the blunder when I went to make a slight change to the ramp
>current source.
>
>Abs max on both VDD and any input is +7V, which appears to be a fairly
>absurd underestimate of what the !clear input can comfortably manage, at
>least for a day or two. It didn't seem to be drawing any input current,
>either--at most a few dozen microamps.
>
>Cheers
>
>Phil Hobbs
>
>(*) It was that highly linear ramp generator I was talking about in
>another thread. Swapping out the mylar cap for a polypropylene reduced
>the soakage tail on the ramp, but didn't eliminate it.
>
>--
>Dr Philip C D Hobbs
>Principal Consultant
>ElectroOptical Innovations LLC / Hobbs ElectroOptics
>Optics, Electro-optics, Photonics, Analog Electronics
>Briarcliff Manor NY 10510
>
>http://electrooptical.net
>http://hobbs-eo.com

The upper ESD diode in the 74VHC74A is essentially a zener to ground,
not a pn diode to Vcc. One could test one to see where it actually
zeners.

Mylar caps make terrible ramps.

I like to test parts past abs max to see what happens. It's rare to
find a part that won't tolerate 2x abs max voltage, and 5:1 isn't
unusual.

John Larkin wrote:
> On Sun, 29 Jan 2023 16:43:36 -0500, Phil Hobbs
> <pcdhSpamMeSenseless@electrooptical.net> wrote:
>
>>
>> In one hand-wired proto recently,(*) I was using an LM319N
>> open-collector dual comparator to drive the !set and !clear inputs of
>> one section of a 74VHC74A dflop.
>>
>> The 319 was running off +-15V. By mistake, I wired the pull-up resistor
>> on one section to +15 rather than +5. The circuit worked perfectly--I
>> only noticed the blunder when I went to make a slight change to the ramp
>> current source.
>>
>> Abs max on both VDD and any input is +7V, which appears to be a fairly
>> absurd underestimate of what the !clear input can comfortably manage, at
>> least for a day or two. It didn't seem to be drawing any input current,
>> either--at most a few dozen microamps.
>>
>> Cheers
>>
>> Phil Hobbs
>>
>> (*) It was that highly linear ramp generator I was talking about in
>> another thread. Swapping out the mylar cap for a polypropylene reduced
>> the soakage tail on the ramp, but didn't eliminate it.
>
>
> The upper ESD diode in the 74VHC74A is essentially a zener to ground,
> not a pn diode to Vcc. One could test one to see where it actually
> zeners.
>
> Mylar caps make terrible ramps.

Mylar isn't too bad at this speed (1-100 Hz). The original version of
this circuit had about a 200 us reset pulse, controlling the gate of a
2N7002 directly. The capacitor was a 330 nF, 200V mylar, and the
discharge arrangement was that 2N7002 with a 20-ohm resistor in series.
The ramp reset pulse was about 200 us, i.e. about 15 time constants.
There was about a 2-ms tail following the reset. The polyprop ones are
probably 3x tighter, but not orders of magnitude.

I have some polystyrenes in my drawer, but they're only available up to
the early nanofarads. (I have a few NOS ones up to 10 nF.)

I made a little RC differentiator gizmo with a polystyrene cap and an
OPA141, and verified that the rest of the ramp was linear to better than
12 bits, which was about the limit of the measurement. Making the reset
pulse 10 ms wide fixed it completely.

> I like to test parts past abs max to see what happens. It's rare to
> find a part that won't tolerate 2x abs max voltage, and 5:1 isn't
> unusual.

Seems like the chip makers decide how tight they can make the spec
without hurting sales.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510

http://electrooptical.net
http://hobbs-eo.com

On Sun, 29 Jan 2023 19:32:32 -0500, Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:

>John Larkin wrote:
>> On Sun, 29 Jan 2023 16:43:36 -0500, Phil Hobbs
>> <pcdhSpamMeSenseless@electrooptical.net> wrote:
>>
>>>
>>> In one hand-wired proto recently,(*) I was using an LM319N
>>> open-collector dual comparator to drive the !set and !clear inputs of
>>> one section of a 74VHC74A dflop.
>>>
>>> The 319 was running off +-15V. By mistake, I wired the pull-up resistor
>>> on one section to +15 rather than +5. The circuit worked perfectly--I
>>> only noticed the blunder when I went to make a slight change to the ramp
>>> current source.
>>>
>>> Abs max on both VDD and any input is +7V, which appears to be a fairly
>>> absurd underestimate of what the !clear input can comfortably manage, at
>>> least for a day or two. It didn't seem to be drawing any input current,
>>> either--at most a few dozen microamps.
>>>
>>> Cheers
>>>
>>> Phil Hobbs
>>>
>>> (*) It was that highly linear ramp generator I was talking about in
>>> another thread. Swapping out the mylar cap for a polypropylene reduced
>>> the soakage tail on the ramp, but didn't eliminate it.
>>
>>
>> The upper ESD diode in the 74VHC74A is essentially a zener to ground,
>> not a pn diode to Vcc. One could test one to see where it actually
>> zeners.
>>
>> Mylar caps make terrible ramps.
>
>Mylar isn't too bad at this speed (1-100 Hz). The original version of
>this circuit had about a 200 us reset pulse, controlling the gate of a
>2N7002 directly. The capacitor was a 330 nF, 200V mylar, and the
>discharge arrangement was that 2N7002 with a 20-ohm resistor in series.
>The ramp reset pulse was about 200 us, i.e. about 15 time constants.
>There was about a 2-ms tail following the reset. The polyprop ones are
>probably 3x tighter, but not orders of magnitude.
>
>I have some polystyrenes in my drawer, but they're only available up to
>the early nanofarads. (I have a few NOS ones up to 10 nF.)
>
>I made a little RC differentiator gizmo with a polystyrene cap and an
>OPA141, and verified that the rest of the ramp was linear to better than
>12 bits, which was about the limit of the measurement. Making the reset
>pulse 10 ms wide fixed it completely.
>
>> I like to test parts past abs max to see what happens. It's rare to
>> find a part that won't tolerate 2x abs max voltage, and 5:1 isn't
>> unusual.
>
>Seems like the chip makers decide how tight they can make the spec
>without hurting sales.
>
>Cheers
>
>Phil Hobbs

Some engineers are reluctant to run parts at abs max, so guardband
down. I figure the manufacturer has already guardbanded.

One interesting case is reverse biasing polarized capacitors, which is
rarely specified.

Another is RF parts, where the abs max voltage is often the max
suggested supply max, and it's assumed but not stated that the actual
drain voltage will swing to 2x the supply.

John Larkin wrote:
> On Sun, 29 Jan 2023 19:32:32 -0500, Phil Hobbs
> <pcdhSpamMeSenseless@electrooptical.net> wrote:
>
>> John Larkin wrote:
>>> On Sun, 29 Jan 2023 16:43:36 -0500, Phil Hobbs
>>> <pcdhSpamMeSenseless@electrooptical.net> wrote:
>>>
>>>>
>>>> In one hand-wired proto recently,(*) I was using an LM319N
>>>> open-collector dual comparator to drive the !set and !clear inputs of
>>>> one section of a 74VHC74A dflop.
>>>>
>>>> The 319 was running off +-15V. By mistake, I wired the pull-up resistor
>>>> on one section to +15 rather than +5. The circuit worked perfectly--I
>>>> only noticed the blunder when I went to make a slight change to the ramp
>>>> current source.
>>>>
>>>> Abs max on both VDD and any input is +7V, which appears to be a fairly
>>>> absurd underestimate of what the !clear input can comfortably manage, at
>>>> least for a day or two. It didn't seem to be drawing any input current,
>>>> either--at most a few dozen microamps.
>>>>
>>>> Cheers
>>>>
>>>> Phil Hobbs
>>>>
>>>> (*) It was that highly linear ramp generator I was talking about in
>>>> another thread. Swapping out the mylar cap for a polypropylene reduced
>>>> the soakage tail on the ramp, but didn't eliminate it.
>>>
>>>
>>> The upper ESD diode in the 74VHC74A is essentially a zener to ground,
>>> not a pn diode to Vcc. One could test one to see where it actually
>>> zeners.
>>>
>>> Mylar caps make terrible ramps.
>>
>> Mylar isn't too bad at this speed (1-100 Hz). The original version of
>> this circuit had about a 200 us reset pulse, controlling the gate of a
>> 2N7002 directly. The capacitor was a 330 nF, 200V mylar, and the
>> discharge arrangement was that 2N7002 with a 20-ohm resistor in series.
>> The ramp reset pulse was about 200 us, i.e. about 15 time constants.
>> There was about a 2-ms tail following the reset. The polyprop ones are
>> probably 3x tighter, but not orders of magnitude.
>>
>> I have some polystyrenes in my drawer, but they're only available up to
>> the early nanofarads. (I have a few NOS ones up to 10 nF.)
>>
>> I made a little RC differentiator gizmo with a polystyrene cap and an
>> OPA141, and verified that the rest of the ramp was linear to better than
>> 12 bits, which was about the limit of the measurement. Making the reset
>> pulse 10 ms wide fixed it completely.
>>
>>> I like to test parts past abs max to see what happens. It's rare to
>>> find a part that won't tolerate 2x abs max voltage, and 5:1 isn't
>>> unusual.
>>
>> Seems like the chip makers decide how tight they can make the spec
>> without hurting sales.
>>
>
> Some engineers are reluctant to run parts at abs max, so guardband
> down. I figure the manufacturer has already guardbanded.
>
> One interesting case is reverse biasing polarized capacitors, which is
> rarely specified.
>
> Another is RF parts, where the abs max voltage is often the max
> suggested supply max, and it's assumed but not stated that the actual
> drain voltage will swing to 2x the supply.
> Yup.

It's inconvenient that there's so little indication of how the ratings
are arrived at.

Wet electros appear fine when you exceed their voltage ratings by a
smallish amount like 10%, but their lifetime drops very very rapidly
with overvoltage.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510

http://electrooptical.net
http://hobbs-eo.com

On Mon, 30 Jan 2023 04:20:21 -0500, Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:

>John Larkin wrote:
>> On Sun, 29 Jan 2023 19:32:32 -0500, Phil Hobbs
>> <pcdhSpamMeSenseless@electrooptical.net> wrote:
>>
>>> John Larkin wrote:
>>>> On Sun, 29 Jan 2023 16:43:36 -0500, Phil Hobbs
>>>> <pcdhSpamMeSenseless@electrooptical.net> wrote:
>>>>
>>>>>
>>>>> In one hand-wired proto recently,(*) I was using an LM319N
>>>>> open-collector dual comparator to drive the !set and !clear inputs of
>>>>> one section of a 74VHC74A dflop.
>>>>>
>>>>> The 319 was running off +-15V. By mistake, I wired the pull-up resistor
>>>>> on one section to +15 rather than +5. The circuit worked perfectly--I
>>>>> only noticed the blunder when I went to make a slight change to the ramp
>>>>> current source.
>>>>>
>>>>> Abs max on both VDD and any input is +7V, which appears to be a fairly
>>>>> absurd underestimate of what the !clear input can comfortably manage, at
>>>>> least for a day or two. It didn't seem to be drawing any input current,
>>>>> either--at most a few dozen microamps.
>>>>>
>>>>> Cheers
>>>>>
>>>>> Phil Hobbs
>>>>>
>>>>> (*) It was that highly linear ramp generator I was talking about in
>>>>> another thread. Swapping out the mylar cap for a polypropylene reduced
>>>>> the soakage tail on the ramp, but didn't eliminate it.
>>>>
>>>>
>>>> The upper ESD diode in the 74VHC74A is essentially a zener to ground,
>>>> not a pn diode to Vcc. One could test one to see where it actually
>>>> zeners.
>>>>
>>>> Mylar caps make terrible ramps.
>>>
>>> Mylar isn't too bad at this speed (1-100 Hz). The original version of
>>> this circuit had about a 200 us reset pulse, controlling the gate of a
>>> 2N7002 directly. The capacitor was a 330 nF, 200V mylar, and the
>>> discharge arrangement was that 2N7002 with a 20-ohm resistor in series.
>>> The ramp reset pulse was about 200 us, i.e. about 15 time constants.
>>> There was about a 2-ms tail following the reset. The polyprop ones are
>>> probably 3x tighter, but not orders of magnitude.
>>>
>>> I have some polystyrenes in my drawer, but they're only available up to
>>> the early nanofarads. (I have a few NOS ones up to 10 nF.)
>>>
>>> I made a little RC differentiator gizmo with a polystyrene cap and an
>>> OPA141, and verified that the rest of the ramp was linear to better than
>>> 12 bits, which was about the limit of the measurement. Making the reset
>>> pulse 10 ms wide fixed it completely.
>>>
>>>> I like to test parts past abs max to see what happens. It's rare to
>>>> find a part that won't tolerate 2x abs max voltage, and 5:1 isn't
>>>> unusual.
>>>
>>> Seems like the chip makers decide how tight they can make the spec
>>> without hurting sales.
>>>
>>
>> Some engineers are reluctant to run parts at abs max, so guardband
>> down. I figure the manufacturer has already guardbanded.
>>
>> One interesting case is reverse biasing polarized capacitors, which is
>> rarely specified.
>>
>> Another is RF parts, where the abs max voltage is often the max
>> suggested supply max, and it's assumed but not stated that the actual
>> drain voltage will swing to 2x the supply.
>> Yup.
>
>It's inconvenient that there's so little indication of how the ratings
>are arrived at.

Very inconvenient. I wonder how guardband standards emerge. It's kind
of a regional cultural thing, I expect. I like to measure parts to see
how conservative the max ratings are. I can recall only one opamp, a
Harris HFA1130, that was rated 11 volts abns max and would die about
there. 11 was an unusual number.

>
>Wet electros appear fine when you exceed their voltage ratings by a
>smallish amount like 10%, but their lifetime drops very very rapidly
>with overvoltage.
>

Polymers are interesting. I tested a bunch for a couple of months to
make sure I could use them reverse biased.

One thing that the semi people can't be trusted about is mosfet max
power and current.

FDD86367 is a dpak spec'd at 227 watts and 100 amps CW.

IR established industry standards for insane power claims. One of
their TO247 fets claims 1000 amps and 1000 watts.

Sometimes the way to get extreme performance is to push a part or two.
That's a calculated risk.

On Mon, 30 Jan 2023 07:14:47 -0800, John Larkin
<jlarkin@highlandSNIPMEtechnology.com> wrote:

>On Mon, 30 Jan 2023 04:20:21 -0500, Phil Hobbs
><pcdhSpamMeSenseless@electrooptical.net> wrote:
>
>>John Larkin wrote:
>>> On Sun, 29 Jan 2023 19:32:32 -0500, Phil Hobbs
>>> <pcdhSpamMeSenseless@electrooptical.net> wrote:
>>>
>>>> John Larkin wrote:
>>>>> On Sun, 29 Jan 2023 16:43:36 -0500, Phil Hobbs
>>>>> <pcdhSpamMeSenseless@electrooptical.net> wrote:
>>>>>
>>>>>>
>>>>>> In one hand-wired proto recently,(*) I was using an LM319N
>>>>>> open-collector dual comparator to drive the !set and !clear inputs of
>>>>>> one section of a 74VHC74A dflop.
>>>>>>
>>>>>> The 319 was running off +-15V. By mistake, I wired the pull-up resistor
>>>>>> on one section to +15 rather than +5. The circuit worked perfectly--I
>>>>>> only noticed the blunder when I went to make a slight change to the ramp
>>>>>> current source.
>>>>>>
>>>>>> Abs max on both VDD and any input is +7V, which appears to be a fairly
>>>>>> absurd underestimate of what the !clear input can comfortably manage, at
>>>>>> least for a day or two. It didn't seem to be drawing any input current,
>>>>>> either--at most a few dozen microamps.
>>>>>>
>>>>>> Cheers
>>>>>>
>>>>>> Phil Hobbs
>>>>>>
>>>>>> (*) It was that highly linear ramp generator I was talking about in
>>>>>> another thread. Swapping out the mylar cap for a polypropylene reduced
>>>>>> the soakage tail on the ramp, but didn't eliminate it.
>>>>>
>>>>>
>>>>> The upper ESD diode in the 74VHC74A is essentially a zener to ground,
>>>>> not a pn diode to Vcc. One could test one to see where it actually
>>>>> zeners.
>>>>>
>>>>> Mylar caps make terrible ramps.
>>>>
>>>> Mylar isn't too bad at this speed (1-100 Hz). The original version of
>>>> this circuit had about a 200 us reset pulse, controlling the gate of a
>>>> 2N7002 directly. The capacitor was a 330 nF, 200V mylar, and the
>>>> discharge arrangement was that 2N7002 with a 20-ohm resistor in series.
>>>> The ramp reset pulse was about 200 us, i.e. about 15 time constants.
>>>> There was about a 2-ms tail following the reset. The polyprop ones are
>>>> probably 3x tighter, but not orders of magnitude.
>>>>
>>>> I have some polystyrenes in my drawer, but they're only available up to
>>>> the early nanofarads. (I have a few NOS ones up to 10 nF.)
>>>>
>>>> I made a little RC differentiator gizmo with a polystyrene cap and an
>>>> OPA141, and verified that the rest of the ramp was linear to better than
>>>> 12 bits, which was about the limit of the measurement. Making the reset
>>>> pulse 10 ms wide fixed it completely.
>>>>
>>>>> I like to test parts past abs max to see what happens. It's rare to
>>>>> find a part that won't tolerate 2x abs max voltage, and 5:1 isn't
>>>>> unusual.
>>>>
>>>> Seems like the chip makers decide how tight they can make the spec
>>>> without hurting sales.
>>>>
>>>
>>> Some engineers are reluctant to run parts at abs max, so guardband
>>> down. I figure the manufacturer has already guardbanded.
>>>
>>> One interesting case is reverse biasing polarized capacitors, which is
>>> rarely specified.
>>>
>>> Another is RF parts, where the abs max voltage is often the max
>>> suggested supply max, and it's assumed but not stated that the actual
>>> drain voltage will swing to 2x the supply.
>>> Yup.
>>
>>It's inconvenient that there's so little indication of how the ratings
>>are arrived at.
>
>Very inconvenient. I wonder how guardband standards emerge. It's kind
>of a regional cultural thing, I expect. I like to measure parts to see
>how conservative the max ratings are. I can recall only one opamp, a
>Harris HFA1130, that was rated 11 volts abns max and would die about
>there. 11 was an unusual number.
>
>>
>>Wet electros appear fine when you exceed their voltage ratings by a
>>smallish amount like 10%, but their lifetime drops very very rapidly
>>with overvoltage.
>>
>
>Polymers are interesting. I tested a bunch for a couple of months to
>make sure I could use them reverse biased.
>
>One thing that the semi people can't be trusted about is mosfet max
>power and current.
>
>FDD86367 is a dpak spec'd at 227 watts and 100 amps CW.
>
>IR established industry standards for insane power claims. One of
>their TO247 fets claims 1000 amps and 1000 watts.
>
>
>Sometimes the way to get extreme performance is to push a part or two.
>That's a calculated risk.

Let me start by saying that I'm not an expert in how one establishes
absolute maximum specs, but I spent the last 2+ decades of my
IC-design career using leading-edge analog processes, both
junction-isolated and dielectrically-isolated, to design complex
custom mixed-signal components. Our customers, large test equipment
manufacturers who might use thousands of an expensive IC---> in each
system <---, expected continuous system up-time measured in months.
Customer-site failures were very expensive and made them VERY unhappy,
especially if magic smoke got release in a clean room. You don't know
joy until you've been on the ultimate receiving end of a call placed
by the president of your customer's billion dollar corporation to the
president of your billion-dollar employer.

The most obvious aspect of an absolute-maximum rating is "Does the
part blow up RIGHT NOW?". But that's only part of it. A stress
beyond some abs-max limit might not destroy the part, but might cause
a parametric shift that pushes it out of spec. This failure may or
may not be immediately apparent in any particular application.
Repeated application of the excess stress might produce cumulative
damage that will cause the circuit to fail some time down the road.

Input bias currents could go up (this applies to logic as well as to
analog circuits like op-amps). Offset could increase. Output
pulldown current could decrease. Protection clamps could be damaged
or destroyed. Supply current could increase. Any given design might
be relatively insensitive to some or all of these shifts, but the IC
manufacturer can't know that and must assume that every guaranteed
spec is critical. That's what drives the absolute-maximum specs.

For the processes I worked with, large numbers* of individual devices
(transistors, capacitors, resistors, etc.) were subjected to thousands
of hours of testing at varying stress levels. Measurements performed
at set intervals looked both gross failures and parametric shifts.
This was used to establish device limits.

*In the case of one particular new digital device type I remember, the
number of individual devices tested was well into 6 digits, and NO
failures were allowed. And even with that, we were required to build
in error detection and correction.

As we designed, we would check that things like collector-base
voltage, reverse Vbe, capacitor voltage, gate-source and gate-drain
voltages, current density, and internal device temperature were never
exceeded with the specified supplies under both static and dynamic
conditions. [Our in-house simulator's abilities to do automatic
checking are way beyond anything I've ever seen available in
commercial simulators.] These checkers were run during EVERY
simulation through the entire design process, from the smallest
circuit block through the complete circuit. And we would typically
guardband our absolute maximum limits as well.

The fact that a component in a prototype board didn't immediately fail
in a dramatic way when you exceeded one of its abs-max limits is nice,
but that's no way to design a production article.

On 2023-01-30 20:20, Steve Goldstein wrote:
> On Mon, 30 Jan 2023 07:14:47 -0800, John Larkin
> <jlarkin@highlandSNIPMEtechnology.com> wrote:
>
>> On Mon, 30 Jan 2023 04:20:21 -0500, Phil Hobbs
>> <pcdhSpamMeSenseless@electrooptical.net> wrote:
>>
>>> John Larkin wrote:
>>>> On Sun, 29 Jan 2023 19:32:32 -0500, Phil Hobbs
>>>> <pcdhSpamMeSenseless@electrooptical.net> wrote:
>>>>
>>>>> John Larkin wrote:
>>>>>> On Sun, 29 Jan 2023 16:43:36 -0500, Phil Hobbs
>>>>>> <pcdhSpamMeSenseless@electrooptical.net> wrote:
>>>>>>
>>>>>>>
>>>>>>> In one hand-wired proto recently,(*) I was using an LM319N
>>>>>>> open-collector dual comparator to drive the !set and !clear inputs of
>>>>>>> one section of a 74VHC74A dflop.
>>>>>>>
>>>>>>> The 319 was running off +-15V. By mistake, I wired the pull-up resistor
>>>>>>> on one section to +15 rather than +5. The circuit worked perfectly--I
>>>>>>> only noticed the blunder when I went to make a slight change to the ramp
>>>>>>> current source.
>>>>>>>
>>>>>>> Abs max on both VDD and any input is +7V, which appears to be a fairly
>>>>>>> absurd underestimate of what the !clear input can comfortably manage, at
>>>>>>> least for a day or two. It didn't seem to be drawing any input current,
>>>>>>> either--at most a few dozen microamps.
>>>>>>>
>>>>>>> Cheers
>>>>>>>
>>>>>>> Phil Hobbs
>>>>>>>
>>>>>>> (*) It was that highly linear ramp generator I was talking about in
>>>>>>> another thread. Swapping out the mylar cap for a polypropylene reduced
>>>>>>> the soakage tail on the ramp, but didn't eliminate it.
>>>>>>
>>>>>>
>>>>>> The upper ESD diode in the 74VHC74A is essentially a zener to ground,
>>>>>> not a pn diode to Vcc. One could test one to see where it actually
>>>>>> zeners.
>>>>>>
>>>>>> Mylar caps make terrible ramps.
>>>>>
>>>>> Mylar isn't too bad at this speed (1-100 Hz). The original version of
>>>>> this circuit had about a 200 us reset pulse, controlling the gate of a
>>>>> 2N7002 directly. The capacitor was a 330 nF, 200V mylar, and the
>>>>> discharge arrangement was that 2N7002 with a 20-ohm resistor in series.
>>>>> The ramp reset pulse was about 200 us, i.e. about 15 time constants.
>>>>> There was about a 2-ms tail following the reset. The polyprop ones are
>>>>> probably 3x tighter, but not orders of magnitude.
>>>>>
>>>>> I have some polystyrenes in my drawer, but they're only available up to
>>>>> the early nanofarads. (I have a few NOS ones up to 10 nF.)
>>>>>
>>>>> I made a little RC differentiator gizmo with a polystyrene cap and an
>>>>> OPA141, and verified that the rest of the ramp was linear to better than
>>>>> 12 bits, which was about the limit of the measurement. Making the reset
>>>>> pulse 10 ms wide fixed it completely.
>>>>>
>>>>>> I like to test parts past abs max to see what happens. It's rare to
>>>>>> find a part that won't tolerate 2x abs max voltage, and 5:1 isn't
>>>>>> unusual.
>>>>>
>>>>> Seems like the chip makers decide how tight they can make the spec
>>>>> without hurting sales.
>>>>>
>>>>
>>>> Some engineers are reluctant to run parts at abs max, so guardband
>>>> down. I figure the manufacturer has already guardbanded.
>>>>
>>>> One interesting case is reverse biasing polarized capacitors, which is
>>>> rarely specified.
>>>>
>>>> Another is RF parts, where the abs max voltage is often the max
>>>> suggested supply max, and it's assumed but not stated that the actual
>>>> drain voltage will swing to 2x the supply.
>>>> Yup.
>>>
>>> It's inconvenient that there's so little indication of how the ratings
>>> are arrived at.
>>
>> Very inconvenient. I wonder how guardband standards emerge. It's kind
>> of a regional cultural thing, I expect. I like to measure parts to see
>> how conservative the max ratings are. I can recall only one opamp, a
>> Harris HFA1130, that was rated 11 volts abns max and would die about
>> there. 11 was an unusual number.
>>
>>>
>>> Wet electros appear fine when you exceed their voltage ratings by a
>>> smallish amount like 10%, but their lifetime drops very very rapidly
>>> with overvoltage.
>>>
>>
>> Polymers are interesting. I tested a bunch for a couple of months to
>> make sure I could use them reverse biased.
>>
>> One thing that the semi people can't be trusted about is mosfet max
>> power and current.
>>
>> FDD86367 is a dpak spec'd at 227 watts and 100 amps CW.
>>
>> IR established industry standards for insane power claims. One of
>> their TO247 fets claims 1000 amps and 1000 watts.
>>
>>
>> Sometimes the way to get extreme performance is to push a part or two.
>> That's a calculated risk.
>
> Let me start by saying that I'm not an expert in how one establishes
> absolute maximum specs, but I spent the last 2+ decades of my
> IC-design career using leading-edge analog processes, both
> junction-isolated and dielectrically-isolated, to design complex
> custom mixed-signal components. Our customers, large test equipment
> manufacturers who might use thousands of an expensive IC---> in each
> system <---, expected continuous system up-time measured in months.
> Customer-site failures were very expensive and made them VERY unhappy,
> especially if magic smoke got release in a clean room. You don't know
> joy until you've been on the ultimate receiving end of a call placed
> by the president of your customer's billion dollar corporation to the
> president of your billion-dollar employer.
>
> The most obvious aspect of an absolute-maximum rating is "Does the
> part blow up RIGHT NOW?". But that's only part of it. A stress
> beyond some abs-max limit might not destroy the part, but might cause
> a parametric shift that pushes it out of spec. This failure may or
> may not be immediately apparent in any particular application.
> Repeated application of the excess stress might produce cumulative
> damage that will cause the circuit to fail some time down the road.
>
> Input bias currents could go up (this applies to logic as well as to
> analog circuits like op-amps). Offset could increase. Output
> pulldown current could decrease. Protection clamps could be damaged
> or destroyed. Supply current could increase. Any given design might
> be relatively insensitive to some or all of these shifts, but the IC
> manufacturer can't know that and must assume that every guaranteed
> spec is critical. That's what drives the absolute-maximum specs.
>
> For the processes I worked with, large numbers* of individual devices
> (transistors, capacitors, resistors, etc.) were subjected to thousands
> of hours of testing at varying stress levels. Measurements performed
> at set intervals looked both gross failures and parametric shifts.
> This was used to establish device limits.
>
> *In the case of one particular new digital device type I remember, the
> number of individual devices tested was well into 6 digits, and NO
> failures were allowed. And even with that, we were required to build
> in error detection and correction.
>
> As we designed, we would check that things like collector-base
> voltage, reverse Vbe, capacitor voltage, gate-source and gate-drain
> voltages, current density, and internal device temperature were never
> exceeded with the specified supplies under both static and dynamic
> conditions. [Our in-house simulator's abilities to do automatic
> checking are way beyond anything I've ever seen available in
> commercial simulators.] These checkers were run during EVERY
> simulation through the entire design process, from the smallest
> circuit block through the complete circuit. And we would typically
> guardband our absolute maximum limits as well.
>
> The fact that a component in a prototype board didn't immediately fail
> in a dramatic way when you exceeded one of its abs-max limits is nice,
> but that's no way to design a production article.
>

On a sunny day (Mon, 30 Jan 2023 20:59:57 -0500) it happened Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote in
<9e867722-bc33-1f1c-edfe-144020e563d0@electrooptical.net>:

>On 2023-01-30 20:20, Steve Goldstein wrote:
>> The fact that a component in a prototype board didn't immediately fail
>> in a dramatic way when you exceeded one of its abs-max limits is nice,
>> but that's no way to design a production article.
>>
>
>IOW, "Here there be dragons." ;)
>
>I'm sympathetic to the chip makers, who have no control over what their
>customers do with their parts. (Some years back we had a regular poster
>'miso', an IC designer with a bad attitude towards customers--I didn't
>like it much, but that doesn't mean he had no excuse.) I'm also glad
>for the amount of effort that goes into that sort of stuff.
>
>However, at least some customers are also vaguely competent, and it's
>frustrating to have zero insight into how such specs are arrived at,
>because sometimes there are excellent reasons for exceeding some of them
>(rf transistors' BV_CEO, for instance) and staying miles away from
>others (MOSFET max current and dissipation).

Maybe for some hobby project, or the F35? but it is bad practice.
And there is liability too if you deliberately design out of spec.

On 30/01/2023 04:36, John Larkin wrote:

<snip>
>
> Some engineers are reluctant to run parts at abs max, so guardband
> down. I figure the manufacturer has already guardbanded.

My experience of exceeding semiconductor temperature specs suggests that
the difference between say an otherwise identical 125'C part and an 85'C
part is twofold:

1) The part number suffix.

2) The price.

--
Cheers
Clive

On Tue, 31 Jan 2023 05:41:50 GMT, Jan Panteltje <alien@comet.invalid>
wrote:

>On a sunny day (Mon, 30 Jan 2023 20:59:57 -0500) it happened Phil Hobbs
><pcdhSpamMeSenseless@electrooptical.net> wrote in
><9e867722-bc33-1f1c-edfe-144020e563d0@electrooptical.net>:
>
>>On 2023-01-30 20:20, Steve Goldstein wrote:
>>> The fact that a component in a prototype board didn't immediately fail
>>> in a dramatic way when you exceeded one of its abs-max limits is nice,
>>> but that's no way to design a production article.
>>>
>>
>>IOW, "Here there be dragons." ;)
>>
>>I'm sympathetic to the chip makers, who have no control over what their
>>customers do with their parts. (Some years back we had a regular poster
>>'miso', an IC designer with a bad attitude towards customers--I didn't
>>like it much, but that doesn't mean he had no excuse.) I'm also glad
>>for the amount of effort that goes into that sort of stuff.
>>
>>However, at least some customers are also vaguely competent, and it's
>>frustrating to have zero insight into how such specs are arrived at,
>>because sometimes there are excellent reasons for exceeding some of them
>>(rf transistors' BV_CEO, for instance) and staying miles away from
>>others (MOSFET max current and dissipation).
>
>
>Maybe for some hobby project, or the F35? but it is bad practice.
>And there is liability too if you deliberately design out of spec.

In fact, BV_CEO is one of the specs we often "violated" in our designs
because those designs (a) were not beta-dependent and (b) had fairly
low-impedance drive at the base. In that particular case BV_CES is
more relevant, and over the years we and others (IEEE publications,
among other places) found that if BV_CES was 3-4x BV_CEO then going a
bit over BV_CEO was OK >for our particular designs<.

On the other hand, I once did a test chip with no apparent device
abs-max spec violations and still had it fail. Under an IR microscope
we could watch a hot-spot develop and destroy the transistor in
question in a second or two. It turns out that this
dielectrically-isolated transistor's didn't allow for uniform heat
conduction into the substrate. Dragons indeed!

Explaining why various abs-max specs are what they are would be a lot
of work with not a lot of market payback. And some manufacturers
would probably be afraid of inadvertently providing knowledge to their
competitors. As an IC user I find that frustrating, but as an IC
designer I do see the other side.

On Tue, 31 Jan 2023 12:09:30 +0000, Clive Arthur
<clive@nowaytoday.co.uk> wrote:

>On 30/01/2023 04:36, John Larkin wrote:
>
><snip>
>>
>> Some engineers are reluctant to run parts at abs max, so guardband
>> down. I figure the manufacturer has already guardbanded.
>
>My experience of exceeding semiconductor temperature specs suggests that
>the difference between say an otherwise identical 125'C part and an 85'C
>part is twofold:
>
>1) The part number suffix.
>
>2) The price.

But the difference between manufacturers for apparently the same part
can be huge. Some of our stock parts are "ADI ONLY" or "FAIRCHILD
ONLY"

On Tuesday, 31 January 2023 at 12:09:38 UTC, Clive Arthur wrote:
> On 30/01/2023 04:36, John Larkin wrote:
>
> <snip>
> >
> > Some engineers are reluctant to run parts at abs max, so guardband
> > down. I figure the manufacturer has already guardbanded.
> My experience of exceeding semiconductor temperature specs suggests that
> the difference between say an otherwise identical 125'C part and an 85'C
> part is twofold:
>
> 1) The part number suffix.
>
> 2) The price.

Yes, a long time ago when TI still had FAEs in the UK I was told that their A-grade
op-amps were exactly the same as the rest apart from extra testing. Apparently
they printed the -A designation BEFORE testing them. If they failed, they got
thrown away. This was cheaper than having branches in the production line!
It worked because most parts were good enough to be A-grade.

John

On 2023-01-31 08:43, Steve Goldstein wrote:
> On Tue, 31 Jan 2023 05:41:50 GMT, Jan Panteltje <alien@comet.invalid>
> wrote:
>
>> On a sunny day (Mon, 30 Jan 2023 20:59:57 -0500) it happened Phil Hobbs
>> <pcdhSpamMeSenseless@electrooptical.net> wrote in
>> <9e867722-bc33-1f1c-edfe-144020e563d0@electrooptical.net>:
>>
>>> On 2023-01-30 20:20, Steve Goldstein wrote:
>>>> The fact that a component in a prototype board didn't immediately fail
>>>> in a dramatic way when you exceeded one of its abs-max limits is nice,
>>>> but that's no way to design a production article.
>>>>
>>>
>>> IOW, "Here there be dragons." ;)
>>>
>>> I'm sympathetic to the chip makers, who have no control over what their
>>> customers do with their parts. (Some years back we had a regular poster
>>> 'miso', an IC designer with a bad attitude towards customers--I didn't
>>> like it much, but that doesn't mean he had no excuse.) I'm also glad
>>> for the amount of effort that goes into that sort of stuff.
>>>
>>> However, at least some customers are also vaguely competent, and it's
>>> frustrating to have zero insight into how such specs are arrived at,
>>> because sometimes there are excellent reasons for exceeding some of them
>>> (rf transistors' BV_CEO, for instance) and staying miles away from
>>> others (MOSFET max current and dissipation).
>>
>>
>> Maybe for some hobby project, or the F35? but it is bad practice.
>> And there is liability too if you deliberately design out of spec.
>
>
> In fact, BV_CEO is one of the specs we often "violated" in our designs
> because those designs (a) were not beta-dependent and (b) had fairly
> low-impedance drive at the base. In that particular case BV_CES is
> more relevant, and over the years we and others (IEEE publications,
> among other places) found that if BV_CES was 3-4x BV_CEO then going a
> bit over BV_CEO was OK >for our particular designs<.
>
> On the other hand, I once did a test chip with no apparent device
> abs-max spec violations and still had it fail. Under an IR microscope
> we could watch a hot-spot develop and destroy the transistor in
> question in a second or two. It turns out that this
> dielectrically-isolated transistor's didn't allow for uniform heat
> conduction into the substrate. Dragons indeed!

I'm surprised it made that much difference if the dissipation was
properly spread out. Normal SIMOX SOI wafers have about 200 nm of oxide
below the transistor layer, which (thermally speaking) is next to
nothing unless the dissipation is concentrated in a very small area.

Small-geometry designs that rely on 3D heat conduction for stability, I
can believe, but that's a design issue.

For thermal non-experts, if you dump heat into an isolated 1 um
hemispherical region at the surface of some uniform material, the
equilibrium delta-T drops by half in the next micron, because the
diameter of the hemisphere doubles.

If you have a 10K delta-T, the resulting gradient is around 5E6 K/m,
which gives you some pretty amazing cooling, providing nobody else
nearby is doing the same thing.

> Explaining why various abs-max specs are what they are would be a lot
> of work with not a lot of market payback. And some manufacturers
> would probably be afraid of inadvertently providing knowledge to their
> competitors. As an IC user I find that frustrating, but as an IC
> designer I do see the other side.

Yeah, sometimes we have to put on our big-boy pants and do the
engineering evaluation, then guard-band on our own.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510

http://electrooptical.net
http://hobbs-eo.com

On 2023-01-31 10:28, John Larkin wrote:
> On Tue, 31 Jan 2023 12:09:30 +0000, Clive Arthur
> <clive@nowaytoday.co.uk> wrote:
>
>> On 30/01/2023 04:36, John Larkin wrote:
>>
>> <snip>
>>>
>>> Some engineers are reluctant to run parts at abs max, so guardband
>>> down. I figure the manufacturer has already guardbanded.
>>
>> My experience of exceeding semiconductor temperature specs suggests that
>> the difference between say an otherwise identical 125'C part and an 85'C
>> part is twofold:
>>
>> 1) The part number suffix.
>>
>> 2) The price.
>
> But the difference between manufacturers for apparently the same part
> can be huge. Some of our stock parts are "ADI ONLY" or "FAIRCHILD
> ONLY"
>

Believing that two parts with the same type number are the same is a
form of category error, similar to "democratic" and "Democratic Republic
of Congo". ;)

The poster children are the various flavors of TLV431--check out the
stability boundaries for On Semi vs. Diodes. ;)

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510

http://electrooptical.net
http://hobbs-eo.com

On Tuesday, January 31, 2023 at 8:09:38 AM UTC-4, Clive Arthur wrote:
> On 30/01/2023 04:36, John Larkin wrote:
>
> <snip>
> >
> > Some engineers are reluctant to run parts at abs max, so guardband
> > down. I figure the manufacturer has already guardbanded.
> My experience of exceeding semiconductor temperature specs suggests that
> the difference between say an otherwise identical 125'C part and an 85'C
> part is twofold:
>
> 1) The part number suffix.
>
> 2) The price.

Sure, they don't create a new part, typically. But they test them separately. I'm more familiar with digital devices, where the timing characteristics vary with temperature. So buying a higher temperature range device is the same as buying a faster device. In fact, they often sell them as speed 1 at commercial temp, but speed 2 at industrial temp, all in the same part number, "C1/I2".

Same silicon, different testing and also the parts come from a different position on the bell curve. Although, some Xilinx guys have pointed out that if their process doesn't have a high pass rate at the fastest speed grade, they have done something wrong. Fallouts are mostly defects, rather than process variations.

--

Rick C.

+-- Get 1,000 miles of free Supercharging
+-- Tesla referral code - https://ts.la/richard11209

On Tue, 31 Jan 2023 13:12:08 -0500, Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:

>On 2023-01-31 10:28, John Larkin wrote:
>> On Tue, 31 Jan 2023 12:09:30 +0000, Clive Arthur
>> <clive@nowaytoday.co.uk> wrote:
>>
>>> On 30/01/2023 04:36, John Larkin wrote:
>>>
>>> <snip>
>>>>
>>>> Some engineers are reluctant to run parts at abs max, so guardband
>>>> down. I figure the manufacturer has already guardbanded.
>>>
>>> My experience of exceeding semiconductor temperature specs suggests that
>>> the difference between say an otherwise identical 125'C part and an 85'C
>>> part is twofold:
>>>
>>> 1) The part number suffix.
>>>
>>> 2) The price.
>>
>> But the difference between manufacturers for apparently the same part
>> can be huge. Some of our stock parts are "ADI ONLY" or "FAIRCHILD
>> ONLY"
>>
>
>Believing that two parts with the same type number are the same is a
>form of category error, similar to "democratic" and "Democratic Republic
>of Congo". ;)
>
>The poster children are the various flavors of TLV431--check out the
>stability boundaries for On Semi vs. Diodes. ;)
>
>Cheers
>
>Phil Hobbs

Don't get me started on c-load stability specs. I'm liable to get
violent.

On Tue, 31 Jan 2023 13:07:50 -0500, Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:

>On 2023-01-31 08:43, Steve Goldstein wrote:
>> On Tue, 31 Jan 2023 05:41:50 GMT, Jan Panteltje <alien@comet.invalid>
>> wrote:
>>
>>> On a sunny day (Mon, 30 Jan 2023 20:59:57 -0500) it happened Phil Hobbs
>>> <pcdhSpamMeSenseless@electrooptical.net> wrote in
>>> <9e867722-bc33-1f1c-edfe-144020e563d0@electrooptical.net>:
>>>
>>>> On 2023-01-30 20:20, Steve Goldstein wrote:
>>>>> The fact that a component in a prototype board didn't immediately fail
>>>>> in a dramatic way when you exceeded one of its abs-max limits is nice,
>>>>> but that's no way to design a production article.
>>>>>
>>>>
>>>> IOW, "Here there be dragons." ;)
>>>>
>>>> I'm sympathetic to the chip makers, who have no control over what their
>>>> customers do with their parts. (Some years back we had a regular poster
>>>> 'miso', an IC designer with a bad attitude towards customers--I didn't
>>>> like it much, but that doesn't mean he had no excuse.) I'm also glad
>>>> for the amount of effort that goes into that sort of stuff.
>>>>
>>>> However, at least some customers are also vaguely competent, and it's
>>>> frustrating to have zero insight into how such specs are arrived at,
>>>> because sometimes there are excellent reasons for exceeding some of them
>>>> (rf transistors' BV_CEO, for instance) and staying miles away from
>>>> others (MOSFET max current and dissipation).
>>>
>>>
>>> Maybe for some hobby project, or the F35? but it is bad practice.
>>> And there is liability too if you deliberately design out of spec.
>>
>>
>> In fact, BV_CEO is one of the specs we often "violated" in our designs
>> because those designs (a) were not beta-dependent and (b) had fairly
>> low-impedance drive at the base. In that particular case BV_CES is
>> more relevant, and over the years we and others (IEEE publications,
>> among other places) found that if BV_CES was 3-4x BV_CEO then going a
>> bit over BV_CEO was OK >for our particular designs<.
>>
>> On the other hand, I once did a test chip with no apparent device
>> abs-max spec violations and still had it fail. Under an IR microscope
>> we could watch a hot-spot develop and destroy the transistor in
>> question in a second or two. It turns out that this
>> dielectrically-isolated transistor's didn't allow for uniform heat
>> conduction into the substrate. Dragons indeed!
>
>I'm surprised it made that much difference if the dissipation was
>properly spread out. Normal SIMOX SOI wafers have about 200 nm of oxide
>below the transistor layer, which (thermally speaking) is next to
>nothing unless the dissipation is concentrated in a very small area.
>
>Small-geometry designs that rely on 3D heat conduction for stability, I
>can believe, but that's a design issue.
>
>For thermal non-experts, if you dump heat into an isolated 1 um
>hemispherical region at the surface of some uniform material, the
>equilibrium delta-T drops by half in the next micron, because the
>diameter of the hemisphere doubles.
>
>If you have a 10K delta-T, the resulting gradient is around 5E6 K/m,
>which gives you some pretty amazing cooling, providing nobody else
>nearby is doing the same thing.
>
>> Explaining why various abs-max specs are what they are would be a lot
>> of work with not a lot of market payback. And some manufacturers
>> would probably be afraid of inadvertently providing knowledge to their
>> competitors. As an IC user I find that frustrating, but as an IC
>> designer I do see the other side.
>
>Yeah, sometimes we have to put on our big-boy pants and do the
>engineering evaluation, then guard-band on our own.
>
>Cheers
>
>Phil Hobbs

The problem was that the dissipation didn't spread out. This
multi-emitter structure had something like 15 emitter stripes, let's
say each was 1um x 5um. Heat in the outer emitters could escape more
easily than from the ones in the center. It worked fine up to a
certain overall dissipation, but once that was exceeded it experienced
thermal runaway. From this was born a design rule limiting the number
of emitter stripes in this particular transistor type.