On Monday, 28 May 2018 at 18:28:17 UTC+2, sea moss wrote:
> > Integrated means, for the LLC resonant converter case, that the leakage inductor is embedded in the transformer construction. You need about 20% leakage, which is easy on a regular transformer (just pull the windings away from each other), but on a planar you cannot pull it away, so you need either a magnetic shunt, or assymetricc transformer windings construction
> >
> Glad you pointed that out. In this case I'm operating the LLC right around the "zero load regulation" point; i.e. the resonant frequency of the series C and leakage inductance. Running open loop with no frequency modulation.. Mag inductance just needs to be large enough to be out of the way. (so it's essentially a series LC resonant converter, with isolation)
>
> Once I can figure out the most practical way to achieve the high isolation needed without making this thing too huge, my idea was to measure the leakage inductance, and add an external L if needed.
>
> Forgot to mention, because it didn't seem relevant until you just brought it up: the planar PCB consists of only secondary windings. The primary consists of a couple turns of HV insulated wire (rated to 25kV). So there's a pretty big gap between the top of the planar PCB and the core to fit the primary turns. Isolation from primary to secondary is 20kV and the LLC front end sits on a different card than this transformer.

Hi Sea Moss,

I happened to look at this post as I was having same doubt. Did you happen to find solution for the first question that you asked?
Also did you consider the creepage along one internal layer to the second internal layer along the edge of the board?

Thankyou in advance!

On Tuesday, March 21, 2023 at 10:56:36 AM UTC-7, Deepak Bikkina wrote:
> On Monday, 28 May 2018 at 18:28:17 UTC+2, sea moss wrote:
> > > Integrated means, for the LLC resonant converter case, that the leakage inductor is embedded in the transformer construction. You need about 20% leakage, which is easy on a regular transformer (just pull the windings away from each other), but on a planar you cannot pull it away, so you need either a magnetic shunt, or assymetricc transformer windings construction
> > >
> > Glad you pointed that out. In this case I'm operating the LLC right around the "zero load regulation" point; i.e. the resonant frequency of the series C and leakage inductance. Running open loop with no frequency modulation. Mag inductance just needs to be large enough to be out of the way. (so it's essentially a series LC resonant converter, with isolation)
> >
> > Once I can figure out the most practical way to achieve the high isolation needed without making this thing too huge, my idea was to measure the leakage inductance, and add an external L if needed.
> >
> > Forgot to mention, because it didn't seem relevant until you just brought it up: the planar PCB consists of only secondary windings. The primary consists of a couple turns of HV insulated wire (rated to 25kV). So there's a pretty big gap between the top of the planar PCB and the core to fit the primary turns. Isolation from primary to secondary is 20kV and the LLC front end sits on a different card than this transformer.
> Hi Sea Moss,
>
> I happened to look at this post as I was having same doubt. Did you happen to find solution for the first question that you asked?
> Also did you consider the creepage along one internal layer to the second internal layer along the edge of the board?
>
> Thankyou in advance!

Hi Deepak,

For my application, I ended up using 50V/mil as a limit for trace-trace spacing on a single inner layer. If the application was airborne I probably would have been even more conservative. I did a lot of thermal cycle and long-term hi-pot testing to prove the design. The main worry was that any small amount of delamination could make an inner layer start to act like an outer layer, where we were using a 20V/mil rule. In this particular application, the planar XFMR was in a potted module and would not see large temperature swings in the field, so I determined the long-term risk of delamination was low. And yes, I did consider the creepage paths from the traces to the board edge.

On Tuesday, 21 March 2023 at 23:06:18 UTC+1, sea moss wrote:
> On Tuesday, March 21, 2023 at 10:56:36 AM UTC-7, Deepak Bikkina wrote:
> > On Monday, 28 May 2018 at 18:28:17 UTC+2, sea moss wrote:
> > > > Integrated means, for the LLC resonant converter case, that the leakage inductor is embedded in the transformer construction. You need about 20% leakage, which is easy on a regular transformer (just pull the windings away from each other), but on a planar you cannot pull it away, so you need either a magnetic shunt, or assymetricc transformer windings construction
> > > >
> > > Glad you pointed that out. In this case I'm operating the LLC right around the "zero load regulation" point; i.e. the resonant frequency of the series C and leakage inductance. Running open loop with no frequency modulation. Mag inductance just needs to be large enough to be out of the way. (so it's essentially a series LC resonant converter, with isolation)
> > >
> > > Once I can figure out the most practical way to achieve the high isolation needed without making this thing too huge, my idea was to measure the leakage inductance, and add an external L if needed.
> > >
> > > Forgot to mention, because it didn't seem relevant until you just brought it up: the planar PCB consists of only secondary windings. The primary consists of a couple turns of HV insulated wire (rated to 25kV). So there's a pretty big gap between the top of the planar PCB and the core to fit the primary turns. Isolation from primary to secondary is 20kV and the LLC front end sits on a different card than this transformer.
> > Hi Sea Moss,
> >
> > I happened to look at this post as I was having same doubt. Did you happen to find solution for the first question that you asked?
> > Also did you consider the creepage along one internal layer to the second internal layer along the edge of the board?
> >
> > Thankyou in advance!
> Hi Deepak,
>
> For my application, I ended up using 50V/mil as a limit for trace-trace spacing on a single inner layer. If the application was airborne I probably would have been even more conservative. I did a lot of thermal cycle and long-term hi-pot testing to prove the design. The main worry was that any small amount of delamination could make an inner layer start to act like an outer layer, where we were using a 20V/mil rule. In this particular application, the planar XFMR was in a potted module and would not see large temperature swings in the field, so I determined the long-term risk of delamination was low. And yes, I did consider the creepage paths from the traces to the board edge.

Thankyou for your immediate response. This information really helps me with my project!

Regards
Deepak B

On Wednesday, 22 March 2023 at 09:55:21 UTC, Deepak Bikkina wrote:
> On Tuesday, 21 March 2023 at 23:06:18 UTC+1, sea moss wrote:
> > On Tuesday, March 21, 2023 at 10:56:36 AM UTC-7, Deepak Bikkina wrote:
> > > On Monday, 28 May 2018 at 18:28:17 UTC+2, sea moss wrote:
> > > > > Integrated means, for the LLC resonant converter case, that the leakage inductor is embedded in the transformer construction. You need about 20% leakage, which is easy on a regular transformer (just pull the windings away from each other), but on a planar you cannot pull it away, so you need either a magnetic shunt, or assymetricc transformer windings construction
> > > > >
> > > > Glad you pointed that out. In this case I'm operating the LLC right around the "zero load regulation" point; i.e. the resonant frequency of the series C and leakage inductance. Running open loop with no frequency modulation. Mag inductance just needs to be large enough to be out of the way. (so it's essentially a series LC resonant converter, with isolation)
> > > >
> > > > Once I can figure out the most practical way to achieve the high isolation needed without making this thing too huge, my idea was to measure the leakage inductance, and add an external L if needed.
> > > >
> > > > Forgot to mention, because it didn't seem relevant until you just brought it up: the planar PCB consists of only secondary windings. The primary consists of a couple turns of HV insulated wire (rated to 25kV). So there's a pretty big gap between the top of the planar PCB and the core to fit the primary turns. Isolation from primary to secondary is 20kV and the LLC front end sits on a different card than this transformer.
> > > Hi Sea Moss,
> > >
> > > I happened to look at this post as I was having same doubt. Did you happen to find solution for the first question that you asked?
> > > Also did you consider the creepage along one internal layer to the second internal layer along the edge of the board?
> > >
> > > Thankyou in advance!
> > Hi Deepak,
> >
> > For my application, I ended up using 50V/mil as a limit for trace-trace spacing on a single inner layer. If the application was airborne I probably would have been even more conservative. I did a lot of thermal cycle and long-term hi-pot testing to prove the design. The main worry was that any small amount of delamination could make an inner layer start to act like an outer layer, where we were using a 20V/mil rule. In this particular application, the planar XFMR was in a potted module and would not see large temperature swings in the field, so I determined the long-term risk of delamination was low. And yes, I did consider the creepage paths from the traces to the board edge.
> Thankyou for your immediate response. This information really helps me with my project!
>
> Regards
> Deepak B

If you are designing computer, communication or audio equipment then section G.13 of IEC62368.1
will give you a lot of useful information about pcb requirements.

John

On Wed, 22 Mar 2023 03:47:38 -0700 (PDT), John Walliker
<jrwalliker@gmail.com> wrote:

>On Wednesday, 22 March 2023 at 09:55:21 UTC, Deepak Bikkina wrote:
>> On Tuesday, 21 March 2023 at 23:06:18 UTC+1, sea moss wrote:
>> > On Tuesday, March 21, 2023 at 10:56:36?AM UTC-7, Deepak Bikkina wrote:
>> > > On Monday, 28 May 2018 at 18:28:17 UTC+2, sea moss wrote:
>> > > > > Integrated means, for the LLC resonant converter case, that the leakage inductor is embedded in the transformer construction. You need about 20% leakage, which is easy on a regular transformer (just pull the windings away from each other), but on a planar you cannot pull it away, so you need either a magnetic shunt, or assymetricc transformer windings construction
>> > > > >
>> > > > Glad you pointed that out. In this case I'm operating the LLC right around the "zero load regulation" point; i.e. the resonant frequency of the series C and leakage inductance. Running open loop with no frequency modulation. Mag inductance just needs to be large enough to be out of the way. (so it's essentially a series LC resonant converter, with isolation)
>> > > >
>> > > > Once I can figure out the most practical way to achieve the high isolation needed without making this thing too huge, my idea was to measure the leakage inductance, and add an external L if needed.
>> > > >
>> > > > Forgot to mention, because it didn't seem relevant until you just brought it up: the planar PCB consists of only secondary windings. The primary consists of a couple turns of HV insulated wire (rated to 25kV). So there's a pretty big gap between the top of the planar PCB and the core to fit the primary turns. Isolation from primary to secondary is 20kV and the LLC front end sits on a different card than this transformer.
>> > > Hi Sea Moss,
>> > >
>> > > I happened to look at this post as I was having same doubt. Did you happen to find solution for the first question that you asked?
>> > > Also did you consider the creepage along one internal layer to the second internal layer along the edge of the board?
>> > >
>> > > Thankyou in advance!
>> > Hi Deepak,
>> >
>> > For my application, I ended up using 50V/mil as a limit for trace-trace spacing on a single inner layer. If the application was airborne I probably would have been even more conservative. I did a lot of thermal cycle and long-term hi-pot testing to prove the design. The main worry was that any small amount of delamination could make an inner layer start to act like an outer layer, where we were using a 20V/mil rule. In this particular application, the planar XFMR was in a potted module and would not see large temperature swings in the field, so I determined the long-term risk of delamination was low. And yes, I did consider the creepage paths from the traces to the board edge.
>> Thankyou for your immediate response. This information really helps me with my project!
>>
>> Regards
>> Deepak B
>
>If you are designing computer, communication or audio equipment then section G.13 of IEC62368.1
>will give you a lot of useful information about pcb requirements.
>
>John

I've seen UL and CE limits for surface clearances but not seen
anything for pcb internal clearances, nearby traces or between layers.
Do you know of any specs for these?

Of course, you have to pay big to purchase the IEC standards, and
every one references a bunch of other ones.

On 2023-03-22 12:03, John Larkin wrote:
> On Wed, 22 Mar 2023 03:47:38 -0700 (PDT), John Walliker
> <jrwalliker@gmail.com> wrote:
>
>> On Wednesday, 22 March 2023 at 09:55:21 UTC, Deepak Bikkina wrote:
>>> On Tuesday, 21 March 2023 at 23:06:18 UTC+1, sea moss wrote:
>>>> On Tuesday, March 21, 2023 at 10:56:36?AM UTC-7, Deepak Bikkina wrote:
>>>>> On Monday, 28 May 2018 at 18:28:17 UTC+2, sea moss wrote:
>>>>>>> Integrated means, for the LLC resonant converter case, that the leakage inductor is embedded in the transformer construction. You need about 20% leakage, which is easy on a regular transformer (just pull the windings away from each other), but on a planar you cannot pull it away, so you need either a magnetic shunt, or assymetricc transformer windings construction
>>>>>>>
>>>>>> Glad you pointed that out. In this case I'm operating the LLC right around the "zero load regulation" point; i.e. the resonant frequency of the series C and leakage inductance. Running open loop with no frequency modulation. Mag inductance just needs to be large enough to be out of the way. (so it's essentially a series LC resonant converter, with isolation)
>>>>>>
>>>>>> Once I can figure out the most practical way to achieve the high isolation needed without making this thing too huge, my idea was to measure the leakage inductance, and add an external L if needed.
>>>>>>
>>>>>> Forgot to mention, because it didn't seem relevant until you just brought it up: the planar PCB consists of only secondary windings. The primary consists of a couple turns of HV insulated wire (rated to 25kV). So there's a pretty big gap between the top of the planar PCB and the core to fit the primary turns. Isolation from primary to secondary is 20kV and the LLC front end sits on a different card than this transformer.
>>>>> Hi Sea Moss,
>>>>>
>>>>> I happened to look at this post as I was having same doubt. Did you happen to find solution for the first question that you asked?
>>>>> Also did you consider the creepage along one internal layer to the second internal layer along the edge of the board?
>>>>>
>>>>> Thankyou in advance!
>>>> Hi Deepak,
>>>>
>>>> For my application, I ended up using 50V/mil as a limit for trace-trace spacing on a single inner layer. If the application was airborne I probably would have been even more conservative. I did a lot of thermal cycle and long-term hi-pot testing to prove the design. The main worry was that any small amount of delamination could make an inner layer start to act like an outer layer, where we were using a 20V/mil rule. In this particular application, the planar XFMR was in a potted module and would not see large temperature swings in the field, so I determined the long-term risk of delamination was low. And yes, I did consider the creepage paths from the traces to the board edge.
>>> Thankyou for your immediate response. This information really helps me with my project!
>>>
>>> Regards
>>> Deepak B
>>
>> If you are designing computer, communication or audio equipment then section G.13 of IEC62368.1
>> will give you a lot of useful information about pcb requirements.
>>
>> John
>
> I've seen UL and CE limits for surface clearances but not seen
> anything for pcb internal clearances, nearby traces or between layers.
> Do you know of any specs for these?
>
> Of course, you have to pay big to purchase the IEC standards, and
> every one references a bunch of other ones.
>

You can sometimes find late drafts of the standards online.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510

http://electrooptical.net
http://hobbs-eo.com

On Wed, 22 Mar 2023 12:51:50 -0400, Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:

>On 2023-03-22 12:03, John Larkin wrote:
>> On Wed, 22 Mar 2023 03:47:38 -0700 (PDT), John Walliker
>> <jrwalliker@gmail.com> wrote:
>>
>>> On Wednesday, 22 March 2023 at 09:55:21 UTC, Deepak Bikkina wrote:
>>>> On Tuesday, 21 March 2023 at 23:06:18 UTC+1, sea moss wrote:
>>>>> On Tuesday, March 21, 2023 at 10:56:36?AM UTC-7, Deepak Bikkina wrote:
>>>>>> On Monday, 28 May 2018 at 18:28:17 UTC+2, sea moss wrote:
>>>>>>>> Integrated means, for the LLC resonant converter case, that the leakage inductor is embedded in the transformer construction. You need about 20% leakage, which is easy on a regular transformer (just pull the windings away from each other), but on a planar you cannot pull it away, so you need either a magnetic shunt, or assymetricc transformer windings construction
>>>>>>>>
>>>>>>> Glad you pointed that out. In this case I'm operating the LLC right around the "zero load regulation" point; i.e. the resonant frequency of the series C and leakage inductance. Running open loop with no frequency modulation. Mag inductance just needs to be large enough to be out of the way. (so it's essentially a series LC resonant converter, with isolation)
>>>>>>>
>>>>>>> Once I can figure out the most practical way to achieve the high isolation needed without making this thing too huge, my idea was to measure the leakage inductance, and add an external L if needed.
>>>>>>>
>>>>>>> Forgot to mention, because it didn't seem relevant until you just brought it up: the planar PCB consists of only secondary windings. The primary consists of a couple turns of HV insulated wire (rated to 25kV). So there's a pretty big gap between the top of the planar PCB and the core to fit the primary turns. Isolation from primary to secondary is 20kV and the LLC front end sits on a different card than this transformer.
>>>>>> Hi Sea Moss,
>>>>>>
>>>>>> I happened to look at this post as I was having same doubt. Did you happen to find solution for the first question that you asked?
>>>>>> Also did you consider the creepage along one internal layer to the second internal layer along the edge of the board?
>>>>>>
>>>>>> Thankyou in advance!
>>>>> Hi Deepak,
>>>>>
>>>>> For my application, I ended up using 50V/mil as a limit for trace-trace spacing on a single inner layer. If the application was airborne I probably would have been even more conservative. I did a lot of thermal cycle and long-term hi-pot testing to prove the design. The main worry was that any small amount of delamination could make an inner layer start to act like an outer layer, where we were using a 20V/mil rule. In this particular application, the planar XFMR was in a potted module and would not see large temperature swings in the field, so I determined the long-term risk of delamination was low. And yes, I did consider the creepage paths from the traces to the board edge.
>>>> Thankyou for your immediate response. This information really helps me with my project!
>>>>
>>>> Regards
>>>> Deepak B
>>>
>>> If you are designing computer, communication or audio equipment then section G.13 of IEC62368.1
>>> will give you a lot of useful information about pcb requirements.
>>>
>>> John
>>
>> I've seen UL and CE limits for surface clearances but not seen
>> anything for pcb internal clearances, nearby traces or between layers.
>> Do you know of any specs for these?
>>
>> Of course, you have to pay big to purchase the IEC standards, and
>> every one references a bunch of other ones.
>>
>
>You can sometimes find late drafts of the standards online.

Yes. Also, many IEC standards are largely copped from other non-IEC
standards, and can be found with a little work. It may be that each
chapter in the donor standard becomes an individual IEC standard.

Joe Gwinn

On Wednesday, 22 March 2023 at 19:25:49 UTC, Joe Gwinn wrote:
> On Wed, 22 Mar 2023 12:51:50 -0400, Phil Hobbs
> <pcdhSpamM...@electrooptical.net> wrote:
>
> >On 2023-03-22 12:03, John Larkin wrote:
> >> On Wed, 22 Mar 2023 03:47:38 -0700 (PDT), John Walliker
> >> <jrwal...@gmail.com> wrote:
> >>
> >>> On Wednesday, 22 March 2023 at 09:55:21 UTC, Deepak Bikkina wrote:
> >>>> On Tuesday, 21 March 2023 at 23:06:18 UTC+1, sea moss wrote:
> >>>>> On Tuesday, March 21, 2023 at 10:56:36?AM UTC-7, Deepak Bikkina wrote:
> >>>>>> On Monday, 28 May 2018 at 18:28:17 UTC+2, sea moss wrote:
> >>>>>>>> Integrated means, for the LLC resonant converter case, that the leakage inductor is embedded in the transformer construction. You need about 20% leakage, which is easy on a regular transformer (just pull the windings away from each other), but on a planar you cannot pull it away, so you need either a magnetic shunt, or assymetricc transformer windings construction
> >>>>>>>>
> >>>>>>> Glad you pointed that out. In this case I'm operating the LLC right around the "zero load regulation" point; i.e. the resonant frequency of the series C and leakage inductance. Running open loop with no frequency modulation. Mag inductance just needs to be large enough to be out of the way.. (so it's essentially a series LC resonant converter, with isolation)
> >>>>>>>
> >>>>>>> Once I can figure out the most practical way to achieve the high isolation needed without making this thing too huge, my idea was to measure the leakage inductance, and add an external L if needed.
> >>>>>>>
> >>>>>>> Forgot to mention, because it didn't seem relevant until you just brought it up: the planar PCB consists of only secondary windings. The primary consists of a couple turns of HV insulated wire (rated to 25kV). So there's a pretty big gap between the top of the planar PCB and the core to fit the primary turns. Isolation from primary to secondary is 20kV and the LLC front end sits on a different card than this transformer.
> >>>>>> Hi Sea Moss,
> >>>>>>
> >>>>>> I happened to look at this post as I was having same doubt. Did you happen to find solution for the first question that you asked?
> >>>>>> Also did you consider the creepage along one internal layer to the second internal layer along the edge of the board?
> >>>>>>
> >>>>>> Thankyou in advance!
> >>>>> Hi Deepak,
> >>>>>
> >>>>> For my application, I ended up using 50V/mil as a limit for trace-trace spacing on a single inner layer. If the application was airborne I probably would have been even more conservative. I did a lot of thermal cycle and long-term hi-pot testing to prove the design. The main worry was that any small amount of delamination could make an inner layer start to act like an outer layer, where we were using a 20V/mil rule. In this particular application, the planar XFMR was in a potted module and would not see large temperature swings in the field, so I determined the long-term risk of delamination was low. And yes, I did consider the creepage paths from the traces to the board edge.
> >>>> Thankyou for your immediate response. This information really helps me with my project!
> >>>>
> >>>> Regards
> >>>> Deepak B
> >>>
> >>> If you are designing computer, communication or audio equipment then section G.13 of IEC62368.1
> >>> will give you a lot of useful information about pcb requirements.
> >>>
> >>> John
> >>
> >> I've seen UL and CE limits for surface clearances but not seen
> >> anything for pcb internal clearances, nearby traces or between layers.
> >> Do you know of any specs for these?
> >>
> >> Of course, you have to pay big to purchase the IEC standards, and
> >> every one references a bunch of other ones.
> >>
> >
> >You can sometimes find late drafts of the standards online.
> Yes. Also, many IEC standards are largely copped from other non-IEC
> standards, and can be found with a little work. It may be that each
> chapter in the donor standard becomes an individual IEC standard.
>
> Joe Gwinn

Most of JL's products probably count as test and measurement equipment
which is subject to IEC61010-1. This standard has tables of internal clearances
and thicknesses required for various voltages, environments and frequencies..

John

On Wed, 22 Mar 2023 13:58:21 -0700 (PDT), John Walliker
<jrwalliker@gmail.com> wrote:

>On Wednesday, 22 March 2023 at 19:25:49 UTC, Joe Gwinn wrote:
>> On Wed, 22 Mar 2023 12:51:50 -0400, Phil Hobbs
>> <pcdhSpamM...@electrooptical.net> wrote:
>>
>> >On 2023-03-22 12:03, John Larkin wrote:
>> >> On Wed, 22 Mar 2023 03:47:38 -0700 (PDT), John Walliker
>> >> <jrwal...@gmail.com> wrote:
>> >>
>> >>> On Wednesday, 22 March 2023 at 09:55:21 UTC, Deepak Bikkina wrote:
>> >>>> On Tuesday, 21 March 2023 at 23:06:18 UTC+1, sea moss wrote:
>> >>>>> On Tuesday, March 21, 2023 at 10:56:36?AM UTC-7, Deepak Bikkina wrote:
>> >>>>>> On Monday, 28 May 2018 at 18:28:17 UTC+2, sea moss wrote:
>> >>>>>>>> Integrated means, for the LLC resonant converter case, that the leakage inductor is embedded in the transformer construction. You need about 20% leakage, which is easy on a regular transformer (just pull the windings away from each other), but on a planar you cannot pull it away, so you need either a magnetic shunt, or assymetricc transformer windings construction
>> >>>>>>>>
>> >>>>>>> Glad you pointed that out. In this case I'm operating the LLC right around the "zero load regulation" point; i.e. the resonant frequency of the series C and leakage inductance. Running open loop with no frequency modulation. Mag inductance just needs to be large enough to be out of the way. (so it's essentially a series LC resonant converter, with isolation)
>> >>>>>>>
>> >>>>>>> Once I can figure out the most practical way to achieve the high isolation needed without making this thing too huge, my idea was to measure the leakage inductance, and add an external L if needed.
>> >>>>>>>
>> >>>>>>> Forgot to mention, because it didn't seem relevant until you just brought it up: the planar PCB consists of only secondary windings. The primary consists of a couple turns of HV insulated wire (rated to 25kV). So there's a pretty big gap between the top of the planar PCB and the core to fit the primary turns. Isolation from primary to secondary is 20kV and the LLC front end sits on a different card than this transformer.
>> >>>>>> Hi Sea Moss,
>> >>>>>>
>> >>>>>> I happened to look at this post as I was having same doubt. Did you happen to find solution for the first question that you asked?
>> >>>>>> Also did you consider the creepage along one internal layer to the second internal layer along the edge of the board?
>> >>>>>>
>> >>>>>> Thankyou in advance!
>> >>>>> Hi Deepak,
>> >>>>>
>> >>>>> For my application, I ended up using 50V/mil as a limit for trace-trace spacing on a single inner layer. If the application was airborne I probably would have been even more conservative. I did a lot of thermal cycle and long-term hi-pot testing to prove the design. The main worry was that any small amount of delamination could make an inner layer start to act like an outer layer, where we were using a 20V/mil rule. In this particular application, the planar XFMR was in a potted module and would not see large temperature swings in the field, so I determined the long-term risk of delamination was low. And yes, I did consider the creepage paths from the traces to the board edge.
>> >>>> Thankyou for your immediate response. This information really helps me with my project!
>> >>>>
>> >>>> Regards
>> >>>> Deepak B
>> >>>
>> >>> If you are designing computer, communication or audio equipment then section G.13 of IEC62368.1
>> >>> will give you a lot of useful information about pcb requirements.
>> >>>
>> >>> John
>> >>
>> >> I've seen UL and CE limits for surface clearances but not seen
>> >> anything for pcb internal clearances, nearby traces or between layers.
>> >> Do you know of any specs for these?
>> >>
>> >> Of course, you have to pay big to purchase the IEC standards, and
>> >> every one references a bunch of other ones.
>> >>
>> >
>> >You can sometimes find late drafts of the standards online.
>> Yes. Also, many IEC standards are largely copped from other non-IEC
>> standards, and can be found with a little work. It may be that each
>> chapter in the donor standard becomes an individual IEC standard.
>>
>> Joe Gwinn
>
>Most of JL's products probably count as test and measurement equipment
>which is subject to IEC61010-1. This standard has tables of internal clearances
>and thicknesses required for various voltages, environments and frequencies.

Yes, but where did these clearances et al come from? I've been
involved in such standards, and the corresponding IEC standard is very
close to the contributing standard, and the donor is often enough.
And, one can get the donor standard, but the IEC standards are often
prohibitively expensive, and change too fast to follow.

Joe Gwinn

On Wed, 22 Mar 2023 17:52:16 -0400, Joe Gwinn <joegwinn@comcast.net>
wrote:

>On Wed, 22 Mar 2023 13:58:21 -0700 (PDT), John Walliker
><jrwalliker@gmail.com> wrote:
>
>>On Wednesday, 22 March 2023 at 19:25:49 UTC, Joe Gwinn wrote:
>>> On Wed, 22 Mar 2023 12:51:50 -0400, Phil Hobbs
>>> <pcdhSpamM...@electrooptical.net> wrote:
>>>
>>> >On 2023-03-22 12:03, John Larkin wrote:
>>> >> On Wed, 22 Mar 2023 03:47:38 -0700 (PDT), John Walliker
>>> >> <jrwal...@gmail.com> wrote:
>>> >>
>>> >>> On Wednesday, 22 March 2023 at 09:55:21 UTC, Deepak Bikkina wrote:
>>> >>>> On Tuesday, 21 March 2023 at 23:06:18 UTC+1, sea moss wrote:
>>> >>>>> On Tuesday, March 21, 2023 at 10:56:36?AM UTC-7, Deepak Bikkina wrote:
>>> >>>>>> On Monday, 28 May 2018 at 18:28:17 UTC+2, sea moss wrote:
>>> >>>>>>>> Integrated means, for the LLC resonant converter case, that the leakage inductor is embedded in the transformer construction. You need about 20% leakage, which is easy on a regular transformer (just pull the windings away from each other), but on a planar you cannot pull it away, so you need either a magnetic shunt, or assymetricc transformer windings construction
>>> >>>>>>>>
>>> >>>>>>> Glad you pointed that out. In this case I'm operating the LLC right around the "zero load regulation" point; i.e. the resonant frequency of the series C and leakage inductance. Running open loop with no frequency modulation. Mag inductance just needs to be large enough to be out of the way. (so it's essentially a series LC resonant converter, with isolation)
>>> >>>>>>>
>>> >>>>>>> Once I can figure out the most practical way to achieve the high isolation needed without making this thing too huge, my idea was to measure the leakage inductance, and add an external L if needed.
>>> >>>>>>>
>>> >>>>>>> Forgot to mention, because it didn't seem relevant until you just brought it up: the planar PCB consists of only secondary windings. The primary consists of a couple turns of HV insulated wire (rated to 25kV). So there's a pretty big gap between the top of the planar PCB and the core to fit the primary turns. Isolation from primary to secondary is 20kV and the LLC front end sits on a different card than this transformer.
>>> >>>>>> Hi Sea Moss,
>>> >>>>>>
>>> >>>>>> I happened to look at this post as I was having same doubt. Did you happen to find solution for the first question that you asked?
>>> >>>>>> Also did you consider the creepage along one internal layer to the second internal layer along the edge of the board?
>>> >>>>>>
>>> >>>>>> Thankyou in advance!
>>> >>>>> Hi Deepak,
>>> >>>>>
>>> >>>>> For my application, I ended up using 50V/mil as a limit for trace-trace spacing on a single inner layer. If the application was airborne I probably would have been even more conservative. I did a lot of thermal cycle and long-term hi-pot testing to prove the design. The main worry was that any small amount of delamination could make an inner layer start to act like an outer layer, where we were using a 20V/mil rule. In this particular application, the planar XFMR was in a potted module and would not see large temperature swings in the field, so I determined the long-term risk of delamination was low. And yes, I did consider the creepage paths from the traces to the board edge.
>>> >>>> Thankyou for your immediate response. This information really helps me with my project!
>>> >>>>
>>> >>>> Regards
>>> >>>> Deepak B
>>> >>>
>>> >>> If you are designing computer, communication or audio equipment then section G.13 of IEC62368.1
>>> >>> will give you a lot of useful information about pcb requirements.
>>> >>>
>>> >>> John
>>> >>
>>> >> I've seen UL and CE limits for surface clearances but not seen
>>> >> anything for pcb internal clearances, nearby traces or between layers.
>>> >> Do you know of any specs for these?
>>> >>
>>> >> Of course, you have to pay big to purchase the IEC standards, and
>>> >> every one references a bunch of other ones.
>>> >>
>>> >
>>> >You can sometimes find late drafts of the standards online.
>>> Yes. Also, many IEC standards are largely copped from other non-IEC
>>> standards, and can be found with a little work. It may be that each
>>> chapter in the donor standard becomes an individual IEC standard.
>>>
>>> Joe Gwinn
>>
>>Most of JL's products probably count as test and measurement equipment
>>which is subject to IEC61010-1. This standard has tables of internal clearances
>>and thicknesses required for various voltages, environments and frequencies.
>
>Yes, but where did these clearances et al come from? I've been
>involved in such standards, and the corresponding IEC standard is very
>close to the contributing standard, and the donor is often enough.
>And, one can get the donor standard, but the IEC standards are often
>prohibitively expensive, and change too fast to follow.
>
>Joe Gwinn

That spec is $850, but there are drafts online.

On Wed, 22 Mar 2023 15:10:10 -0700, John Larkin
<jlarkin@highlandSNIPMEtechnology.com> wrote:

>On Wed, 22 Mar 2023 17:52:16 -0400, Joe Gwinn <joegwinn@comcast.net>
>wrote:
>
>>On Wed, 22 Mar 2023 13:58:21 -0700 (PDT), John Walliker
>><jrwalliker@gmail.com> wrote:
>>
>>>On Wednesday, 22 March 2023 at 19:25:49 UTC, Joe Gwinn wrote:
>>>> On Wed, 22 Mar 2023 12:51:50 -0400, Phil Hobbs
>>>> <pcdhSpamM...@electrooptical.net> wrote:
>>>>
>>>> >On 2023-03-22 12:03, John Larkin wrote:
>>>> >> On Wed, 22 Mar 2023 03:47:38 -0700 (PDT), John Walliker
>>>> >> <jrwal...@gmail.com> wrote:
>>>> >>
>>>> >>> On Wednesday, 22 March 2023 at 09:55:21 UTC, Deepak Bikkina wrote:
>>>> >>>> On Tuesday, 21 March 2023 at 23:06:18 UTC+1, sea moss wrote:
>>>> >>>>> On Tuesday, March 21, 2023 at 10:56:36?AM UTC-7, Deepak Bikkina wrote:
>>>> >>>>>> On Monday, 28 May 2018 at 18:28:17 UTC+2, sea moss wrote:
>>>> >>>>>>>> Integrated means, for the LLC resonant converter case, that the leakage inductor is embedded in the transformer construction. You need about 20% leakage, which is easy on a regular transformer (just pull the windings away from each other), but on a planar you cannot pull it away, so you need either a magnetic shunt, or assymetricc transformer windings construction
>>>> >>>>>>>>
>>>> >>>>>>> Glad you pointed that out. In this case I'm operating the LLC right around the "zero load regulation" point; i.e. the resonant frequency of the series C and leakage inductance. Running open loop with no frequency modulation. Mag inductance just needs to be large enough to be out of the way. (so it's essentially a series LC resonant converter, with isolation)
>>>> >>>>>>>
>>>> >>>>>>> Once I can figure out the most practical way to achieve the high isolation needed without making this thing too huge, my idea was to measure the leakage inductance, and add an external L if needed.
>>>> >>>>>>>
>>>> >>>>>>> Forgot to mention, because it didn't seem relevant until you just brought it up: the planar PCB consists of only secondary windings. The primary consists of a couple turns of HV insulated wire (rated to 25kV). So there's a pretty big gap between the top of the planar PCB and the core to fit the primary turns. Isolation from primary to secondary is 20kV and the LLC front end sits on a different card than this transformer.
>>>> >>>>>> Hi Sea Moss,
>>>> >>>>>>
>>>> >>>>>> I happened to look at this post as I was having same doubt. Did you happen to find solution for the first question that you asked?
>>>> >>>>>> Also did you consider the creepage along one internal layer to the second internal layer along the edge of the board?
>>>> >>>>>>
>>>> >>>>>> Thankyou in advance!
>>>> >>>>> Hi Deepak,
>>>> >>>>>
>>>> >>>>> For my application, I ended up using 50V/mil as a limit for trace-trace spacing on a single inner layer. If the application was airborne I probably would have been even more conservative. I did a lot of thermal cycle and long-term hi-pot testing to prove the design. The main worry was that any small amount of delamination could make an inner layer start to act like an outer layer, where we were using a 20V/mil rule. In this particular application, the planar XFMR was in a potted module and would not see large temperature swings in the field, so I determined the long-term risk of delamination was low. And yes, I did consider the creepage paths from the traces to the board edge.
>>>> >>>> Thankyou for your immediate response. This information really helps me with my project!
>>>> >>>>
>>>> >>>> Regards
>>>> >>>> Deepak B
>>>> >>>
>>>> >>> If you are designing computer, communication or audio equipment then section G.13 of IEC62368.1
>>>> >>> will give you a lot of useful information about pcb requirements.
>>>> >>>
>>>> >>> John
>>>> >>
>>>> >> I've seen UL and CE limits for surface clearances but not seen
>>>> >> anything for pcb internal clearances, nearby traces or between layers.
>>>> >> Do you know of any specs for these?
>>>> >>
>>>> >> Of course, you have to pay big to purchase the IEC standards, and
>>>> >> every one references a bunch of other ones.
>>>> >>
>>>> >
>>>> >You can sometimes find late drafts of the standards online.
>>>> Yes. Also, many IEC standards are largely copped from other non-IEC
>>>> standards, and can be found with a little work. It may be that each
>>>> chapter in the donor standard becomes an individual IEC standard.
>>>>
>>>> Joe Gwinn
>>>
>>>Most of JL's products probably count as test and measurement equipment
>>>which is subject to IEC61010-1. This standard has tables of internal clearances
>>>and thicknesses required for various voltages, environments and frequencies.
>>
>>Yes, but where did these clearances et al come from? I've been
>>involved in such standards, and the corresponding IEC standard is very
>>close to the contributing standard, and the donor is often enough.
>>And, one can get the donor standard, but the IEC standards are often
>>prohibitively expensive, and change too fast to follow.
>>
>>Joe Gwinn
>
>That spec is $850, but there are drafts online.

It that IEC spec complete, or do you need a swarm of them to have the
entire story?

Joe Gwinn

On Thursday, 23 March 2023 at 00:07:59 UTC, Joe Gwinn wrote:
> On Wed, 22 Mar 2023 15:10:10 -0700, John Larkin
> <jla...@highlandSNIPMEtechnology.com> wrote:
>
> >On Wed, 22 Mar 2023 17:52:16 -0400, Joe Gwinn <joeg...@comcast.net>
> >wrote:
> >
> >>On Wed, 22 Mar 2023 13:58:21 -0700 (PDT), John Walliker
> >><jrwal...@gmail.com> wrote:
> >>
> >>>On Wednesday, 22 March 2023 at 19:25:49 UTC, Joe Gwinn wrote:
> >>>> On Wed, 22 Mar 2023 12:51:50 -0400, Phil Hobbs
> >>>> <pcdhSpamM...@electrooptical.net> wrote:
> >>>>
> >>>> >On 2023-03-22 12:03, John Larkin wrote:
> >>>> >> On Wed, 22 Mar 2023 03:47:38 -0700 (PDT), John Walliker
> >>>> >> <jrwal...@gmail.com> wrote:
> >>>> >>
> >>>> >>> On Wednesday, 22 March 2023 at 09:55:21 UTC, Deepak Bikkina wrote:
> >>>> >>>> On Tuesday, 21 March 2023 at 23:06:18 UTC+1, sea moss wrote:
> >>>> >>>>> On Tuesday, March 21, 2023 at 10:56:36?AM UTC-7, Deepak Bikkina wrote:
> >>>> >>>>>> On Monday, 28 May 2018 at 18:28:17 UTC+2, sea moss wrote:
> >>>> >>>>>>>> Integrated means, for the LLC resonant converter case, that the leakage inductor is embedded in the transformer construction. You need about 20% leakage, which is easy on a regular transformer (just pull the windings away from each other), but on a planar you cannot pull it away, so you need either a magnetic shunt, or assymetricc transformer windings construction
> >>>> >>>>>>>>
> >>>> >>>>>>> Glad you pointed that out. In this case I'm operating the LLC right around the "zero load regulation" point; i.e. the resonant frequency of the series C and leakage inductance. Running open loop with no frequency modulation. Mag inductance just needs to be large enough to be out of the way. (so it's essentially a series LC resonant converter, with isolation)
> >>>> >>>>>>>
> >>>> >>>>>>> Once I can figure out the most practical way to achieve the high isolation needed without making this thing too huge, my idea was to measure the leakage inductance, and add an external L if needed.
> >>>> >>>>>>>
> >>>> >>>>>>> Forgot to mention, because it didn't seem relevant until you just brought it up: the planar PCB consists of only secondary windings. The primary consists of a couple turns of HV insulated wire (rated to 25kV). So there's a pretty big gap between the top of the planar PCB and the core to fit the primary turns. Isolation from primary to secondary is 20kV and the LLC front end sits on a different card than this transformer.
> >>>> >>>>>> Hi Sea Moss,
> >>>> >>>>>>
> >>>> >>>>>> I happened to look at this post as I was having same doubt. Did you happen to find solution for the first question that you asked?
> >>>> >>>>>> Also did you consider the creepage along one internal layer to the second internal layer along the edge of the board?
> >>>> >>>>>>
> >>>> >>>>>> Thankyou in advance!
> >>>> >>>>> Hi Deepak,
> >>>> >>>>>
> >>>> >>>>> For my application, I ended up using 50V/mil as a limit for trace-trace spacing on a single inner layer. If the application was airborne I probably would have been even more conservative. I did a lot of thermal cycle and long-term hi-pot testing to prove the design. The main worry was that any small amount of delamination could make an inner layer start to act like an outer layer, where we were using a 20V/mil rule. In this particular application, the planar XFMR was in a potted module and would not see large temperature swings in the field, so I determined the long-term risk of delamination was low. And yes, I did consider the creepage paths from the traces to the board edge.
> >>>> >>>> Thankyou for your immediate response. This information really helps me with my project!
> >>>> >>>>
> >>>> >>>> Regards
> >>>> >>>> Deepak B
> >>>> >>>
> >>>> >>> If you are designing computer, communication or audio equipment then section G.13 of IEC62368.1
> >>>> >>> will give you a lot of useful information about pcb requirements..
> >>>> >>>
> >>>> >>> John
> >>>> >>
> >>>> >> I've seen UL and CE limits for surface clearances but not seen
> >>>> >> anything for pcb internal clearances, nearby traces or between layers.
> >>>> >> Do you know of any specs for these?
> >>>> >>
> >>>> >> Of course, you have to pay big to purchase the IEC standards, and
> >>>> >> every one references a bunch of other ones.
> >>>> >>
> >>>> >
> >>>> >You can sometimes find late drafts of the standards online.
> >>>> Yes. Also, many IEC standards are largely copped from other non-IEC
> >>>> standards, and can be found with a little work. It may be that each
> >>>> chapter in the donor standard becomes an individual IEC standard.
> >>>>
> >>>> Joe Gwinn
> >>>
> >>>Most of JL's products probably count as test and measurement equipment
> >>>which is subject to IEC61010-1. This standard has tables of internal clearances
> >>>and thicknesses required for various voltages, environments and frequencies.
> >>
> >>Yes, but where did these clearances et al come from? I've been
> >>involved in such standards, and the corresponding IEC standard is very
> >>close to the contributing standard, and the donor is often enough.
> >>And, one can get the donor standard, but the IEC standards are often
> >>prohibitively expensive, and change too fast to follow.
> >>
> >>Joe Gwinn
> >
> >That spec is $850, but there are drafts online.
> It that IEC spec complete, or do you need a swarm of them to have the
> entire story?
>
> Joe Gwinn

The IEC61010-1 document is 157 pages long and is reasonably complete. None
of the standards are completely standalone, but this one is not too bad.
The 62368.1 2018 standard for information technology and audio-visual equipment
is 338 pages long and also contains most of what is needed to design a compliant
product. These standards are just for safety. EMC compliance requires a different
set of standards. One good thing is that there has been a lot of effort to harmonise
standards in recent years so that a single design has a good chance of being
compliant worldwide. Unfortunately, the FCC does like to do things slightly differently
to everyone else which complicates compliance testing.
John

On Thu, 23 Mar 2023 01:53:20 -0700 (PDT), John Walliker
<jrwalliker@gmail.com> wrote:

>On Thursday, 23 March 2023 at 00:07:59 UTC, Joe Gwinn wrote:
>> On Wed, 22 Mar 2023 15:10:10 -0700, John Larkin
>> <jla...@highlandSNIPMEtechnology.com> wrote:
>>
>> >On Wed, 22 Mar 2023 17:52:16 -0400, Joe Gwinn <joeg...@comcast.net>
>> >wrote:
>> >
>> >>On Wed, 22 Mar 2023 13:58:21 -0700 (PDT), John Walliker
>> >><jrwal...@gmail.com> wrote:
>> >>
>> >>>On Wednesday, 22 March 2023 at 19:25:49 UTC, Joe Gwinn wrote:
>> >>>> On Wed, 22 Mar 2023 12:51:50 -0400, Phil Hobbs
>> >>>> <pcdhSpamM...@electrooptical.net> wrote:
>> >>>>
>> >>>> >On 2023-03-22 12:03, John Larkin wrote:
>> >>>> >> On Wed, 22 Mar 2023 03:47:38 -0700 (PDT), John Walliker
>> >>>> >> <jrwal...@gmail.com> wrote:
>> >>>> >>
>> >>>> >>> On Wednesday, 22 March 2023 at 09:55:21 UTC, Deepak Bikkina wrote:
>> >>>> >>>> On Tuesday, 21 March 2023 at 23:06:18 UTC+1, sea moss wrote:
>> >>>> >>>>> On Tuesday, March 21, 2023 at 10:56:36?AM UTC-7, Deepak Bikkina wrote:
>> >>>> >>>>>> On Monday, 28 May 2018 at 18:28:17 UTC+2, sea moss wrote:
>> >>>> >>>>>>>> Integrated means, for the LLC resonant converter case, that the leakage inductor is embedded in the transformer construction. You need about 20% leakage, which is easy on a regular transformer (just pull the windings away from each other), but on a planar you cannot pull it away, so you need either a magnetic shunt, or assymetricc transformer windings construction
>> >>>> >>>>>>>>
>> >>>> >>>>>>> Glad you pointed that out. In this case I'm operating the LLC right around the "zero load regulation" point; i.e. the resonant frequency of the series C and leakage inductance. Running open loop with no frequency modulation. Mag inductance just needs to be large enough to be out of the way. (so it's essentially a series LC resonant converter, with isolation)
>> >>>> >>>>>>>
>> >>>> >>>>>>> Once I can figure out the most practical way to achieve the high isolation needed without making this thing too huge, my idea was to measure the leakage inductance, and add an external L if needed.
>> >>>> >>>>>>>
>> >>>> >>>>>>> Forgot to mention, because it didn't seem relevant until you just brought it up: the planar PCB consists of only secondary windings. The primary consists of a couple turns of HV insulated wire (rated to 25kV). So there's a pretty big gap between the top of the planar PCB and the core to fit the primary turns. Isolation from primary to secondary is 20kV and the LLC front end sits on a different card than this transformer.
>> >>>> >>>>>> Hi Sea Moss,
>> >>>> >>>>>>
>> >>>> >>>>>> I happened to look at this post as I was having same doubt. Did you happen to find solution for the first question that you asked?
>> >>>> >>>>>> Also did you consider the creepage along one internal layer to the second internal layer along the edge of the board?
>> >>>> >>>>>>
>> >>>> >>>>>> Thankyou in advance!
>> >>>> >>>>> Hi Deepak,
>> >>>> >>>>>
>> >>>> >>>>> For my application, I ended up using 50V/mil as a limit for trace-trace spacing on a single inner layer. If the application was airborne I probably would have been even more conservative. I did a lot of thermal cycle and long-term hi-pot testing to prove the design. The main worry was that any small amount of delamination could make an inner layer start to act like an outer layer, where we were using a 20V/mil rule. In this particular application, the planar XFMR was in a potted module and would not see large temperature swings in the field, so I determined the long-term risk of delamination was low. And yes, I did consider the creepage paths from the traces to the board edge.
>> >>>> >>>> Thankyou for your immediate response. This information really helps me with my project!
>> >>>> >>>>
>> >>>> >>>> Regards
>> >>>> >>>> Deepak B
>> >>>> >>>
>> >>>> >>> If you are designing computer, communication or audio equipment then section G.13 of IEC62368.1
>> >>>> >>> will give you a lot of useful information about pcb requirements.
>> >>>> >>>
>> >>>> >>> John
>> >>>> >>
>> >>>> >> I've seen UL and CE limits for surface clearances but not seen
>> >>>> >> anything for pcb internal clearances, nearby traces or between layers.
>> >>>> >> Do you know of any specs for these?
>> >>>> >>
>> >>>> >> Of course, you have to pay big to purchase the IEC standards, and
>> >>>> >> every one references a bunch of other ones.
>> >>>> >>
>> >>>> >
>> >>>> >You can sometimes find late drafts of the standards online.
>> >>>> Yes. Also, many IEC standards are largely copped from other non-IEC
>> >>>> standards, and can be found with a little work. It may be that each
>> >>>> chapter in the donor standard becomes an individual IEC standard.
>> >>>>
>> >>>> Joe Gwinn
>> >>>
>> >>>Most of JL's products probably count as test and measurement equipment
>> >>>which is subject to IEC61010-1. This standard has tables of internal clearances
>> >>>and thicknesses required for various voltages, environments and frequencies.
>> >>
>> >>Yes, but where did these clearances et al come from? I've been
>> >>involved in such standards, and the corresponding IEC standard is very
>> >>close to the contributing standard, and the donor is often enough.
>> >>And, one can get the donor standard, but the IEC standards are often
>> >>prohibitively expensive, and change too fast to follow.
>> >>
>> >>Joe Gwinn
>> >
>> >That spec is $850, but there are drafts online.
>> It that IEC spec complete, or do you need a swarm of them to have the
>> entire story?
>>
>> Joe Gwinn
>
>The IEC61010-1 document is 157 pages long and is reasonably complete. None
>of the standards are completely standalone, but this one is not too bad.
>The 62368.1 2018 standard for information technology and audio-visual equipment
>is 338 pages long and also contains most of what is needed to design a compliant
>product. These standards are just for safety. EMC compliance requires a different
>set of standards. One good thing is that there has been a lot of effort to harmonise
>standards in recent years so that a single design has a good chance of being
>compliant worldwide. Unfortunately, the FCC does like to do things slightly differently
>to everyone else which complicates compliance testing.

I worked at the FCC in the mid 1970s. As befits a US Federal
regulatory agency, it is lawyer dominated, with a very loose grip on
engineering. I learned more law than they learned engineering.

Joe Gwinn