The multi-value option on the Espresso logic-minimization software can
be used to solve the "input-encoding" problem, where you have say some
m-bit ROM and some number of outputs n > m, and you want to find out
assigning which bit vectors in the ROM to what output vectors will
result in the smallest decode logic.

The documentation isn't particularly helpful:

<http://bear.ces.cwru.edu/eecs_cad/man_octtools_espresso_inputs.html>

the closest relevant example I can find is Example 2:

"This example shows a description of a multiple-valued function with 5
binary variables and 3 multiple-valued variables (8 variables total)
where the multiple-valued variables have sizes of 4 27 and 10 (note that
the last multiple-valued variable is the "output" and also encodes the
ON -set, DC -set and OFF -set information)."

.mv 8 5 4 27 10
.ilb in1 in2 in3 in4 in5
.label var=5 part1 part2 part3 part4
.label var=6 a b c d e f g h i j k l m n
o p q r s t u v w x y z a1
.label var=7 out1 out2 out3 out4 out5 out6
out7 out8 out9 out10
0-010|1000|100000000000000000000000000|0010000000
10-10|1000|010000000000000000000000000|1000000000
0-111|1000|001000000000000000000000000|0001000000
0-10-|1000|000100000000000000000000000|0001000000
00000|1000|000010000000000000000000000|1000000000
00010|1000|000001000000000000000000000|0010000000
01001|1000|000000100000000000000000000|0000000010
0101-|1000|000000010000000000000000000|0000000000
0-0-0|1000|000000001000000000000000000|1000000000
10000|1000|000000000100000000000000000|0000000000
11100|1000|000000000010000000000000000|0010000000
10-10|1000|000000000001000000000000000|0000000000
11111|1000|000000000000100000000000000|0010000000
.
.
.
11111|0001|000000000000000000000000001|000000000

For myself I basically just want to find out how to have X bits of
external input and Y bits of ROM and optimize the encoding in ROM such
that the decode logic is minimized, but I'm struggling to figure out
this input file syntax..

On Monday, June 26, 2023 at 5:34:47 PM UTC-4, bitrex wrote:
> The multi-value option on the Espresso logic-minimization software can
> be used to solve the "input-encoding" problem, where you have say some
> m-bit ROM and some number of outputs n > m, and you want to find out
> assigning which bit vectors in the ROM to what output vectors will
> result in the smallest decode logic.
>
> The documentation isn't particularly helpful:
>
> <http://bear.ces.cwru.edu/eecs_cad/man_octtools_espresso_inputs.html>
>
> the closest relevant example I can find is Example 2:
>
> "This example shows a description of a multiple-valued function with 5
> binary variables and 3 multiple-valued variables (8 variables total)
> where the multiple-valued variables have sizes of 4 27 and 10 (note that
> the last multiple-valued variable is the "output" and also encodes the
> ON -set, DC -set and OFF -set information)."
>
> .mv 8 5 4 27 10
> .ilb in1 in2 in3 in4 in5
> .label var=5 part1 part2 part3 part4
> .label var=6 a b c d e f g h i j k l m n
> o p q r s t u v w x y z a1
> .label var=7 out1 out2 out3 out4 out5 out6
> out7 out8 out9 out10
> 0-010|1000|100000000000000000000000000|0010000000
> 10-10|1000|010000000000000000000000000|1000000000
> 0-111|1000|001000000000000000000000000|0001000000
> 0-10-|1000|000100000000000000000000000|0001000000
> 00000|1000|000010000000000000000000000|1000000000
> 00010|1000|000001000000000000000000000|0010000000
> 01001|1000|000000100000000000000000000|0000000010
> 0101-|1000|000000010000000000000000000|0000000000
> 0-0-0|1000|000000001000000000000000000|1000000000
> 10000|1000|000000000100000000000000000|0000000000
> 11100|1000|000000000010000000000000000|0010000000
> 10-10|1000|000000000001000000000000000|0000000000
> 11111|1000|000000000000100000000000000|0010000000
> .
> .
> .
> 11111|0001|000000000000000000000000001|000000000
>
>
>
> For myself I basically just want to find out how to have X bits of
> external input and Y bits of ROM and optimize the encoding in ROM such
> that the decode logic is minimized, but I'm struggling to figure out
> this input file syntax..

This isn't 1980 anymore, no one is all that concerned with saving memory, unless it's some super expensive high performance type. Get a "ROM" with wider words, this can synthesized with a composite stack using parallel addressing as well part upgrade. Whoever wrote the description in the link is a worthless idiot.

On 6/28/2023 6:08 PM, Fred Bloggs wrote:
> On Monday, June 26, 2023 at 5:34:47 PM UTC-4, bitrex wrote:
>> The multi-value option on the Espresso logic-minimization software can
>> be used to solve the "input-encoding" problem, where you have say some
>> m-bit ROM and some number of outputs n > m, and you want to find out
>> assigning which bit vectors in the ROM to what output vectors will
>> result in the smallest decode logic.
>>
>> The documentation isn't particularly helpful:
>>
>> <http://bear.ces.cwru.edu/eecs_cad/man_octtools_espresso_inputs.html>
>>
>> the closest relevant example I can find is Example 2:
>>
>> "This example shows a description of a multiple-valued function with 5
>> binary variables and 3 multiple-valued variables (8 variables total)
>> where the multiple-valued variables have sizes of 4 27 and 10 (note that
>> the last multiple-valued variable is the "output" and also encodes the
>> ON -set, DC -set and OFF -set information)."
>>
>> .mv 8 5 4 27 10
>> .ilb in1 in2 in3 in4 in5
>> .label var=5 part1 part2 part3 part4
>> .label var=6 a b c d e f g h i j k l m n
>> o p q r s t u v w x y z a1
>> .label var=7 out1 out2 out3 out4 out5 out6
>> out7 out8 out9 out10
>> 0-010|1000|100000000000000000000000000|0010000000
>> 10-10|1000|010000000000000000000000000|1000000000
>> 0-111|1000|001000000000000000000000000|0001000000
>> 0-10-|1000|000100000000000000000000000|0001000000
>> 00000|1000|000010000000000000000000000|1000000000
>> 00010|1000|000001000000000000000000000|0010000000
>> 01001|1000|000000100000000000000000000|0000000010
>> 0101-|1000|000000010000000000000000000|0000000000
>> 0-0-0|1000|000000001000000000000000000|1000000000
>> 10000|1000|000000000100000000000000000|0000000000
>> 11100|1000|000000000010000000000000000|0010000000
>> 10-10|1000|000000000001000000000000000|0000000000
>> 11111|1000|000000000000100000000000000|0010000000
>> .
>> .
>> .
>> 11111|0001|000000000000000000000000001|000000000
>>
>>
>>
>> For myself I basically just want to find out how to have X bits of
>> external input and Y bits of ROM and optimize the encoding in ROM such
>> that the decode logic is minimized, but I'm struggling to figure out
>> this input file syntax..
>
> This isn't 1980 anymore, no one is all that concerned with saving memory, unless it's some super expensive high performance type. Get a "ROM" with wider words, this can synthesized with a composite stack using parallel addressing as well part upgrade. Whoever wrote the description in the link is a worthless idiot.

I figured out how it works, and Espresso-MV only gets you part of the
way there for the input-encoding problem, vs just minimizing a Boolean
function.

It outputs a set of constraints, where the output decode logic is
minimized when an input encoding can be found such that the constraint
terms all lie on the faces of a Boolean hypercube.

See e.g. the four-variable problem on the last two pages here:

<https://www.tud.ttu.ee/im/Peeter.Ellervee/IAS0540/espresso-explained.pdf>

and see how the states are encoded such that the path around
the square makes it so all the constraint terms have a Hamming distance
of one from each other.

On Wednesday, June 28, 2023 at 11:23:12 PM UTC-4, bitrex wrote:
> On 6/28/2023 6:08 PM, Fred Bloggs wrote:
> > On Monday, June 26, 2023 at 5:34:47 PM UTC-4, bitrex wrote:
> >> The multi-value option on the Espresso logic-minimization software can
> >> be used to solve the "input-encoding" problem, where you have say some
> >> m-bit ROM and some number of outputs n > m, and you want to find out
> >> assigning which bit vectors in the ROM to what output vectors will
> >> result in the smallest decode logic.
> >>
> >> The documentation isn't particularly helpful:
> >>
> >> <http://bear.ces.cwru.edu/eecs_cad/man_octtools_espresso_inputs.html>
> >>
> >> the closest relevant example I can find is Example 2:
> >>
> >> "This example shows a description of a multiple-valued function with 5
> >> binary variables and 3 multiple-valued variables (8 variables total)
> >> where the multiple-valued variables have sizes of 4 27 and 10 (note that
> >> the last multiple-valued variable is the "output" and also encodes the
> >> ON -set, DC -set and OFF -set information)."
> >>
> >> .mv 8 5 4 27 10
> >> .ilb in1 in2 in3 in4 in5
> >> .label var=5 part1 part2 part3 part4
> >> .label var=6 a b c d e f g h i j k l m n
> >> o p q r s t u v w x y z a1
> >> .label var=7 out1 out2 out3 out4 out5 out6
> >> out7 out8 out9 out10
> >> 0-010|1000|100000000000000000000000000|0010000000
> >> 10-10|1000|010000000000000000000000000|1000000000
> >> 0-111|1000|001000000000000000000000000|0001000000
> >> 0-10-|1000|000100000000000000000000000|0001000000
> >> 00000|1000|000010000000000000000000000|1000000000
> >> 00010|1000|000001000000000000000000000|0010000000
> >> 01001|1000|000000100000000000000000000|0000000010
> >> 0101-|1000|000000010000000000000000000|0000000000
> >> 0-0-0|1000|000000001000000000000000000|1000000000
> >> 10000|1000|000000000100000000000000000|0000000000
> >> 11100|1000|000000000010000000000000000|0010000000
> >> 10-10|1000|000000000001000000000000000|0000000000
> >> 11111|1000|000000000000100000000000000|0010000000
> >> .
> >> .
> >> .
> >> 11111|0001|000000000000000000000000001|000000000
> >>
> >>
> >>
> >> For myself I basically just want to find out how to have X bits of
> >> external input and Y bits of ROM and optimize the encoding in ROM such
> >> that the decode logic is minimized, but I'm struggling to figure out
> >> this input file syntax..
> >
> > This isn't 1980 anymore, no one is all that concerned with saving memory, unless it's some super expensive high performance type. Get a "ROM" with wider words, this can synthesized with a composite stack using parallel addressing as well part upgrade. Whoever wrote the description in the link is a worthless idiot.
> I figured out how it works, and Espresso-MV only gets you part of the
> way there for the input-encoding problem, vs just minimizing a Boolean
> function.
>
> It outputs a set of constraints, where the output decode logic is
> minimized when an input encoding can be found such that the constraint
> terms all lie on the faces of a Boolean hypercube.
>
> See e.g. the four-variable problem on the last two pages here:
>
> <https://www.tud.ttu.ee/im/Peeter.Ellervee/IAS0540/espresso-explained.pdf>
>
> and see how the states are encoded such that the path around
> the square makes it so all the constraint terms have a Hamming distance
> of one from each other.

I don't see how you get more minimum than a memory table look-up.

On Wed, 28 Jun 2023 15:08:41 -0700 (PDT), Fred Bloggs
<bloggs.fredbloggs.fred@gmail.com> wrote:

>On Monday, June 26, 2023 at 5:34:47?PM UTC-4, bitrex wrote:
>> The multi-value option on the Espresso logic-minimization software can
>> be used to solve the "input-encoding" problem, where you have say some
>> m-bit ROM and some number of outputs n > m, and you want to find out
>> assigning which bit vectors in the ROM to what output vectors will
>> result in the smallest decode logic.
>>
>> The documentation isn't particularly helpful:
>>
>> <http://bear.ces.cwru.edu/eecs_cad/man_octtools_espresso_inputs.html>
>>
>> the closest relevant example I can find is Example 2:
>>
>> "This example shows a description of a multiple-valued function with 5
>> binary variables and 3 multiple-valued variables (8 variables total)
>> where the multiple-valued variables have sizes of 4 27 and 10 (note that
>> the last multiple-valued variable is the "output" and also encodes the
>> ON -set, DC -set and OFF -set information)."
>>
>> .mv 8 5 4 27 10
>> .ilb in1 in2 in3 in4 in5
>> .label var=5 part1 part2 part3 part4
>> .label var=6 a b c d e f g h i j k l m n
>> o p q r s t u v w x y z a1
>> .label var=7 out1 out2 out3 out4 out5 out6
>> out7 out8 out9 out10
>> 0-010|1000|100000000000000000000000000|0010000000
>> 10-10|1000|010000000000000000000000000|1000000000
>> 0-111|1000|001000000000000000000000000|0001000000
>> 0-10-|1000|000100000000000000000000000|0001000000
>> 00000|1000|000010000000000000000000000|1000000000
>> 00010|1000|000001000000000000000000000|0010000000
>> 01001|1000|000000100000000000000000000|0000000010
>> 0101-|1000|000000010000000000000000000|0000000000
>> 0-0-0|1000|000000001000000000000000000|1000000000
>> 10000|1000|000000000100000000000000000|0000000000
>> 11100|1000|000000000010000000000000000|0010000000
>> 10-10|1000|000000000001000000000000000|0000000000
>> 11111|1000|000000000000100000000000000|0010000000
>> .
>> .
>> .
>> 11111|0001|000000000000000000000000001|000000000
>>
>>
>>
>> For myself I basically just want to find out how to have X bits of
>> external input and Y bits of ROM and optimize the encoding in ROM such
>> that the decode logic is minimized, but I'm struggling to figure out
>> this input file syntax..
>
>This isn't 1980 anymore, no one is all that concerned with saving memory, unless it's some super expensive high performance type. Get a "ROM" with wider words, this can synthesized with a composite stack using parallel addressing as well part upgrade. Whoever wrote the description in the link is a worthless idiot.

The FPGA tools take your suggestion and map it into their
architecture. The days of Karnaugh maps are long gone.

On 6/29/2023 5:26 PM, John Larkin wrote:
> On Wed, 28 Jun 2023 15:08:41 -0700 (PDT), Fred Bloggs
> <bloggs.fredbloggs.fred@gmail.com> wrote:
>
>> On Monday, June 26, 2023 at 5:34:47?PM UTC-4, bitrex wrote:
>>> The multi-value option on the Espresso logic-minimization software can
>>> be used to solve the "input-encoding" problem, where you have say some
>>> m-bit ROM and some number of outputs n > m, and you want to find out
>>> assigning which bit vectors in the ROM to what output vectors will
>>> result in the smallest decode logic.
>>>
>>> The documentation isn't particularly helpful:
>>>
>>> <http://bear.ces.cwru.edu/eecs_cad/man_octtools_espresso_inputs.html>
>>>
>>> the closest relevant example I can find is Example 2:
>>>
>>> "This example shows a description of a multiple-valued function with 5
>>> binary variables and 3 multiple-valued variables (8 variables total)
>>> where the multiple-valued variables have sizes of 4 27 and 10 (note that
>>> the last multiple-valued variable is the "output" and also encodes the
>>> ON -set, DC -set and OFF -set information)."
>>>
>>> .mv 8 5 4 27 10
>>> .ilb in1 in2 in3 in4 in5
>>> .label var=5 part1 part2 part3 part4
>>> .label var=6 a b c d e f g h i j k l m n
>>> o p q r s t u v w x y z a1
>>> .label var=7 out1 out2 out3 out4 out5 out6
>>> out7 out8 out9 out10
>>> 0-010|1000|100000000000000000000000000|0010000000
>>> 10-10|1000|010000000000000000000000000|1000000000
>>> 0-111|1000|001000000000000000000000000|0001000000
>>> 0-10-|1000|000100000000000000000000000|0001000000
>>> 00000|1000|000010000000000000000000000|1000000000
>>> 00010|1000|000001000000000000000000000|0010000000
>>> 01001|1000|000000100000000000000000000|0000000010
>>> 0101-|1000|000000010000000000000000000|0000000000
>>> 0-0-0|1000|000000001000000000000000000|1000000000
>>> 10000|1000|000000000100000000000000000|0000000000
>>> 11100|1000|000000000010000000000000000|0010000000
>>> 10-10|1000|000000000001000000000000000|0000000000
>>> 11111|1000|000000000000100000000000000|0010000000
>>> .
>>> .
>>> .
>>> 11111|0001|000000000000000000000000001|000000000
>>>
>>>
>>>
>>> For myself I basically just want to find out how to have X bits of
>>> external input and Y bits of ROM and optimize the encoding in ROM such
>>> that the decode logic is minimized, but I'm struggling to figure out
>>> this input file syntax..
>>
>> This isn't 1980 anymore, no one is all that concerned with saving memory, unless it's some super expensive high performance type. Get a "ROM" with wider words, this can synthesized with a composite stack using parallel addressing as well part upgrade. Whoever wrote the description in the link is a worthless idiot.
>
> The FPGA tools take your suggestion and map it into their
> architecture. The days of Karnaugh maps are long gone.
>

Pretty sure the undergrad-textbook Karnaugh maps were always largely
pedagogical tool; the digital systems of even the 1950s already needed
more complexity than could be easily analyzed graphically.

I suppose someone had to build the Ur-computer without computer-aided
design but computers were helping to design computers very early on.

On 6/29/2023 5:26 PM, John Larkin wrote:
> On Wed, 28 Jun 2023 15:08:41 -0700 (PDT), Fred Bloggs
> <bloggs.fredbloggs.fred@gmail.com> wrote:
>
>> On Monday, June 26, 2023 at 5:34:47?PM UTC-4, bitrex wrote:
>>> The multi-value option on the Espresso logic-minimization software can
>>> be used to solve the "input-encoding" problem, where you have say some
>>> m-bit ROM and some number of outputs n > m, and you want to find out
>>> assigning which bit vectors in the ROM to what output vectors will
>>> result in the smallest decode logic.
>>>
>>> The documentation isn't particularly helpful:
>>>
>>> <http://bear.ces.cwru.edu/eecs_cad/man_octtools_espresso_inputs.html>
>>>
>>> the closest relevant example I can find is Example 2:
>>>
>>> "This example shows a description of a multiple-valued function with 5
>>> binary variables and 3 multiple-valued variables (8 variables total)
>>> where the multiple-valued variables have sizes of 4 27 and 10 (note that
>>> the last multiple-valued variable is the "output" and also encodes the
>>> ON -set, DC -set and OFF -set information)."
>>>
>>> .mv 8 5 4 27 10
>>> .ilb in1 in2 in3 in4 in5
>>> .label var=5 part1 part2 part3 part4
>>> .label var=6 a b c d e f g h i j k l m n
>>> o p q r s t u v w x y z a1
>>> .label var=7 out1 out2 out3 out4 out5 out6
>>> out7 out8 out9 out10
>>> 0-010|1000|100000000000000000000000000|0010000000
>>> 10-10|1000|010000000000000000000000000|1000000000
>>> 0-111|1000|001000000000000000000000000|0001000000
>>> 0-10-|1000|000100000000000000000000000|0001000000
>>> 00000|1000|000010000000000000000000000|1000000000
>>> 00010|1000|000001000000000000000000000|0010000000
>>> 01001|1000|000000100000000000000000000|0000000010
>>> 0101-|1000|000000010000000000000000000|0000000000
>>> 0-0-0|1000|000000001000000000000000000|1000000000
>>> 10000|1000|000000000100000000000000000|0000000000
>>> 11100|1000|000000000010000000000000000|0010000000
>>> 10-10|1000|000000000001000000000000000|0000000000
>>> 11111|1000|000000000000100000000000000|0010000000
>>> .
>>> .
>>> .
>>> 11111|0001|000000000000000000000000001|000000000
>>>
>>>
>>>
>>> For myself I basically just want to find out how to have X bits of
>>> external input and Y bits of ROM and optimize the encoding in ROM such
>>> that the decode logic is minimized, but I'm struggling to figure out
>>> this input file syntax..
>>
>> This isn't 1980 anymore, no one is all that concerned with saving memory, unless it's some super expensive high performance type. Get a "ROM" with wider words, this can synthesized with a composite stack using parallel addressing as well part upgrade. Whoever wrote the description in the link is a worthless idiot.
>
> The FPGA tools take your suggestion and map it into their
> architecture. The days of Karnaugh maps are long gone.
>

Incidentally Maurice Karnaugh passed away just last November, at the age
of 98

On 2023-06-29 17:26, John Larkin wrote:
> On Wed, 28 Jun 2023 15:08:41 -0700 (PDT), Fred Bloggs
> <bloggs.fredbloggs.fred@gmail.com> wrote:
>
>> On Monday, June 26, 2023 at 5:34:47?PM UTC-4, bitrex wrote:

>>> <snip> For myself I basically just want to find out how to have X
>>> bits of external input and Y bits of ROM and optimize the
>>> encoding in ROM such that the decode logic is minimized, but I'm
>>> struggling to figure out this input file syntax..
>>
>> This isn't 1980 anymore, no one is all that concerned with saving
>> memory, unless it's some super expensive high performance type. Get
>> a "ROM" with wider words, this can synthesized with a composite
>> stack using parallel addressing as well part upgrade. Whoever
>> wrote the description in the link is a worthless idiot.
>
> The FPGA tools take your suggestion and map it into their
> architecture. The days of Karnaugh maps are long gone.

Karnaugh maps take about 10 minutes to learn from a standing start. I
know this because, long ago when I was a second-year undergraduate, I
taught everybody in my physics lab section how to do it. (There was a
logic minimization segment to the lab assignment.)

It runs out of gas past three or four inputs, but that's plenty for
using multifunction gates, for instance.

MFGs are super useful--they're fast, and you can make any two-input
logic function from one of two types of three-input gates, so you don't
need to keep a whole lot of types.

So every once in awhile I need to use a Karnaugh map, even still.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510

http://electrooptical.net
http://hobbs-eo.com

On 6/29/2023 10:13 PM, Phil Hobbs wrote:
> On 2023-06-29 17:26, John Larkin wrote:
>> On Wed, 28 Jun 2023 15:08:41 -0700 (PDT), Fred Bloggs
>> <bloggs.fredbloggs.fred@gmail.com> wrote:
>>
>>> On Monday, June 26, 2023 at 5:34:47?PM UTC-4, bitrex wrote:
>
>>>> <snip> For myself I basically just want to find out how to have X
>>>> bits of external input and Y bits of ROM and optimize the
>>>> encoding in ROM such that the decode logic is minimized, but I'm
>>>> struggling to figure out this input file syntax..
>>>
>>> This isn't 1980 anymore, no one is all that concerned with saving
>>> memory, unless it's some super expensive high performance type. Get
>>> a "ROM" with wider words, this can synthesized with a composite
>>> stack using parallel addressing as well part upgrade.  Whoever
>>> wrote the description in the link is a worthless idiot.
>>
>> The FPGA tools take your suggestion and map it into their
>> architecture. The days of Karnaugh maps are long gone.
>
> Karnaugh maps take about 10 minutes to learn from a standing start.  I
> know this because, long ago when I was a second-year undergraduate, I
> taught everybody in my physics lab section how to do it.  (There was a
> logic minimization segment to the lab assignment.)
>
> It runs out of gas past three or four inputs, but that's plenty for
> using multifunction gates, for instance.
>
> MFGs are super useful--they're fast, and you can make any two-input
> logic function from one of two types of three-input gates, so you don't
> need to keep a whole lot of types.
>
> So every once in awhile I need to use a Karnaugh map, even still.
>
> Cheers
>
> Phil Hobbs
>

"Logic Friday' will jointly minimize up to 16 inputs and outputs, and
spit out a gate diagram optimized for either die area or the standard
74xxxxxxxx series ICs.

<https://download.cnet.com/Logic-Friday/3000-20415_4-75848245.html>

It'll also spit out a C function which might occasionally be useful, I
think I remember a post one time about someone using one of the really
tiny 8-bitters, with like 256 bytes of RAM just to implement a weird
logic function.

On Thursday, June 29, 2023 at 10:13:51 PM UTC-4, Phil Hobbs wrote:
> On 2023-06-29 17:26, John Larkin wrote:
> > On Wed, 28 Jun 2023 15:08:41 -0700 (PDT), Fred Bloggs
> > <bloggs.fred...@gmail.com> wrote:
> >
> >> On Monday, June 26, 2023 at 5:34:47?PM UTC-4, bitrex wrote:
> >>> <snip> For myself I basically just want to find out how to have X
> >>> bits of external input and Y bits of ROM and optimize the
> >>> encoding in ROM such that the decode logic is minimized, but I'm
> >>> struggling to figure out this input file syntax..
> >>
> >> This isn't 1980 anymore, no one is all that concerned with saving
> >> memory, unless it's some super expensive high performance type. Get
> >> a "ROM" with wider words, this can synthesized with a composite
> >> stack using parallel addressing as well part upgrade. Whoever
> >> wrote the description in the link is a worthless idiot.
> >
> > The FPGA tools take your suggestion and map it into their
> > architecture. The days of Karnaugh maps are long gone.
> Karnaugh maps take about 10 minutes to learn from a standing start. I
> know this because, long ago when I was a second-year undergraduate, I
> taught everybody in my physics lab section how to do it. (There was a
> logic minimization segment to the lab assignment.)
>
> It runs out of gas past three or four inputs, but that's plenty for
> using multifunction gates, for instance.
>
> MFGs are super useful--they're fast, and you can make any two-input
> logic function from one of two types of three-input gates, so you don't
> need to keep a whole lot of types.
>
> So every once in awhile I need to use a Karnaugh map, even still.

They're good for "hazard-free" logic synthesis and creation of sequencing through an ASM.

The best minimizer out there for MSI level design is "bubble-logic".

>
> Cheers
>
> Phil Hobbs
>
> --
> Dr Philip C D Hobbs
> Principal Consultant
> ElectroOptical Innovations LLC / Hobbs ElectroOptics
> Optics, Electro-optics, Photonics, Analog Electronics
> Briarcliff Manor NY 10510
>
> http://electrooptical.net
> http://hobbs-eo.com