Has anyone used filled vias? Epoxy? Copper?

I need thermal conductivity, as in a D2PAK on one side of a board and
a heat sink on the other.

torsdag den 10. august 2023 kl. 04.45.14 UTC+2 skrev John Larkin:
> Has anyone used filled vias? Epoxy? Copper?
>
> I need thermal conductivity, as in a D2PAK on one side of a board and
> a heat sink on the other.

if you don't mind spending the extra ~$300 jlcpcb will do prototypes with copper filled and plated over vias claiming 8W/m.k

https://cart.jlcpcb.com/quote?orderType=1&stencilLayer=4&stencilWidth=100&stencilLength=100&stencilCounts=5

On Thu, 10 Aug 2023 01:45:06 -0700 (PDT), Lasse Langwadt Christensen
<langwadt@fonz.dk> wrote:

>torsdag den 10. august 2023 kl. 04.45.14 UTC+2 skrev John Larkin:
>> Has anyone used filled vias? Epoxy? Copper?
>>
>> I need thermal conductivity, as in a D2PAK on one side of a board and
>> a heat sink on the other.
>
>if you don't mind spending the extra ~$300 jlcpcb will do prototypes with copper filled and plated over vias claiming 8W/m.k
>
>https://cart.jlcpcb.com/quote?orderType=1&stencilLayer=4&stencilWidth=100&stencilLength=100&stencilCounts=5

Pure copper is 400!

8 w/m-k is the sort of value you can get from a filled epoxy. I'd
probably use a plastic via fill, which I understand is cheaper and
will reduce the thermal resistance of a via by 2:1 or some such.

Maybe we can specify heavier plating in the vias too.

Our usual via is about 75 k/w, top to bottom on a board. 200 of them
would be 0.375 k/w, which is OK. Half of that would be better.

On 10/08/2023 11:55 am, John Larkin wrote:
> On Thu, 10 Aug 2023 01:45:06 -0700 (PDT), Lasse Langwadt Christensen
> <langwadt@fonz.dk> wrote:
>
>> torsdag den 10. august 2023 kl. 04.45.14 UTC+2 skrev John Larkin:
>>> Has anyone used filled vias? Epoxy? Copper?
>>>
>>> I need thermal conductivity, as in a D2PAK on one side of a board and
>>> a heat sink on the other.
>>
>> if you don't mind spending the extra ~$300 jlcpcb will do prototypes with copper filled and plated over vias claiming 8W/m.k
>>
>> https://cart.jlcpcb.com/quote?orderType=1&stencilLayer=4&stencilWidth=100&stencilLength=100&stencilCounts=5
>
> Pure copper is 400!
>
> 8 w/m-k is the sort of value you can get from a filled epoxy. I'd
> probably use a plastic via fill, which I understand is cheaper and
> will reduce the thermal resistance of a via by 2:1 or some such.
>
> Maybe we can specify heavier plating in the vias too.
>
> Our usual via is about 75 k/w, top to bottom on a board. 200 of them
> would be 0.375 k/w, which is OK. Half of that would be better.

Solder?

piglet

torsdag den 10. august 2023 kl. 12.55.31 UTC+2 skrev John Larkin:
> On Thu, 10 Aug 2023 01:45:06 -0700 (PDT), Lasse Langwadt Christensen
> <lang...@fonz.dk> wrote:
>
> >torsdag den 10. august 2023 kl. 04.45.14 UTC+2 skrev John Larkin:
> >> Has anyone used filled vias? Epoxy? Copper?
> >>
> >> I need thermal conductivity, as in a D2PAK on one side of a board and
> >> a heat sink on the other.
> >
> >if you don't mind spending the extra ~$300 jlcpcb will do prototypes with copper filled and plated over vias claiming 8W/m.k
> >
> >https://cart.jlcpcb.com/quote?orderType=1&stencilLayer=4&stencilWidth=100&stencilLength=100&stencilCounts=5
> Pure copper is 400!
>
> 8 w/m-k is the sort of value you can get from a filled epoxy. I'd
> probably use a plastic via fill, which I understand is cheaper and
> will reduce the thermal resistance of a via by 2:1 or some such.

you could try it, epoxy filled and plated of over is only ~$23 for 5x 100x100mm pcbs from jlc

On Thu, 10 Aug 2023 12:38:05 +0100, piglet <erichpwagner@hotmail.com>
wrote:

>On 10/08/2023 11:55 am, John Larkin wrote:
>> On Thu, 10 Aug 2023 01:45:06 -0700 (PDT), Lasse Langwadt Christensen
>> <langwadt@fonz.dk> wrote:
>>
>>> torsdag den 10. august 2023 kl. 04.45.14 UTC+2 skrev John Larkin:
>>>> Has anyone used filled vias? Epoxy? Copper?
>>>>
>>>> I need thermal conductivity, as in a D2PAK on one side of a board and
>>>> a heat sink on the other.
>>>
>>> if you don't mind spending the extra ~$300 jlcpcb will do prototypes with copper filled and plated over vias claiming 8W/m.k
>>>
>>> https://cart.jlcpcb.com/quote?orderType=1&stencilLayer=4&stencilWidth=100&stencilLength=100&stencilCounts=5
>>
>> Pure copper is 400!
>>
>> 8 w/m-k is the sort of value you can get from a filled epoxy. I'd
>> probably use a plastic via fill, which I understand is cheaper and
>> will reduce the thermal resistance of a via by 2:1 or some such.
>>
>> Maybe we can specify heavier plating in the vias too.
>>
>> Our usual via is about 75 k/w, top to bottom on a board. 200 of them
>> would be 0.375 k/w, which is OK. Half of that would be better.
>
>Solder?
>
>piglet

The usual concern is that with via-in-pad, the vias will suck the
solder away from the part. That sounds good to me! I'd think that
extra solder paste would leave enough on the pads but slurp some down
into the vias. Solder isn't a great heat conductor but a filled via
can have half the theta of a hollow one.

We want a field of d2pak fets opposite a copper CPU cooler.

torsdag den 10. august 2023 kl. 17.13.21 UTC+2 skrev John Larkin:
> On Thu, 10 Aug 2023 12:38:05 +0100, piglet <erichp...@hotmail.com>
> wrote:
> >On 10/08/2023 11:55 am, John Larkin wrote:
> >> On Thu, 10 Aug 2023 01:45:06 -0700 (PDT), Lasse Langwadt Christensen
> >> <lang...@fonz.dk> wrote:
> >>
> >>> torsdag den 10. august 2023 kl. 04.45.14 UTC+2 skrev John Larkin:
> >>>> Has anyone used filled vias? Epoxy? Copper?
> >>>>
> >>>> I need thermal conductivity, as in a D2PAK on one side of a board and
> >>>> a heat sink on the other.
> >>>
> >>> if you don't mind spending the extra ~$300 jlcpcb will do prototypes with copper filled and plated over vias claiming 8W/m.k
> >>>
> >>> https://cart.jlcpcb.com/quote?orderType=1&stencilLayer=4&stencilWidth=100&stencilLength=100&stencilCounts=5
> >>
> >> Pure copper is 400!
> >>
> >> 8 w/m-k is the sort of value you can get from a filled epoxy. I'd
> >> probably use a plastic via fill, which I understand is cheaper and
> >> will reduce the thermal resistance of a via by 2:1 or some such.
> >>
> >> Maybe we can specify heavier plating in the vias too.
> >>
> >> Our usual via is about 75 k/w, top to bottom on a board. 200 of them
> >> would be 0.375 k/w, which is OK. Half of that would be better.
> >
> >Solder?
> >
> >piglet
> The usual concern is that with via-in-pad, the vias will suck the
> solder away from the part. That sounds good to me! I'd think that
> extra solder paste would leave enough on the pads but slurp some down
> into the vias. Solder isn't a great heat conductor but a filled via
> can have half the theta of a hollow one.

but if the solder pokes out of the via the pcb won't sit flat on the heatsink
> We want a field of d2pak fets opposite a copper CPU cooler.

if you want to get fancy, https://www.pcbway.com/blog/PCB_Basic_Information/Copper_Coin_Embedded_PCB_for_Heat_Dissipation_PCB_Knowledge_00c055cb.html

On Thu, 10 Aug 2023 08:32:01 -0700 (PDT), Lasse Langwadt Christensen
<langwadt@fonz.dk> wrote:

>torsdag den 10. august 2023 kl. 17.13.21 UTC+2 skrev John Larkin:
>> On Thu, 10 Aug 2023 12:38:05 +0100, piglet <erichp...@hotmail.com>
>> wrote:
>> >On 10/08/2023 11:55 am, John Larkin wrote:
>> >> On Thu, 10 Aug 2023 01:45:06 -0700 (PDT), Lasse Langwadt Christensen
>> >> <lang...@fonz.dk> wrote:
>> >>
>> >>> torsdag den 10. august 2023 kl. 04.45.14 UTC+2 skrev John Larkin:
>> >>>> Has anyone used filled vias? Epoxy? Copper?
>> >>>>
>> >>>> I need thermal conductivity, as in a D2PAK on one side of a board and
>> >>>> a heat sink on the other.
>> >>>
>> >>> if you don't mind spending the extra ~$300 jlcpcb will do prototypes with copper filled and plated over vias claiming 8W/m.k
>> >>>
>> >>> https://cart.jlcpcb.com/quote?orderType=1&stencilLayer=4&stencilWidth=100&stencilLength=100&stencilCounts=5
>> >>
>> >> Pure copper is 400!
>> >>
>> >> 8 w/m-k is the sort of value you can get from a filled epoxy. I'd
>> >> probably use a plastic via fill, which I understand is cheaper and
>> >> will reduce the thermal resistance of a via by 2:1 or some such.
>> >>
>> >> Maybe we can specify heavier plating in the vias too.
>> >>
>> >> Our usual via is about 75 k/w, top to bottom on a board. 200 of them
>> >> would be 0.375 k/w, which is OK. Half of that would be better.
>> >
>> >Solder?
>> >
>> >piglet
>> The usual concern is that with via-in-pad, the vias will suck the
>> solder away from the part. That sounds good to me! I'd think that
>> extra solder paste would leave enough on the pads but slurp some down
>> into the vias. Solder isn't a great heat conductor but a filled via
>> can have half the theta of a hollow one.
>
>but if the solder pokes out of the via the pcb won't sit flat on the heatsink

I don't want to do that. We'll have a 3G gap-pad between the cooler
and the PCB to get good thermals and compensate for minor mechanical
issues.

The Dynatron G199 cooler is, well, cool. It's big and flat.

>
>> We want a field of d2pak fets opposite a copper CPU cooler.
>
>if you want to get fancy, https://www.pcbway.com/blog/PCB_Basic_Information/Copper_Coin_Embedded_PCB_for_Heat_Dissipation_PCB_Knowledge_00c055cb.html

On Thu, 10 Aug 2023 08:46:25 -0700, John Larkin
<jlarkin@highlandSNIPMEtechnology.com> wrote:

>On Thu, 10 Aug 2023 08:32:01 -0700 (PDT), Lasse Langwadt Christensen
><langwadt@fonz.dk> wrote:
>
>>torsdag den 10. august 2023 kl. 17.13.21 UTC+2 skrev John Larkin:
>>> On Thu, 10 Aug 2023 12:38:05 +0100, piglet <erichp...@hotmail.com>
>>> wrote:
>>> >On 10/08/2023 11:55 am, John Larkin wrote:
>>> >> On Thu, 10 Aug 2023 01:45:06 -0700 (PDT), Lasse Langwadt Christensen
>>> >> <lang...@fonz.dk> wrote:
>>> >>
>>> >>> torsdag den 10. august 2023 kl. 04.45.14 UTC+2 skrev John Larkin:
>>> >>>> Has anyone used filled vias? Epoxy? Copper?
>>> >>>>
>>> >>>> I need thermal conductivity, as in a D2PAK on one side of a board and
>>> >>>> a heat sink on the other.
>>> >>>
>>> >>> if you don't mind spending the extra ~$300 jlcpcb will do prototypes with copper filled and plated over vias claiming 8W/m.k
>>> >>>
>>> >>> https://cart.jlcpcb.com/quote?orderType=1&stencilLayer=4&stencilWidth=100&stencilLength=100&stencilCounts=5
>>> >>
>>> >> Pure copper is 400!
>>> >>
>>> >> 8 w/m-k is the sort of value you can get from a filled epoxy. I'd
>>> >> probably use a plastic via fill, which I understand is cheaper and
>>> >> will reduce the thermal resistance of a via by 2:1 or some such.
>>> >>
>>> >> Maybe we can specify heavier plating in the vias too.
>>> >>
>>> >> Our usual via is about 75 k/w, top to bottom on a board. 200 of them
>>> >> would be 0.375 k/w, which is OK. Half of that would be better.
>>> >
>>> >Solder?
>>> >
>>> >piglet
>>> The usual concern is that with via-in-pad, the vias will suck the
>>> solder away from the part. That sounds good to me! I'd think that
>>> extra solder paste would leave enough on the pads but slurp some down
>>> into the vias. Solder isn't a great heat conductor but a filled via
>>> can have half the theta of a hollow one.
>>
>>but if the solder pokes out of the via the pcb won't sit flat on the heatsink

My production people say that they can screen a bigger footprint of
solder paste than the part. When it reflows, the extra solder will be
sucked in, to fill the vias without making a bad joint to the part.

That will mostly fill the vias but leaves the hazard of bumps on the
cooler side.

torsdag den 10. august 2023 kl. 22.14.18 UTC+2 skrev John Larkin:
> On Thu, 10 Aug 2023 08:46:25 -0700, John Larkin
> <jla...@highlandSNIPMEtechnology.com> wrote:
>
> >On Thu, 10 Aug 2023 08:32:01 -0700 (PDT), Lasse Langwadt Christensen
> ><lang...@fonz.dk> wrote:
> >
> >>torsdag den 10. august 2023 kl. 17.13.21 UTC+2 skrev John Larkin:
> >>> On Thu, 10 Aug 2023 12:38:05 +0100, piglet <erichp...@hotmail.com>
> >>> wrote:
> >>> >On 10/08/2023 11:55 am, John Larkin wrote:
> >>> >> On Thu, 10 Aug 2023 01:45:06 -0700 (PDT), Lasse Langwadt Christensen
> >>> >> <lang...@fonz.dk> wrote:
> >>> >>
> >>> >>> torsdag den 10. august 2023 kl. 04.45.14 UTC+2 skrev John Larkin:
> >>> >>>> Has anyone used filled vias? Epoxy? Copper?
> >>> >>>>
> >>> >>>> I need thermal conductivity, as in a D2PAK on one side of a board and
> >>> >>>> a heat sink on the other.
> >>> >>>
> >>> >>> if you don't mind spending the extra ~$300 jlcpcb will do prototypes with copper filled and plated over vias claiming 8W/m.k
> >>> >>>
> >>> >>> https://cart.jlcpcb.com/quote?orderType=1&stencilLayer=4&stencilWidth=100&stencilLength=100&stencilCounts=5
> >>> >>
> >>> >> Pure copper is 400!
> >>> >>
> >>> >> 8 w/m-k is the sort of value you can get from a filled epoxy. I'd
> >>> >> probably use a plastic via fill, which I understand is cheaper and
> >>> >> will reduce the thermal resistance of a via by 2:1 or some such.
> >>> >>
> >>> >> Maybe we can specify heavier plating in the vias too.
> >>> >>
> >>> >> Our usual via is about 75 k/w, top to bottom on a board. 200 of them
> >>> >> would be 0.375 k/w, which is OK. Half of that would be better.
> >>> >
> >>> >Solder?
> >>> >
> >>> >piglet
> >>> The usual concern is that with via-in-pad, the vias will suck the
> >>> solder away from the part. That sounds good to me! I'd think that
> >>> extra solder paste would leave enough on the pads but slurp some down
> >>> into the vias. Solder isn't a great heat conductor but a filled via
> >>> can have half the theta of a hollow one.
> >>
> >>but if the solder pokes out of the via the pcb won't sit flat on the heatsink
> My production people say that they can screen a bigger footprint of
> solder paste than the part. When it reflows, the extra solder will be
> sucked in, to fill the vias without making a bad joint to the part.
>
> That will mostly fill the vias but leaves the hazard of bumps on the
> cooler side.

https://designertools.app.protoexpress.com/?appid=TRESVIA&data=ONsTAS5bIR5nFHqIuoQIEqpeYI6FNtC1kNPK9gKk14INuL5nZePBvOxvbHPnk5%20cnHE%20LdwaQf3NPMrsZsHzKD%20%2FM7rjI1AL7TaRuIf%20k%2FaLF5w5yX8NdWEca2p4jr%2Fqd%2F3jiCq2vt109mcdP9itFqb25bcJfU80I08FAEkspybHJoOJbTfc%2FCoK4ZEe1vozrLfjq9Dfs2X42lXYJUnGyJi%20eJFcIvDOZINfUJtZF81UttQPqGh3kPEVQTVWItcA67vr3TNP%20WeEN22%20bXT7AER4Z2z2hsmst3QN4FxVwxvTJQoSn0PzSIu7GDixipPk0cwhm3SBk3Vu9L4HLMaXYQ%3D%3D&q=Thu%20Aug%2010%2016:07:45%20PDT%202023

On Wednesday, August 9, 2023 at 7:45:14 PM UTC-7, John Larkin wrote:
> Has anyone used filled vias? Epoxy? Copper?
>
> I need thermal conductivity, as in a D2PAK on one side of a board and
> a heat sink on the other.

Why not drill a hole, and fill it with an aluminum nitride slug? You know
you want to.
DPAK or TO220 would work better: more area to plop a bigger slug.

Alternate approaches include just wiring to the transistor with stranded copper,
and letting the heatsink go electrically hot.

On Thu, 10 Aug 2023 16:10:31 -0700 (PDT), Lasse Langwadt Christensen
<langwadt@fonz.dk> wrote:

>torsdag den 10. august 2023 kl. 22.14.18 UTC+2 skrev John Larkin:
>> On Thu, 10 Aug 2023 08:46:25 -0700, John Larkin
>> <jla...@highlandSNIPMEtechnology.com> wrote:
>>
>> >On Thu, 10 Aug 2023 08:32:01 -0700 (PDT), Lasse Langwadt Christensen
>> ><lang...@fonz.dk> wrote:
>> >
>> >>torsdag den 10. august 2023 kl. 17.13.21 UTC+2 skrev John Larkin:
>> >>> On Thu, 10 Aug 2023 12:38:05 +0100, piglet <erichp...@hotmail.com>
>> >>> wrote:
>> >>> >On 10/08/2023 11:55 am, John Larkin wrote:
>> >>> >> On Thu, 10 Aug 2023 01:45:06 -0700 (PDT), Lasse Langwadt Christensen
>> >>> >> <lang...@fonz.dk> wrote:
>> >>> >>
>> >>> >>> torsdag den 10. august 2023 kl. 04.45.14 UTC+2 skrev John Larkin:
>> >>> >>>> Has anyone used filled vias? Epoxy? Copper?
>> >>> >>>>
>> >>> >>>> I need thermal conductivity, as in a D2PAK on one side of a board and
>> >>> >>>> a heat sink on the other.
>> >>> >>>
>> >>> >>> if you don't mind spending the extra ~$300 jlcpcb will do prototypes with copper filled and plated over vias claiming 8W/m.k
>> >>> >>>
>> >>> >>> https://cart.jlcpcb.com/quote?orderType=1&stencilLayer=4&stencilWidth=100&stencilLength=100&stencilCounts=5
>> >>> >>
>> >>> >> Pure copper is 400!
>> >>> >>
>> >>> >> 8 w/m-k is the sort of value you can get from a filled epoxy. I'd
>> >>> >> probably use a plastic via fill, which I understand is cheaper and
>> >>> >> will reduce the thermal resistance of a via by 2:1 or some such.
>> >>> >>
>> >>> >> Maybe we can specify heavier plating in the vias too.
>> >>> >>
>> >>> >> Our usual via is about 75 k/w, top to bottom on a board. 200 of them
>> >>> >> would be 0.375 k/w, which is OK. Half of that would be better.
>> >>> >
>> >>> >Solder?
>> >>> >
>> >>> >piglet
>> >>> The usual concern is that with via-in-pad, the vias will suck the
>> >>> solder away from the part. That sounds good to me! I'd think that
>> >>> extra solder paste would leave enough on the pads but slurp some down
>> >>> into the vias. Solder isn't a great heat conductor but a filled via
>> >>> can have half the theta of a hollow one.
>> >>
>> >>but if the solder pokes out of the via the pcb won't sit flat on the heatsink
>> My production people say that they can screen a bigger footprint of
>> solder paste than the part. When it reflows, the extra solder will be
>> sucked in, to fill the vias without making a bad joint to the part.
>>
>> That will mostly fill the vias but leaves the hazard of bumps on the
>> cooler side.
>
>https://designertools.app.protoexpress.com/?appid=TRESVIA&data=ONsTAS5bIR5nFHqIuoQIEqpeYI6FNtC1kNPK9gKk14INuL5nZePBvOxvbHPnk5%20cnHE%20LdwaQf3NPMrsZsHzKD%20%2FM7rjI1AL7TaRuIf%20k%2FaLF5w5yX8NdWEca2p4jr%2Fqd%2F3jiCq2vt109mcdP9itFqb25bcJfU80I08FAEkspybHJoOJbTfc%2FCoK4ZEe1vozrLfjq9Dfs2X42lXYJUnGyJi%20eJFcIvDOZINfUJtZF81UttQPqGh3kPEVQTVWItcA67vr3TNP%20WeEN22%20bXT7AER4Z2z2hsmst3QN4FxVwxvTJQoSn0PzSIu7GDixipPk0cwhm3SBk3Vu9L4HLMaXYQ%3D%3D&q=Thu%20Aug%2010%2016:07:45%20PDT%202023

Fun. If I specify one via, the theta per via is different from the
theta for the array of one via. Theta also depends on which pattern
that one via is arranged in.

This reminds me of some trace impedance calculators that go negative
for wide traces.

On 11/08/2023 9:24 am, whit3rd wrote:
> On Wednesday, August 9, 2023 at 7:45:14 PM UTC-7, John Larkin wrote:
>> Has anyone used filled vias? Epoxy? Copper?
>>
>> I need thermal conductivity, as in a D2PAK on one side of a board and
>> a heat sink on the other.
>
> Why not drill a hole, and fill it with an aluminum nitride slug? You know
> you want to.
> DPAK or TO220 would work better: more area to plop a bigger slug.
>
> Alternate approaches include just wiring to the transistor with stranded copper,
> and letting the heatsink go electrically hot.

Does anyone still make something like this?

https://web.archive.org/web/20160323085333/http://tem-products.com/index.php/thermal-connectors/power-peg.html

On Sat, 12 Aug 2023 00:29:53 +1000, Chris Jones
<lugnut808@spam.yahoo.com> wrote:

>On 11/08/2023 9:24 am, whit3rd wrote:
>> On Wednesday, August 9, 2023 at 7:45:14?PM UTC-7, John Larkin wrote:
>>> Has anyone used filled vias? Epoxy? Copper?
>>>
>>> I need thermal conductivity, as in a D2PAK on one side of a board and
>>> a heat sink on the other.
>>
>> Why not drill a hole, and fill it with an aluminum nitride slug? You know
>> you want to.
>> DPAK or TO220 would work better: more area to plop a bigger slug.
>>
>> Alternate approaches include just wiring to the transistor with stranded copper,
>> and letting the heatsink go electrically hot.
>
>Does anyone still make something like this?
>
>https://web.archive.org/web/20160323085333/http://tem-products.com/index.php/thermal-connectors/power-peg.html
>

That's interesting. A short spacer might do the same function.

On Thursday, 10 August 2023 at 21:14:18 UTC+1, John Larkin wrote:
> On Thu, 10 Aug 2023 08:46:25 -0700, John Larkin
> <jla...@highlandSNIPMEtechnology.com> wrote:
>
> >On Thu, 10 Aug 2023 08:32:01 -0700 (PDT), Lasse Langwadt Christensen
> ><lang...@fonz.dk> wrote:
> >
> >>torsdag den 10. august 2023 kl. 17.13.21 UTC+2 skrev John Larkin:
> >>> On Thu, 10 Aug 2023 12:38:05 +0100, piglet <erichp...@hotmail.com>
> >>> wrote:
> >>> >On 10/08/2023 11:55 am, John Larkin wrote:
> >>> >> On Thu, 10 Aug 2023 01:45:06 -0700 (PDT), Lasse Langwadt Christensen
> >>> >> <lang...@fonz.dk> wrote:
> >>> >>
> >>> >>> torsdag den 10. august 2023 kl. 04.45.14 UTC+2 skrev John Larkin:
> >>> >>>> Has anyone used filled vias? Epoxy? Copper?
> >>> >>>>
> >>> >>>> I need thermal conductivity, as in a D2PAK on one side of a board and
> >>> >>>> a heat sink on the other.
> >>> >>>
> >>> >>> if you don't mind spending the extra ~$300 jlcpcb will do prototypes with copper filled and plated over vias claiming 8W/m.k
> >>> >>>
> >>> >>> https://cart.jlcpcb.com/quote?orderType=1&stencilLayer=4&stencilWidth=100&stencilLength=100&stencilCounts=5
> >>> >>
> >>> >> Pure copper is 400!
> >>> >>
> >>> >> 8 w/m-k is the sort of value you can get from a filled epoxy. I'd
> >>> >> probably use a plastic via fill, which I understand is cheaper and
> >>> >> will reduce the thermal resistance of a via by 2:1 or some such.
> >>> >>
> >>> >> Maybe we can specify heavier plating in the vias too.
> >>> >>
> >>> >> Our usual via is about 75 k/w, top to bottom on a board. 200 of them
> >>> >> would be 0.375 k/w, which is OK. Half of that would be better.
> >>> >
> >>> >Solder?
> >>> >
> >>> >piglet
> >>> The usual concern is that with via-in-pad, the vias will suck the
> >>> solder away from the part. That sounds good to me! I'd think that
> >>> extra solder paste would leave enough on the pads but slurp some down
> >>> into the vias. Solder isn't a great heat conductor but a filled via
> >>> can have half the theta of a hollow one.
> >>
> >>but if the solder pokes out of the via the pcb won't sit flat on the heatsink
> My production people say that they can screen a bigger footprint of
> solder paste than the part. When it reflows, the extra solder will be
> sucked in, to fill the vias without making a bad joint to the part.
>
> That will mostly fill the vias but leaves the hazard of bumps on the
> cooler side.

Lots of small vias seem to work better because there is more surface tension
per unit mass of solder to hold it in place. Also, proportionally more copper than
with few large vias.
John

fredag den 11. august 2023 kl. 17.07.24 UTC+2 skrev John Larkin:
> On Sat, 12 Aug 2023 00:29:53 +1000, Chris Jones
> <lugn...@spam.yahoo.com> wrote:
>
> >On 11/08/2023 9:24 am, whit3rd wrote:
> >> On Wednesday, August 9, 2023 at 7:45:14?PM UTC-7, John Larkin wrote:
> >>> Has anyone used filled vias? Epoxy? Copper?
> >>>
> >>> I need thermal conductivity, as in a D2PAK on one side of a board and
> >>> a heat sink on the other.
> >>
> >> Why not drill a hole, and fill it with an aluminum nitride slug? You know
> >> you want to.
> >> DPAK or TO220 would work better: more area to plop a bigger slug.
> >>
> >> Alternate approaches include just wiring to the transistor with stranded copper,
> >> and letting the heatsink go electrically hot.
> >
> >Does anyone still make something like this?
> >
> >https://web.archive.org/web/20160323085333/http://tem-products.com/index.php/thermal-connectors/power-peg.html
> >
> That's interesting. A short spacer might do the same function.

https://www.ebay.com/itm/195835787106

in a plated hole under the tap, maybe with a piece of PCB on the back to hold them in place during reflow

On Thu, 10 Aug 2023 16:24:51 -0700 (PDT), whit3rd <whit3rd@gmail.com>
wrote:

>On Wednesday, August 9, 2023 at 7:45:14?PM UTC-7, John Larkin wrote:
>> Has anyone used filled vias? Epoxy? Copper?
>>
>> I need thermal conductivity, as in a D2PAK on one side of a board and
>> a heat sink on the other.
>
>Why not drill a hole, and fill it with an aluminum nitride slug? You know
>you want to.
>DPAK or TO220 would work better: more area to plop a bigger slug.
>
>Alternate approaches include just wiring to the transistor with stranded copper,
>and letting the heatsink go electrically hot.

My original idea was to tap holes in the cooler and bolt TO-220s to it
with AlN insulators. That would work, but tapping the cooler copper
and fins would be messy, and the TO220's and insulators would need to
be greased and assembled.

The better idea is to pick-and-place D2PAK fets on the bottom of the
board, and via the heat to a cooler on the top side. If we use gap-pad
between the cooler and the top of the board, which we should, we don't
need insulators.

I want 40 watts per D2PAK fet x 8 fets, mayge 160 watts total max.
About 200 vias per fet. The numbers are challenging but look possible.

This is great:

https://www.dropbox.com/scl/fi/sjay5hyw0zagta3gdsyzl/G199.jpg?rlkey=jykutl4az0h7yntnuxke2mrcc&raw=1

Dynatron G199. We can get them for about $40, a fraction of what a
machined heat sink and fan and stuff would cost. It has a nice flat
surface to sink stuff to.

On Fri, 11 Aug 2023 10:20:32 -0700 (PDT), John Walliker
<jrwalliker@gmail.com> wrote:

>On Thursday, 10 August 2023 at 21:14:18 UTC+1, John Larkin wrote:
>> On Thu, 10 Aug 2023 08:46:25 -0700, John Larkin
>> <jla...@highlandSNIPMEtechnology.com> wrote:
>>
>> >On Thu, 10 Aug 2023 08:32:01 -0700 (PDT), Lasse Langwadt Christensen
>> ><lang...@fonz.dk> wrote:
>> >
>> >>torsdag den 10. august 2023 kl. 17.13.21 UTC+2 skrev John Larkin:
>> >>> On Thu, 10 Aug 2023 12:38:05 +0100, piglet <erichp...@hotmail.com>
>> >>> wrote:
>> >>> >On 10/08/2023 11:55 am, John Larkin wrote:
>> >>> >> On Thu, 10 Aug 2023 01:45:06 -0700 (PDT), Lasse Langwadt Christensen
>> >>> >> <lang...@fonz.dk> wrote:
>> >>> >>
>> >>> >>> torsdag den 10. august 2023 kl. 04.45.14 UTC+2 skrev John Larkin:
>> >>> >>>> Has anyone used filled vias? Epoxy? Copper?
>> >>> >>>>
>> >>> >>>> I need thermal conductivity, as in a D2PAK on one side of a board and
>> >>> >>>> a heat sink on the other.
>> >>> >>>
>> >>> >>> if you don't mind spending the extra ~$300 jlcpcb will do prototypes with copper filled and plated over vias claiming 8W/m.k
>> >>> >>>
>> >>> >>> https://cart.jlcpcb.com/quote?orderType=1&stencilLayer=4&stencilWidth=100&stencilLength=100&stencilCounts=5
>> >>> >>
>> >>> >> Pure copper is 400!
>> >>> >>
>> >>> >> 8 w/m-k is the sort of value you can get from a filled epoxy. I'd
>> >>> >> probably use a plastic via fill, which I understand is cheaper and
>> >>> >> will reduce the thermal resistance of a via by 2:1 or some such.
>> >>> >>
>> >>> >> Maybe we can specify heavier plating in the vias too.
>> >>> >>
>> >>> >> Our usual via is about 75 k/w, top to bottom on a board. 200 of them
>> >>> >> would be 0.375 k/w, which is OK. Half of that would be better.
>> >>> >
>> >>> >Solder?
>> >>> >
>> >>> >piglet
>> >>> The usual concern is that with via-in-pad, the vias will suck the
>> >>> solder away from the part. That sounds good to me! I'd think that
>> >>> extra solder paste would leave enough on the pads but slurp some down
>> >>> into the vias. Solder isn't a great heat conductor but a filled via
>> >>> can have half the theta of a hollow one.
>> >>
>> >>but if the solder pokes out of the via the pcb won't sit flat on the heatsink
>> My production people say that they can screen a bigger footprint of
>> solder paste than the part. When it reflows, the extra solder will be
>> sucked in, to fill the vias without making a bad joint to the part.
>>
>> That will mostly fill the vias but leaves the hazard of bumps on the
>> cooler side.
>
>Lots of small vias seem to work better because there is more surface tension
>per unit mass of solder to hold it in place. Also, proportionally more copper than
>with few large vias.
>John

A couple of sources say that a 0.3 mm diameter via is optimum for
thermal conductivity in a stitched array. I don't know why.

Maybe it's hard to plate thick copper in the walls of a tiny via.

On Fri, 11 Aug 2023 10:25:16 -0700 (PDT), Lasse Langwadt Christensen
<langwadt@fonz.dk> wrote:

>fredag den 11. august 2023 kl. 17.07.24 UTC+2 skrev John Larkin:
>> On Sat, 12 Aug 2023 00:29:53 +1000, Chris Jones
>> <lugn...@spam.yahoo.com> wrote:
>>
>> >On 11/08/2023 9:24 am, whit3rd wrote:
>> >> On Wednesday, August 9, 2023 at 7:45:14?PM UTC-7, John Larkin wrote:
>> >>> Has anyone used filled vias? Epoxy? Copper?
>> >>>
>> >>> I need thermal conductivity, as in a D2PAK on one side of a board and
>> >>> a heat sink on the other.
>> >>
>> >> Why not drill a hole, and fill it with an aluminum nitride slug? You know
>> >> you want to.
>> >> DPAK or TO220 would work better: more area to plop a bigger slug.
>> >>
>> >> Alternate approaches include just wiring to the transistor with stranded copper,
>> >> and letting the heatsink go electrically hot.
>> >
>> >Does anyone still make something like this?
>> >
>> >https://web.archive.org/web/20160323085333/http://tem-products.com/index.php/thermal-connectors/power-peg.html
>> >
>> That's interesting. A short spacer might do the same function.
>
>https://www.ebay.com/itm/195835787106
>
>in a plated hole under the tap, maybe with a piece of PCB on the back to hold them in place during reflow
>

We do want to pick-and-place eight D2PAK fets and one temperature
sensor on the bottom of the board, opposite the cooler, so any of the
slug ideas have complications.

fredag den 11. august 2023 kl. 21.14.00 UTC+2 skrev John Larkin:
> On Fri, 11 Aug 2023 10:20:32 -0700 (PDT), John Walliker
> <jrwal...@gmail.com> wrote:
>
> >On Thursday, 10 August 2023 at 21:14:18 UTC+1, John Larkin wrote:
> >> On Thu, 10 Aug 2023 08:46:25 -0700, John Larkin
> >> <jla...@highlandSNIPMEtechnology.com> wrote:
> >>
> >> >On Thu, 10 Aug 2023 08:32:01 -0700 (PDT), Lasse Langwadt Christensen
> >> ><lang...@fonz.dk> wrote:
> >> >
> >> >>torsdag den 10. august 2023 kl. 17.13.21 UTC+2 skrev John Larkin:
> >> >>> On Thu, 10 Aug 2023 12:38:05 +0100, piglet <erichp...@hotmail.com>
> >> >>> wrote:
> >> >>> >On 10/08/2023 11:55 am, John Larkin wrote:
> >> >>> >> On Thu, 10 Aug 2023 01:45:06 -0700 (PDT), Lasse Langwadt Christensen
> >> >>> >> <lang...@fonz.dk> wrote:
> >> >>> >>
> >> >>> >>> torsdag den 10. august 2023 kl. 04.45.14 UTC+2 skrev John Larkin:
> >> >>> >>>> Has anyone used filled vias? Epoxy? Copper?
> >> >>> >>>>
> >> >>> >>>> I need thermal conductivity, as in a D2PAK on one side of a board and
> >> >>> >>>> a heat sink on the other.
> >> >>> >>>
> >> >>> >>> if you don't mind spending the extra ~$300 jlcpcb will do prototypes with copper filled and plated over vias claiming 8W/m.k
> >> >>> >>>
> >> >>> >>> https://cart.jlcpcb.com/quote?orderType=1&stencilLayer=4&stencilWidth=100&stencilLength=100&stencilCounts=5
> >> >>> >>
> >> >>> >> Pure copper is 400!
> >> >>> >>
> >> >>> >> 8 w/m-k is the sort of value you can get from a filled epoxy. I'd
> >> >>> >> probably use a plastic via fill, which I understand is cheaper and
> >> >>> >> will reduce the thermal resistance of a via by 2:1 or some such.
> >> >>> >>
> >> >>> >> Maybe we can specify heavier plating in the vias too.
> >> >>> >>
> >> >>> >> Our usual via is about 75 k/w, top to bottom on a board. 200 of them
> >> >>> >> would be 0.375 k/w, which is OK. Half of that would be better.
> >> >>> >
> >> >>> >Solder?
> >> >>> >
> >> >>> >piglet
> >> >>> The usual concern is that with via-in-pad, the vias will suck the
> >> >>> solder away from the part. That sounds good to me! I'd think that
> >> >>> extra solder paste would leave enough on the pads but slurp some down
> >> >>> into the vias. Solder isn't a great heat conductor but a filled via
> >> >>> can have half the theta of a hollow one.
> >> >>
> >> >>but if the solder pokes out of the via the pcb won't sit flat on the heatsink
> >> My production people say that they can screen a bigger footprint of
> >> solder paste than the part. When it reflows, the extra solder will be
> >> sucked in, to fill the vias without making a bad joint to the part.
> >>
> >> That will mostly fill the vias but leaves the hazard of bumps on the
> >> cooler side.
> >
> >Lots of small vias seem to work better because there is more surface tension
> >per unit mass of solder to hold it in place. Also, proportionally more copper than
> >with few large vias.
> >John
> A couple of sources say that a 0.3 mm diameter via is optimum for
> thermal conductivity in a stitched array. I don't know why.
>
> Maybe it's hard to plate thick copper in the walls of a tiny via.

afaiu it is because the plating tends to build up faster in the easy to reach areas
so you risk the via opening plating over before the walls, trapping stuff inside

I believe you can get vias plated all the way to solid copper but it takes a long time
so I suspect expensive

On Fri, 11 Aug 2023 12:29:38 -0700 (PDT), Lasse Langwadt Christensen
<langwadt@fonz.dk> wrote:

>fredag den 11. august 2023 kl. 21.14.00 UTC+2 skrev John Larkin:
>> On Fri, 11 Aug 2023 10:20:32 -0700 (PDT), John Walliker
>> <jrwal...@gmail.com> wrote:
>>
>> >On Thursday, 10 August 2023 at 21:14:18 UTC+1, John Larkin wrote:
>> >> On Thu, 10 Aug 2023 08:46:25 -0700, John Larkin
>> >> <jla...@highlandSNIPMEtechnology.com> wrote:
>> >>
>> >> >On Thu, 10 Aug 2023 08:32:01 -0700 (PDT), Lasse Langwadt Christensen
>> >> ><lang...@fonz.dk> wrote:
>> >> >
>> >> >>torsdag den 10. august 2023 kl. 17.13.21 UTC+2 skrev John Larkin:
>> >> >>> On Thu, 10 Aug 2023 12:38:05 +0100, piglet <erichp...@hotmail.com>
>> >> >>> wrote:
>> >> >>> >On 10/08/2023 11:55 am, John Larkin wrote:
>> >> >>> >> On Thu, 10 Aug 2023 01:45:06 -0700 (PDT), Lasse Langwadt Christensen
>> >> >>> >> <lang...@fonz.dk> wrote:
>> >> >>> >>
>> >> >>> >>> torsdag den 10. august 2023 kl. 04.45.14 UTC+2 skrev John Larkin:
>> >> >>> >>>> Has anyone used filled vias? Epoxy? Copper?
>> >> >>> >>>>
>> >> >>> >>>> I need thermal conductivity, as in a D2PAK on one side of a board and
>> >> >>> >>>> a heat sink on the other.
>> >> >>> >>>
>> >> >>> >>> if you don't mind spending the extra ~$300 jlcpcb will do prototypes with copper filled and plated over vias claiming 8W/m.k
>> >> >>> >>>
>> >> >>> >>> https://cart.jlcpcb.com/quote?orderType=1&stencilLayer=4&stencilWidth=100&stencilLength=100&stencilCounts=5
>> >> >>> >>
>> >> >>> >> Pure copper is 400!
>> >> >>> >>
>> >> >>> >> 8 w/m-k is the sort of value you can get from a filled epoxy. I'd
>> >> >>> >> probably use a plastic via fill, which I understand is cheaper and
>> >> >>> >> will reduce the thermal resistance of a via by 2:1 or some such.
>> >> >>> >>
>> >> >>> >> Maybe we can specify heavier plating in the vias too.
>> >> >>> >>
>> >> >>> >> Our usual via is about 75 k/w, top to bottom on a board. 200 of them
>> >> >>> >> would be 0.375 k/w, which is OK. Half of that would be better.
>> >> >>> >
>> >> >>> >Solder?
>> >> >>> >
>> >> >>> >piglet
>> >> >>> The usual concern is that with via-in-pad, the vias will suck the
>> >> >>> solder away from the part. That sounds good to me! I'd think that
>> >> >>> extra solder paste would leave enough on the pads but slurp some down
>> >> >>> into the vias. Solder isn't a great heat conductor but a filled via
>> >> >>> can have half the theta of a hollow one.
>> >> >>
>> >> >>but if the solder pokes out of the via the pcb won't sit flat on the heatsink
>> >> My production people say that they can screen a bigger footprint of
>> >> solder paste than the part. When it reflows, the extra solder will be
>> >> sucked in, to fill the vias without making a bad joint to the part.
>> >>
>> >> That will mostly fill the vias but leaves the hazard of bumps on the
>> >> cooler side.
>> >
>> >Lots of small vias seem to work better because there is more surface tension
>> >per unit mass of solder to hold it in place. Also, proportionally more copper than
>> >with few large vias.
>> >John
>> A couple of sources say that a 0.3 mm diameter via is optimum for
>> thermal conductivity in a stitched array. I don't know why.
>>
>> Maybe it's hard to plate thick copper in the walls of a tiny via.
>
>afaiu it is because the plating tends to build up faster in the easy to reach areas
>so you risk the via opening plating over before the walls, trapping stuff inside
>
>I believe you can get vias plated all the way to solid copper but it takes a long time
>so I suspect expensive

It amazes me that they can plate any copper midway in a tube that is
10 times as long as its diameter.

We do need to find out how thick they can plate the vias at some
reasonable cost.

fredag den 11. august 2023 kl. 21.17.55 UTC+2 skrev John Larkin:
> On Fri, 11 Aug 2023 10:25:16 -0700 (PDT), Lasse Langwadt Christensen
> <lang...@fonz.dk> wrote:
>
> >fredag den 11. august 2023 kl. 17.07.24 UTC+2 skrev John Larkin:
> >> On Sat, 12 Aug 2023 00:29:53 +1000, Chris Jones
> >> <lugn...@spam.yahoo.com> wrote:
> >>
> >> >On 11/08/2023 9:24 am, whit3rd wrote:
> >> >> On Wednesday, August 9, 2023 at 7:45:14?PM UTC-7, John Larkin wrote:
> >> >>> Has anyone used filled vias? Epoxy? Copper?
> >> >>>
> >> >>> I need thermal conductivity, as in a D2PAK on one side of a board and
> >> >>> a heat sink on the other.
> >> >>
> >> >> Why not drill a hole, and fill it with an aluminum nitride slug? You know
> >> >> you want to.
> >> >> DPAK or TO220 would work better: more area to plop a bigger slug.
> >> >>
> >> >> Alternate approaches include just wiring to the transistor with stranded copper,
> >> >> and letting the heatsink go electrically hot.
> >> >
> >> >Does anyone still make something like this?
> >> >
> >> >https://web.archive.org/web/20160323085333/http://tem-products.com/index.php/thermal-connectors/power-peg.html
> >> >
> >> That's interesting. A short spacer might do the same function.
> >
> >https://www.ebay.com/itm/195835787106
> >
> >in a plated hole under the tap, maybe with a piece of PCB on the back to hold them in place during reflow
> >
> We do want to pick-and-place eight D2PAK fets and one temperature
> sensor on the bottom of the board, opposite the cooler, so any of the
> slug ideas have complications.

I imagined the discs being pressed into the pcb before paste/pnp/solder