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tech / sci.electronics.design / Using backside power in chips gives several percent improvement in speed , die size and power consumption

Using backside power in chips gives several percent improvement in speed , die size and power consumption

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From: ali...@comet.invalid (Jan Panteltje)
Newsgroups: sci.electronics.design
Subject: Using backside power in chips gives several percent improvement in speed , die size and power consumption
Date: Sun, 13 Aug 2023 07:18:32 GMT
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by: Jan Panteltje - Sun, 13 Aug 2023 07:18 UTC

Intel Details PowerVia Backside Power Delivery Technology
https://www.tomshardware.com/news/intel-details-powervia-backside-power-delivery-network
A key feature of Intel's 18A and 20A nodes revealed

Samsung Expects Huge Chip Performance Gains From Backside Power Delivery
https://www.tomshardware.com/news/samsung-expects-huge-performance-gains-from-backside-power-delivery
Samsung shares power delivery advantages

Re: Using backside power in chips gives several percent improvement in speed , die size and power consumption

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From: jlar...@highlandSNIPMEtechnology.com (John Larkin)
Newsgroups: sci.electronics.design
Subject: Re: Using backside power in chips gives several percent improvement in speed , die size and power consumption
Date: Sun, 13 Aug 2023 06:46:00 -0700
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by: John Larkin - Sun, 13 Aug 2023 13:46 UTC

On Sun, 13 Aug 2023 07:18:32 GMT, Jan Panteltje <alien@comet.invalid>
wrote:

>Intel Details PowerVia Backside Power Delivery Technology
> https://www.tomshardware.com/news/intel-details-powervia-backside-power-delivery-network
> A key feature of Intel's 18A and 20A nodes revealed
>
>Samsung Expects Huge Chip Performance Gains From Backside Power Delivery
> https://www.tomshardware.com/news/samsung-expects-huge-performance-gains-from-backside-power-delivery
> Samsung shares power delivery advantages
>

That's wonderful, but we've been doing that on multilayer PC boards
for decades.

Re: Using backside power in chips gives several percent improvement in speed , die size and power consumption

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From: ali...@comet.invalid (Jan Panteltje)
Newsgroups: sci.electronics.design
Subject: Re: Using backside power in chips gives several percent improvement in speed , die size and power consumption
Date: Sun, 13 Aug 2023 15:01:09 GMT
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by: Jan Panteltje - Sun, 13 Aug 2023 15:01 UTC

On a sunny day (Sun, 13 Aug 2023 06:46:00 -0700) it happened John Larkin
<jlarkin@highlandSNIPMEtechnology.com> wrote in
<qinhdih9b33el3pn31v4lbsflcnm1rvgao@4ax.com>:

>On Sun, 13 Aug 2023 07:18:32 GMT, Jan Panteltje <alien@comet.invalid>
>wrote:
>
>>Intel Details PowerVia Backside Power Delivery Technology
>> https://www.tomshardware.com/news/intel-details-powervia-backside-power-delivery-network
>> A key feature of Intel's 18A and 20A nodes revealed
>>
>>Samsung Expects Huge Chip Performance Gains From Backside Power Delivery
>> https://www.tomshardware.com/news/samsung-expects-huge-performance-gains-from-backside-power-delivery
>> Samsung shares power delivery advantages
>>
>
>That's wonderful, but we've been doing that on multilayer PC boards
>for decades.

Ys, I had thr same thought,
but then silly-con may be a bit more difficult...

Re: Using backside power in chips gives several percent improvement in speed , die size and power consumption

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by: John Larkin - Sun, 13 Aug 2023 16:03 UTC

On Sun, 13 Aug 2023 15:01:09 GMT, Jan Panteltje <alien@comet.invalid>
wrote:

>On a sunny day (Sun, 13 Aug 2023 06:46:00 -0700) it happened John Larkin
><jlarkin@highlandSNIPMEtechnology.com> wrote in
><qinhdih9b33el3pn31v4lbsflcnm1rvgao@4ax.com>:
>
>>On Sun, 13 Aug 2023 07:18:32 GMT, Jan Panteltje <alien@comet.invalid>
>>wrote:
>>
>>>Intel Details PowerVia Backside Power Delivery Technology
>>> https://www.tomshardware.com/news/intel-details-powervia-backside-power-delivery-network
>>> A key feature of Intel's 18A and 20A nodes revealed
>>>
>>>Samsung Expects Huge Chip Performance Gains From Backside Power Delivery
>>> https://www.tomshardware.com/news/samsung-expects-huge-performance-gains-from-backside-power-delivery
>>> Samsung shares power delivery advantages
>>>
>>
>>That's wonderful, but we've been doing that on multilayer PC boards
>>for decades.
>
>Ys, I had thr same thought,
>but then silly-con may be a bit more difficult...

Another similarity is via resistance, or in our current case here, via
thermal resistance. I guess that via thermal resistance isn't an issue
in ICs.

I don't know if Moore or Feynman considered connection resistance as a
limiting factor on IC scaling.

Re: Using backside power in chips gives several percent improvement in speed , die size and power consumption

<ubc22f$2ict$1@solani.org>

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From: ali...@comet.invalid (Jan Panteltje)
Newsgroups: sci.electronics.design
Subject: Re: Using backside power in chips gives several percent improvement in speed , die size and power consumption
Date: Mon, 14 Aug 2023 02:03:58 GMT
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by: Jan Panteltje - Mon, 14 Aug 2023 02:03 UTC

On a sunny day (Sun, 13 Aug 2023 09:03:48 -0700) it happened John Larkin
<jlarkin@highlandSNIPMEtechnology.com> wrote in
<sfvhdidr5s0u2qs3o36n6uvifhbvspe97t@4ax.com>:

>On Sun, 13 Aug 2023 15:01:09 GMT, Jan Panteltje <alien@comet.invalid>
>wrote:
>
>>On a sunny day (Sun, 13 Aug 2023 06:46:00 -0700) it happened John Larkin
>><jlarkin@highlandSNIPMEtechnology.com> wrote in
>><qinhdih9b33el3pn31v4lbsflcnm1rvgao@4ax.com>:
>>
>>>On Sun, 13 Aug 2023 07:18:32 GMT, Jan Panteltje <alien@comet.invalid>
>>>wrote:
>>>
>>>>Intel Details PowerVia Backside Power Delivery Technology
>>>> https://www.tomshardware.com/news/intel-details-powervia-backside-power-delivery-network
>>>> A key feature of Intel's 18A and 20A nodes revealed
>>>>
>>>>Samsung Expects Huge Chip Performance Gains From Backside Power Delivery
>>>> https://www.tomshardware.com/news/samsung-expects-huge-performance-gains-from-backside-power-delivery
>>>> Samsung shares power delivery advantages
>>>>
>>>
>>>That's wonderful, but we've been doing that on multilayer PC boards
>>>for decades.
>>
>>Ys, I had thr same thought,
>>but then silly-con may be a bit more difficult...
>
>Another similarity is via resistance, or in our current case here, via
>thermal resistance. I guess that via thermal resistance isn't an issue
>in ICs.
>
>I don't know if Moore or Feynman considered connection resistance as a
>limiting factor on IC scaling.

It is very basic thing, as old as the world:
Power:
https://panteltje.nl/pub/z80/graphics_card_bottom.jpg
Signal:
https://panteltje.nl/pub/z80/graphics_card_top.jpg

:-)

Subject	Author
Using backside power in chips gives several percent improvement in speed , die s	Jan Panteltje
Re: Using backside power in chips gives several percent improvement in speed , d	John Larkin
Re: Using backside power in chips gives several percent improvement in speed , d	Jan Panteltje
Re: Using backside power in chips gives several percent improvement in speed , d	John Larkin
Re: Using backside power in chips gives several percent improvement in speed , d	Jan Panteltje