On Wed, 22 Nov 2023 15:10:44 -0500, Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:

>On 2023-11-22 11:08, John Larkin wrote:
>> On Tue, 21 Nov 2023 22:13:57 -0500, Phil Hobbs
>> <pcdhSpamMeSenseless@electrooptical.net> wrote:
>>
>>> On 2023-11-21 17:35, john larkin wrote:
>>>> On Tue, 21 Nov 2023 22:13:32 +0100, Jeroen Belleman
>>>> <jeroen@nospam.please> wrote:
>>>>
>>>>> On 11/21/23 20:03, john larkin wrote:
>>>>>> [...]
>>>>>>
>>>>>> I think I'll TDR some 0603 caps of different values and see how they
>>>>>> look. Conventional wisdom is that all 0603 ceramic caps have about the
>>>>>> same ESL, which I suspect is right. So bypassing with stepped values
>>>>>> makes no sense. What's your opinion?
>>>>>>
>>>>>
>>>>> I remember an amplifier designed by my predecessor where he had
>>>>> religiously bypassed every stage with three parallel capacitors.
>>>>> The two smaller values were SMDs and the larger one was a thru-hole
>>>>> Ta drop. Quite over the top, as I later found. This was in 1988 or
>>>>> so. Probably a left-over from the time when all components had wires,
>>>>> and when this used to be radio-amateur lore. (My predecessor was one.)
>>>>>
>>>>> I was surprised when I measured the ESL of smallish radial-wired
>>>>> aluminium electrolytic capacitors: Only about 5nH, the same as a
>>>>> Ta drop cap with the same wire spacing and indeed what you'd
>>>>> expect from a simple wire jumper of the same geometry. ESR was
>>>>> similar too. I concluded that Ta caps were a waste of money. On
>>>>> the other hand, axial-wired capacitors were much worse, with ESL
>>>>> values over 100nH. I also found that both Al and Ta electrolytics
>>>>> with values below a few uF were pretty much useless, with ESR
>>>>> values above 10 Ohms, not worth the trouble in bypass roles.
>>>>>
>>>>> Jeroen Belleman
>>>>
>>>> I think that using stepped cap values is folklore now, with SMT parts.
>>>
>>> It's been folklore for a good 40 years that I know about.
>>
>> Well, some people haven't got word, even though they are not yet 40
>> years old.
>>
>> What has changed in the last 40 years is that multilayer PCBs are
>> cheap now. The best high-speed bypass cap is a power plane a few mils
>> from a ground plane. Once you have a reasonable amount of plane
>> capacitance, you can splash any sort of caps around the plane and it
>> just mnakes things better. Vias up to parts dominate now.
>
>Yes, assuming that your only decoupling issues are power planes. Those
>of us who are not in that blessed state have to do jazz still. ;)

The new little board is 8 layers. My record is 10... so far.

>
>>> When I was a stripling of about 22, I had this gig making satellite
>>> radio equipment, part of a big push involving nearly the whole RF
>>> department. We were building the first civilian direct broadcast
>>> satellite system, which was cool. I was entirely unqualified when I
>>> started, which is always the best sort of gig for anyone with a bit of
>>> moxie.
>>>
>>> In those hallowed halls of Microtel Pacific Research in Burnaby BC (the
>>> design bureau for the local incarnation of GTE Lenkurt), Enlightened
>>> Opinion strongly favoured bypassing with a 100 nF stacked film cap in
>>> parallel with 1 nF monolithic ceramic. (These were the through-hole
>>> days, you understand.)
>>>
>>> I thought that was a crock, so I put one of those very nice point one
>>> microfarad gizmos on a network analyzer, and measured its impedance. As
>>> I recall, it looked exactly like a perfect capacitor with a snice mall
>>> ESR, until going very slightly inductive (well under an ohm, iirc) out
>>> near 100 MHz. I sent around a memo about this, because all that cargo
>>> cult design was costing money and board space.
>>>
>>> The next day, somebody from another department stopped by my desk with a
>>> copy of the memo. He pointed to that +0.xxx ohm reactance, and said,
>>> "You see? It goes inductive. That means it'll ring." (The Q was, like,
>>> 0.2.)
>>
>> Common sense is always rare.
>>
>> All caps go inductive at high frequency, regardless of the nameplate C
>> value. What varies with value is the series resonance impedance dip,
>> which I usually want to be as low as possible. So use 10 uF bypasses.
>>
>> We're doing a new tiny embedded delay generator, and certain ignorant
>> youth are repeating urban legends about bypassing, passed on from
>> their grandmothers I assume. Power supply ripple makes jitter, so I
>> want big bypass caps. We have nine jitter-critical timing ramps a few
>> inches from five switching supplies.
>Hard to avoid nowadays. BITD we'd just say, "Use a linear supply."
>
>> Incidentally, TPS562208 (costs 22 cents) makes a nice +5 to -8
>> inverting switcher, but TI's sim model is broken so their version of
>> Spice won't model it. I suspect hard-ground internal nodes.
>
>For a regulator,
>
>Nice ~= good, small, cheap, and dumb. ;)

Not super dumb, for a small cheap part. It's a synchronous switcher
with spread-spectrum, soft-start, thermal limiting, and an enable that
can be used for UVLO.

>
>What are the edges like?

Spread-spectrum like crazy.

Here's the rise on TPS564302, basically the same part.

https://www.dropbox.com/s/6prmxq1i2k4gutq/TPS54302_rise.JPG?raw=1

You can see the substrate diode conducting for about 40 ns before the
rise. Cool.

and the ss waveform

https://www.dropbox.com/s/jban5vjybbb2g77/TPS54302_PWM.JPG?raw=1

and the spectrum at the switch node

https://www.dropbox.com/s/etctkh2rzesockj/TPS54302_spectrum.JPG?raw=1

It's fast but clean, no nasty SRD effects. But it gets very warm at 3
amps. 2 looks prudent.

>
>Cheers
>
>Phil Hobbs

On Wed, 22 Nov 2023 11:27:58 -0800 (PST), Fred Bloggs
<bloggs.fredbloggs.fred@gmail.com> wrote:

>On Wednesday, November 22, 2023 at 11:09:12?AM UTC-5, John Larkin wrote:
>> On Tue, 21 Nov 2023 22:13:57 -0500, Phil Hobbs
>> <pcdhSpamM...@electrooptical.net> wrote:
>>
>> >On 2023-11-21 17:35, john larkin wrote:
>> >> On Tue, 21 Nov 2023 22:13:32 +0100, Jeroen Belleman
>> >> <jer...@nospam.please> wrote:
>> >>
>> >>> On 11/21/23 20:03, john larkin wrote:
>> >>>> [...]
>> >>>>
>> >>>> I think I'll TDR some 0603 caps of different values and see how they
>> >>>> look. Conventional wisdom is that all 0603 ceramic caps have about the
>> >>>> same ESL, which I suspect is right. So bypassing with stepped values
>> >>>> makes no sense. What's your opinion?
>> >>>>
>> >>>
>> >>> I remember an amplifier designed by my predecessor where he had
>> >>> religiously bypassed every stage with three parallel capacitors.
>> >>> The two smaller values were SMDs and the larger one was a thru-hole
>> >>> Ta drop. Quite over the top, as I later found. This was in 1988 or
>> >>> so. Probably a left-over from the time when all components had wires,
>> >>> and when this used to be radio-amateur lore. (My predecessor was one.)
>> >>>
>> >>> I was surprised when I measured the ESL of smallish radial-wired
>> >>> aluminium electrolytic capacitors: Only about 5nH, the same as a
>> >>> Ta drop cap with the same wire spacing and indeed what you'd
>> >>> expect from a simple wire jumper of the same geometry. ESR was
>> >>> similar too. I concluded that Ta caps were a waste of money. On
>> >>> the other hand, axial-wired capacitors were much worse, with ESL
>> >>> values over 100nH. I also found that both Al and Ta electrolytics
>> >>> with values below a few uF were pretty much useless, with ESR
>> >>> values above 10 Ohms, not worth the trouble in bypass roles.
>> >>>
>> >>> Jeroen Belleman
>> >>
>> >> I think that using stepped cap values is folklore now, with SMT parts.
>> >
>> >It's been folklore for a good 40 years that I know about.
>> Well, some people haven't got word, even though they are not yet 40
>> years old.
>>
>> What has changed in the last 40 years is that multilayer PCBs are
>> cheap now. The best high-speed bypass cap is a power plane a few mils
>> from a ground plane. Once you have a reasonable amount of plane
>> capacitance, you can splash any sort of caps around the plane and it
>> just mnakes things better. Vias up to parts dominate now.
>> >
>> >When I was a stripling of about 22, I had this gig making satellite
>> >radio equipment, part of a big push involving nearly the whole RF
>> >department. We were building the first civilian direct broadcast
>> >satellite system, which was cool. I was entirely unqualified when I
>> >started, which is always the best sort of gig for anyone with a bit of
>> >moxie.
>> >
>> >In those hallowed halls of Microtel Pacific Research in Burnaby BC (the
>> >design bureau for the local incarnation of GTE Lenkurt), Enlightened
>> >Opinion strongly favoured bypassing with a 100 nF stacked film cap in
>> >parallel with 1 nF monolithic ceramic. (These were the through-hole
>> >days, you understand.)
>> >
>> >I thought that was a crock, so I put one of those very nice point one
>> >microfarad gizmos on a network analyzer, and measured its impedance. As
>> >I recall, it looked exactly like a perfect capacitor with a snice mall
>> >ESR, until going very slightly inductive (well under an ohm, iirc) out
>> >near 100 MHz. I sent around a memo about this, because all that cargo
>> >cult design was costing money and board space.
>> >
>> >The next day, somebody from another department stopped by my desk with a
>> >copy of the memo. He pointed to that +0.xxx ohm reactance, and said,
>> >"You see? It goes inductive. That means it'll ring." (The Q was, like,
>> >0.2.)
>> Common sense is always rare.
>>
>> All caps go inductive at high frequency, regardless of the nameplate C
>> value. What varies with value is the series resonance impedance dip,
>> which I usually want to be as low as possible. So use 10 uF bypasses.
>>
>> We're doing a new tiny embedded delay generator, and certain ignorant
>> youth are repeating urban legends about bypassing, passed on from
>> their grandmothers I assume. Power supply ripple makes jitter, so I
>> want big bypass caps. We have nine jitter-critical timing ramps a few
>> inches from five switching supplies.
>
>Not sure those caps filter power supply ripple all that much. The most significant effect is they allow maximal slew rate of your output triggers and whatnot's, and that is what reduces jitter: slewing pass a threshold in minimal time. jitter, rms is roughly threshold voltage jitter, rms/S.R. That dumb ESL in the bypass puts a fundamental lower limit on S.R.

I have switched supplies +5V and -8V, and quiet supplies/planes +5Q
and -5Q. +5V becomes +5Q through a 47 uH inductor, and we make -5Q
through a linear regulator from -8V. More capacitance on the Q
supplies helps, hence lots of 10uF bypasses.

If a couple of cmos chips change prop delay 1 ns per volt, that's 1 ps
per millivolt. Our basic insertion delay from trig to output is 20 ns,
so a little power supply ripple can make a lot of jitter.

The original concept had the critical timing path pass through an
FPGA, but I vetoed that. FPGAs are slow and noisy.

ECL is the way to go for low jitter; it's not very sensitive to power
supply or temperature, but it's not practical on a small product.

On Wed, 22 Nov 2023 11:21:27 -0800 (PST), Fred Bloggs
<bloggs.fredbloggs.fred@gmail.com> wrote:

>On Wednesday, November 22, 2023 at 2:05:55?PM UTC-5, john larkin wrote:
>> On Sun, 19 Nov 2023 10:41:04 -0800 (PST), Fred Bloggs
>> <bloggs.fred...@gmail.com> wrote:
>>
>> >Actually debuted in 2021.
>> >
>> >While the feature only provides estimates, it is possible to import details about the type of engine your car has in order to obtain more accurate results.
>> >
>> >The tool debuted in 2021, and the company’s 2023 Environmental Report has estimated that it had prevented over 1.3 million tons of pollution up to the end of 2022. The report suggested that’s equivalent to “taking approximately 250,000 fuel-based cars off the road for a year.”
>> >
>> >https://www.thecooldown.com/green-tech/google-maps-fuel-efficient-routes-traffic/
>> Suppose I don't want to penny-pinch, but select the fastest, or the
>> most scenic path, or one that passes a really good restaurant. Does
>> the app include those preferences?
>
>It's google maps, so it tells where everything is, and they allow you to drag the trace of their route through any place you want, so the answer is yes.

Sounds like a lot of overhead. I just get in and drive where I'm
going.

If you listen to some of the compulsive penny-pinchers here, their
time must be worth about $2 per hour.

On Thursday, November 23, 2023 at 10:43:34 AM UTC+11, John Larkin wrote:
> On Wed, 22 Nov 2023 11:27:58 -0800 (PST), Fred Bloggs
> <bloggs.fred...@gmail.com> wrote:
> >On Wednesday, November 22, 2023 at 11:09:12?AM UTC-5, John Larkin wrote:
> >> On Tue, 21 Nov 2023 22:13:57 -0500, Phil Hobbs <pcdhSpamM...@electrooptical.net> wrote:
> >> >On 2023-11-21 17:35, john larkin wrote:
> >> >> On Tue, 21 Nov 2023 22:13:32 +0100, Jeroen Belleman <jer...@nospam..please> wrote:
> >> >>> On 11/21/23 20:03, john larkin wrote:

<snip>

> The original concept had the critical timing path pass through an
> FPGA, but I vetoed that. FPGAs are slow and noisy.

Not all of them.

> ECL is the way to go for low jitter; it's not very sensitive to power supply or temperature, but it's not practical on a small product.

Why not? If you need the low jitter, it's worth adding a -3.3V negative rail to power a couple of ECL parts along the crucial signal path. Back around 1996 I took a TTL based through-hole single Euroboard, replaced most of the TTL parts with surface mount and - and in the space freed up - in put a couple of ECL chips and and an ECL-to-TTL converter to get rid a bunch of power-supply induced sub-nanosecond jitter.

--
Bill Sloman, Sydney

On Wednesday, November 22, 2023 at 4:35:38 AM UTC+11, John Larkin wrote:
> On Sun, 19 Nov 2023 22:34:59 -0800 (PST), Anthony William Sloman <bill.....@ieee.org> wrote:
> >On Monday, November 20, 2023 at 8:46:34?AM UTC+11, John Larkin wrote:
> >> On Sun, 19 Nov 2023 12:55:49 -0800 (PST), Fred Bloggs <bloggs.fred...@gmail.com> wrote:
> >> >On Sunday, November 19, 2023 at 3:33:36?PM UTC-5, John Larkin wrote:
> >> >> On Sun, 19 Nov 2023 10:41:04 -0800 (PST), Fred Bloggs <bloggs.fred....@gmail.com> wrote:
> >> >>
> >> >> >Actually debuted in 2021.
> >> >> >
> >> >> >While the feature only provides estimates, it is possible to import details about the type of engine your car has in order to obtain more accurate results.
> >> >> >
> >> >> >The tool debuted in 2021, and the company’s 2023 Environmental Report has estimated that it had prevented over 1.3 million tons of pollution up to the end of 2022. The report suggested that’s equivalent to “taking approximately 250,000 fuel-based cars off the road for a year.”
> >> >> >
> >> >> >https://www.thecooldown.com/green-tech/google-maps-fuel-efficient-routes-traffic/
> >> >>
> >> >> That's weird, calling CO2 "pollution." CO2 keeps us alive.
> >> >
> >> >The dose makes the poison.
> >>
> >> So too much air, water, light, or tater tots are "pollution."
> >
> >100% pure oxygen let premature babies breathe more easily, but destroyed their eyesight,
> >
> >https://www.nih.gov/news-events/news-releases/higher-oxygen-levels-improve-preterm-survival-increase-risk-eye-condition
> >
> >> We don't have an Académie française, so you can define things the way that terrifies you the most.
> >
> >Nobody is terrified by rising CO2 levels. John Larkin lacks any sense of self-preservation and confuses rational precautions with blind panic - he can't do either.
>
> Consider this:
>
> You could exit your lame insult fest; you are only damaging yourself.

But you are claiming that people are "terrified" when they clearly aren't. Is that polite?

> For a few hundred dollars, you could get a decent oscilloscope, a DVM, a power supply, and some parts kits. Maybe some cheap or free eval boards.
>
> You could, with a bit of imagination, do something interesting, keep your brain active, and post something on-topic. You might even have friendly interactions with people.

I do have friendly interactions with quite a lot of people. Not you - you do seem to have been unfriendly for quite long enough that I'm not going to try.

> You claim expertise in magnetics, and high-speed design, so play with them.

It's not just a claim. And I do play with them in LTSpice from time to time.. If I had even the sniff of a customer I'd do quite a bit more.

--
Bill Sloman, Sydney

On Thursday, November 23, 2023 at 10:43:34 AM UTC+11, John Larkin wrote:
> On Wed, 22 Nov 2023 11:27:58 -0800 (PST), Fred Bloggs <bloggs.fred...@gmail.com> wrote:
> >On Wednesday, November 22, 2023 at 11:09:12?AM UTC-5, John Larkin wrote:
> >> On Tue, 21 Nov 2023 22:13:57 -0500, Phil Hobbs <pcdhSpamM...@electrooptical.net> wrote:
> >> >On 2023-11-21 17:35, john larkin wrote:
> >> >> On Tue, 21 Nov 2023 22:13:32 +0100, Jeroen Belleman <jer...@nospam..please> wrote:
> >> >>> On 11/21/23 20:03, john larkin wrote:

<snip>

> I have switched supplies +5V and -8V, and quiet supplies/planes +5Q and -5Q. +5V becomes +5Q through a 47 uH inductor, and we make -5Q through a linear regulator from -8V. More capacitance on the Q supplies helps, hence lots of 10uF bypasses.

If that's the circuit for which you posted the LTSpice simulation, you hadn't put in a value for the parallel capacitance of the 47uH inductor, and when I did the switching spikes were huge. A 1uH ferrite bead tamed them a lot, and using four 12uH Wirth ferrite beads instead of the 47uH inductor tamed them even more.

> If a couple of cmos chips change prop delay 1 ns per volt, that's 1 ps per millivolt. Our basic insertion delay from trig to output is 20 ns, so a little power supply ripple can make a lot of jitter.

Huge switching spikes make lots of power supply ripple. They also dissipate a lot of heat in the switch.
> The original concept had the critical timing path pass through an FPGA, but I vetoed that. FPGAs are slow and noisy.

Some are.

> ECL is the way to go for low jitter; it's not very sensitive to power supply or temperature, but it's not practical on a small product.

It's entirely practical, but it does take extra effort. Confining it to critical paths does reduce the effort.

--
Bill Sloman, Sydney