https://www.dropbox.com/s/ml84s07yetuvral/Z498_A2.jpg?raw=1

Every once in while we lay out a 4-layer board full of crazy ideas,
and see if any will work.

This will get sawed up into 16 bits, and various people can play with
theirs.

Fast parts are often badly characterized, and layout matters, so you
have to just try things.

Two long vertical cuts will slice this into three slabs, and each of
them can be cut up into individual boards. This requires intensive
topological planning.

One controversial idea: we have a d-flop that has clock-to-output
delay of 200 ps typ, and reset to output of 300 ps. So if you connect
clock and reset together and apply an edge, that should make a 100 ps
output pulse. That might replace my shorted transmission line that got
clumsy to lay out.

--

John Larkin Highland Technology, Inc

The best designs are necessarily accidental.

On Tue, 18 May 2021 21:38:46 -0700, jlarkin@highlandsniptechnology.com
wrote:

>
>
>https://www.dropbox.com/s/ml84s07yetuvral/Z498_A2.jpg?raw=1
>
>Every once in while we lay out a 4-layer board full of crazy ideas,
>and see if any will work.
>
>This will get sawed up into 16 bits, and various people can play with
>theirs.
>
>Fast parts are often badly characterized, and layout matters, so you
>have to just try things.
>
>Two long vertical cuts will slice this into three slabs, and each of
>them can be cut up into individual boards. This requires intensive
>topological planning.
>
>One controversial idea: we have a d-flop that has clock-to-output
>delay of 200 ps typ, and reset to output of 300 ps. So if you connect
>clock and reset together and apply an edge, that should make a 100 ps
>output pulse. That might replace my shorted transmission line that got
>clumsy to lay out.

Interesting idea. I'd expect the results to be highly variable both
on a per-part and per-IC-manufacturing-lot basis. Personally I
wouldn't risk a product development on it, but it could be amusing.

Remove the pork products to reply by email.

On Wed, 19 May 2021 07:39:54 -0400, Steve Goldstein
<sgoldHAM@alum.mit.edu> wrote:

>On Tue, 18 May 2021 21:38:46 -0700, jlarkin@highlandsniptechnology.com
>wrote:
>
>>
>>
>>https://www.dropbox.com/s/ml84s07yetuvral/Z498_A2.jpg?raw=1
>>
>>Every once in while we lay out a 4-layer board full of crazy ideas,
>>and see if any will work.
>>
>>This will get sawed up into 16 bits, and various people can play with
>>theirs.
>>
>>Fast parts are often badly characterized, and layout matters, so you
>>have to just try things.
>>
>>Two long vertical cuts will slice this into three slabs, and each of
>>them can be cut up into individual boards. This requires intensive
>>topological planning.
>>
>>One controversial idea: we have a d-flop that has clock-to-output
>>delay of 200 ps typ, and reset to output of 300 ps. So if you connect
>>clock and reset together and apply an edge, that should make a 100 ps
>>output pulse. That might replace my shorted transmission line that got
>>clumsy to lay out.
>
>Interesting idea. I'd expect the results to be highly variable both
>on a per-part and per-IC-manufacturing-lot basis. Personally I
>wouldn't risk a product development on it, but it could be amusing.

It would have to be fine-tuned of course; my little board has a
trimpot to do that. We'd use a DAC in real life. I said it was
controversial.

>
>Remove the pork products to reply by email.

Your email address is not kosher.

--

John Larkin Highland Technology, Inc

The best designs are necessarily accidental.