I was in the hospital and happened to watch an interview with new CEO of Intel and that got me thinking.

What is the smallest IC being manufactured?

I have heard 4 nm.
If not 4nm, then what is?

I have heard that TMSC and Samsung produce the smallest. True?

Which US company produces the smallest - produces, not buys.

On 5/19/2021 7:57 AM, David Hutchinson wrote:
>
>
>
> I was in the hospital and happened to watch an interview with new CEO of Intel and that got me thinking.
>
> What is the smallest IC being manufactured?
>
> I have heard 4 nm.
> If not 4nm, then what is?
>
> I have heard that TMSC and Samsung produce the smallest. True?
>
> Which US company produces the smallest - produces, not buys.

IBM has recently announced a 2nm geometry.

On Wednesday, May 19, 2021 at 11:16:26 AM UTC-4, Don Y wrote:
> On 5/19/2021 7:57 AM, David Hutchinson wrote:
> >
> >
> >
> > I was in the hospital and happened to watch an interview with new CEO of Intel and that got me thinking.
> >
> > What is the smallest IC being manufactured?
> >
> > I have heard 4 nm.
> > If not 4nm, then what is?
> >
> > I have heard that TMSC and Samsung produce the smallest. True?
> >
> > Which US company produces the smallest - produces, not buys.
> IBM has recently announced a 2nm geometry.

Announcing and producing are two different things.

I believe this feature size has to do with the electrical channel and is not a physical feature. I'm wondering if the processing is truly continuing to advance with ever smaller features in proportion to this reference number? At some point the ever decreasing feature size will have to end since it is not practical to use X-rays in IC manufacturing. But then I'm not an IC designer, so maybe the will continue to come up with new tricks to make features ever smaller.

--

Rick C.

- Get 1,000 miles of free Supercharging
- Tesla referral code - https://ts.la/richard11209

On Wednesday, May 19, 2021 at 7:57:07 AM UTC-7, dave.hu...@gmail.com wrote:
> I was in the hospital and happened to watch an interview with new CEO of Intel and that got me thinking.
>
> What is the smallest IC being manufactured?
>
> I have heard 4 nm.
> If not 4nm, then what is?
>
> I have heard that TMSC and Samsung produce the smallest. True?
>
> Which US company produces the smallest - produces, not buys.

TSMC (soon to be in US AZ) produces the highest volume of 4nm for Intel's (unnamed) competitor.

On 5/19/2021 8:16 AM, Don Y wrote:
> On 5/19/2021 7:57 AM, David Hutchinson wrote:
>>
>>
>>
>> I was in the hospital and happened to watch an interview with new CEO of
>> Intel and that got me thinking.
>>
>> What is the smallest IC being manufactured?
>>
>> I have heard 4 nm.
>> If not 4nm, then what is?
>>
>> I have heard that TMSC and Samsung produce the smallest. True?
>>
>> Which US company produces the smallest - produces, not buys.
>
> IBM has recently announced a 2nm geometry.

<https://www.ibtimes.com/2-nanometer-chip-ibm-says-its-fingernail-sized-microchip-worlds-smallest-most-3194842>

"IBM has announced that it has created the world's first 2-nanometer chip.
The tech giant claims the microchip, which is about the size of a fingernail,
is the smallest and most powerful chip yet developed."

I can't recall where I heard that they will likely be *licensing* the
technology (though using it for certain of their products) as the
primary consequence of this announcement.

<https://www.wraltechwire.com/2021/05/06/big-blues-chip-breakthrough-ibm-unveils-smaller-more-powerful-semiconductor/>

Would be nice to have such a wafer (functional or not) to use as a clock face!

On Wednesday, May 19, 2021 at 11:41:51 AM UTC-4, Don Y wrote:
> On 5/19/2021 8:16 AM, Don Y wrote:
> > On 5/19/2021 7:57 AM, David Hutchinson wrote:
> >>
> >>
> >>
> >> I was in the hospital and happened to watch an interview with new CEO of
> >> Intel and that got me thinking.
> >>
> >> What is the smallest IC being manufactured?
> >>
> >> I have heard 4 nm.
> >> If not 4nm, then what is?
> >>
> >> I have heard that TMSC and Samsung produce the smallest. True?
> >>
> >> Which US company produces the smallest - produces, not buys.
> >
> > IBM has recently announced a 2nm geometry.
> <https://www.ibtimes.com/2-nanometer-chip-ibm-says-its-fingernail-sized-microchip-worlds-smallest-most-3194842>
>
> "IBM has announced that it has created the world's first 2-nanometer chip..
> The tech giant claims the microchip, which is about the size of a fingernail,
> is the smallest and most powerful chip yet developed."
>
> I can't recall where I heard that they will likely be *licensing* the
> technology (though using it for certain of their products) as the
> primary consequence of this announcement.
>
> <https://www.wraltechwire.com/2021/05/06/big-blues-chip-breakthrough-ibm-unveils-smaller-more-powerful-semiconductor/>
>
> Would be nice to have such a wafer (functional or not) to use as a clock face!

Something is rotten in Denmark (no offense to Denmark, I'm just quoting some English guy).

"The world’s first 2 nanometer (nm), much smaller in scale that existing 5 nm and 7 nm yet packing more processing power 45% more than 7 nm chips while using 75% less energy, says IBM."

How does a 3.5x reduction in feature size only provide a 45% gain in "processing power"?

I'm also not finding any indication of when this will be in products. Maybe because it's not very manufacturable? “2 nm technology [uses] transmission electron microscopy."

--

Rick C.

- Get 1,000 miles of free Supercharging
- Tesla referral code - https://ts.la/richard11209

> I believe this feature size has to do with the electrical channel and is not a physical feature.

As far as I know, you are completely right. The "2nm" or "1nm" is
related to the geometrical feature that would have an "equivalent"
conventional device producing the expected extrapolated performances
(speed, power consumption, leakage or whatever...). Just for comparison,
bear in mind that the silicon lattice constant is about 0.5nm, so the
1nm channel is barely two silicon atomic layers. A device really sized
at this scale should require a true technology breakthrough, where
quantum or mesoscopic effects are not negligible.

The progress in manufacturing is mostly due to unconventional new
structures (e.g. 3D fin fets) or brand new material or exhoteric
semiconductor compounds. Indeed, a field of applied research that I am
far for claiming trivial.

--

maitre Aliboron

maitre Aliboron wrote:
>> I believe this feature size has to do with the electrical channel and
>> is not a physical feature.
>
> As far as I know, you are completely right. The "2nm" or "1nm" is
> related to the geometrical feature that would have an "equivalent"
> conventional device producing the expected extrapolated performances
> (speed, power consumption, leakage or whatever...). Just for comparison,
> bear in mind that the silicon lattice constant is about 0.5nm, so the
> 1nm channel is barely two silicon atomic layers. A device really sized
> at this scale should require a true technology breakthrough, where
> quantum or mesoscopic effects are not negligible.
>
> The progress in manufacturing is mostly due to unconventional new
> structures (e.g. 3D fin fets) or brand new material or exhoteric
> semiconductor compounds. Indeed, a field of applied research that I am
> far for claiming trivial.
>

Classically the nodes were named by the minimum FET gate length. (You
resize the device by changing the gate width, which is almost always
much larger than the length.)

FinFETs started coming in at 32 nm iirc, in response to the creeping
failure of Mead-Conway VLSI scaling. With VDD limited by gate length
(a proxy for the width of the channel) and gate oxide thickness limited
by leakage due to tunnelling, the only way to get enough E field to turn
the FET on completely was to wrap the gate around three sides of the
channel.

Since then processing has got hugely more complicated--instead of just
silicon, oxygen, nitrogen, boron, phosphorus, aluminum, and copper,
chips now contain most of the stable elements.

Ten years ago one of the major problems was huge variations in threshold
voltage due to dopant atom statistics--it makes a lot of difference
whether you have 90 or 100 dopant atoms in the channel, for instance.
AIUI they solved that by atomic-layer deposition followed by local
diffusion. Not your grandpa's quartz furnace anymore!

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510

http://electrooptical.net
http://hobbs-eo.com

Phil Hobbs <pcdhSpamMeSenseless@electrooptical.net> wrote in
news:368ca83b-bd01-44a4-3b07-07b257b62e59@electrooptical.net:

> maitre Aliboron wrote:
>>> I believe this feature size has to do with the electrical
>>> channel and is not a physical feature.
>>
>> As far as I know, you are completely right. The "2nm" or "1nm" is
>> related to the geometrical feature that would have an
>> "equivalent" conventional device producing the expected
>> extrapolated performances (speed, power consumption, leakage or
>> whatever...). Just for comparison, bear in mind that the silicon
>> lattice constant is about 0.5nm, so the 1nm channel is barely two
>> silicon atomic layers. A device really sized at this scale should
>> require a true technology breakthrough, where quantum or
>> mesoscopic effects are not negligible.
>>
>> The progress in manufacturing is mostly due to unconventional new
>> structures (e.g. 3D fin fets) or brand new material or exhoteric
>> semiconductor compounds. Indeed, a field of applied research that
>> I am far for claiming trivial.
>>
>
> Classically the nodes were named by the minimum FET gate length.
> (You resize the device by changing the gate width, which is almost
> always much larger than the length.)
>
> FinFETs started coming in at 32 nm iirc, in response to the
> creeping failure of Mead-Conway VLSI scaling. With VDD limited
> by gate length (a proxy for the width of the channel) and gate
> oxide thickness limited by leakage due to tunnelling, the only way
> to get enough E field to turn the FET on completely was to wrap
> the gate around three sides of the channel.
>
> Since then processing has got hugely more complicated--instead of
> just silicon, oxygen, nitrogen, boron, phosphorus, aluminum, and
> copper, chips now contain most of the stable elements.
>
> Ten years ago one of the major problems was huge variations in
> threshold voltage due to dopant atom statistics--it makes a lot of
> difference whether you have 90 or 100 dopant atoms in the channel,
> for instance. AIUI they solved that by atomic-layer deposition
> followed by local diffusion. Not your grandpa's quartz furnace
> anymore!
>
> Cheers
>
> Phil Hobbs
>

Burn baby, burn.

Whereas the silicon spike grown to produce the new kilogram standard
was as pure and properly structured as it has ever gotten.

Moley, moley, moley.

Phil Hobbs <pcdhSpamMeSenseless@electrooptical.net> wrote:

> maitre Aliboron wrote:
>>> I believe this feature size has to do with the electrical channel and
>>> is not a physical feature.
>>
>> As far as I know, you are completely right. The "2nm" or "1nm" is
>> related to the geometrical feature that would have an "equivalent"
>> conventional device producing the expected extrapolated performances
>> (speed, power consumption, leakage or whatever...). Just for
>> comparison, bear in mind that the silicon lattice constant is about
>> 0.5nm, so the 1nm channel is barely two silicon atomic layers. A device
>> really sized at this scale should require a true technology
>> breakthrough, where quantum or mesoscopic effects are not negligible.
>>
>> The progress in manufacturing is mostly due to unconventional new
>> structures (e.g. 3D fin fets) or brand new material or exhoteric
>> semiconductor compounds. Indeed, a field of applied research that I am
>> far for claiming trivial.
>>
>
> Classically the nodes were named by the minimum FET gate length. (You
> resize the device by changing the gate width, which is almost always
> much larger than the length.)
>
> FinFETs started coming in at 32 nm iirc, in response to the creeping
> failure of Mead-Conway VLSI scaling. With VDD limited by gate length
> (a proxy for the width of the channel) and gate oxide thickness limited
> by leakage due to tunnelling, the only way to get enough E field to turn
> the FET on completely was to wrap the gate around three sides of the
> channel.
>
> Since then processing has got hugely more complicated--instead of just
> silicon, oxygen, nitrogen, boron, phosphorus, aluminum, and copper,
> chips now contain most of the stable elements.
>
> Ten years ago one of the major problems was huge variations in threshold
> voltage due to dopant atom statistics--it makes a lot of difference
> whether you have 90 or 100 dopant atoms in the channel, for instance.
> AIUI they solved that by atomic-layer deposition followed by local
> diffusion. Not your grandpa's quartz furnace anymore!
>
> Cheers
>
> Phil Hobbs

Here's some videos on EUV machines by ASML:

1. The Extreme Physics Pushing Moore�s Law to the Next Level
https://www.youtube.com/watch?v=f0gMdGrVteI

2. ASML: TSMC's Critical Supplier, Explained
https://www.youtube.com/watch?v=CFsn1CUyXWs

3. How ASML Builds a $150 Million EUV Machine
https://www.youtube.com/watch?v=jJIO7aRXUCg

--
The best designs occur in the theta state. - sw

Steve Wilson wrote:
> Phil Hobbs <pcdhSpamMeSenseless@electrooptical.net> wrote:
>
>> maitre Aliboron wrote:
>>>> I believe this feature size has to do with the electrical channel and
>>>> is not a physical feature.
>>>
>>> As far as I know, you are completely right. The "2nm" or "1nm" is
>>> related to the geometrical feature that would have an "equivalent"
>>> conventional device producing the expected extrapolated performances
>>> (speed, power consumption, leakage or whatever...). Just for
>>> comparison, bear in mind that the silicon lattice constant is about
>>> 0.5nm, so the 1nm channel is barely two silicon atomic layers. A device
>>> really sized at this scale should require a true technology
>>> breakthrough, where quantum or mesoscopic effects are not negligible.
>>>
>>> The progress in manufacturing is mostly due to unconventional new
>>> structures (e.g. 3D fin fets) or brand new material or exhoteric
>>> semiconductor compounds. Indeed, a field of applied research that I am
>>> far for claiming trivial.
>>>
>>
>> Classically the nodes were named by the minimum FET gate length. (You
>> resize the device by changing the gate width, which is almost always
>> much larger than the length.)
>>
>> FinFETs started coming in at 32 nm iirc, in response to the creeping
>> failure of Mead-Conway VLSI scaling. With VDD limited by gate length
>> (a proxy for the width of the channel) and gate oxide thickness limited
>> by leakage due to tunnelling, the only way to get enough E field to turn
>> the FET on completely was to wrap the gate around three sides of the
>> channel.
>>
>> Since then processing has got hugely more complicated--instead of just
>> silicon, oxygen, nitrogen, boron, phosphorus, aluminum, and copper,
>> chips now contain most of the stable elements.
>>
>> Ten years ago one of the major problems was huge variations in threshold
>> voltage due to dopant atom statistics--it makes a lot of difference
>> whether you have 90 or 100 dopant atoms in the channel, for instance.
>> AIUI they solved that by atomic-layer deposition followed by local
>> diffusion. Not your grandpa's quartz furnace anymore!
>>
>> Cheers
>>
>> Phil Hobbs
>
> Here's some videos on EUV machines by ASML:
>
> 1. The Extreme Physics Pushing Moore’s Law to the Next Level
> https://www.youtube.com/watch?v=f0gMdGrVteI
>
> 2. ASML: TSMC's Critical Supplier, Explained
> https://www.youtube.com/watch?v=CFsn1CUyXWs
>
> 3. How ASML Builds a $150 Million EUV Machine
> https://www.youtube.com/watch?v=jJIO7aRXUCg

Yeah, I did some work for them on that gizmo (not as much as JL though).
The CO2 laser is impressive in person.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510

http://electrooptical.net
http://hobbs-eo.com

Phil Hobbs <pcdhSpamMeSenseless@electrooptical.net> wrote:

> Steve Wilson wrote:

[...]
>> Here's some videos on EUV machines by ASML:
>>
>> 1. The Extreme Physics Pushing Moore’s Law to the Next Level
>> https://www.youtube.com/watch?v=f0gMdGrVteI
>>
>> 2. ASML: TSMC's Critical Supplier, Explained
>> https://www.youtube.com/watch?v=CFsn1CUyXWs
>>
>> 3. How ASML Builds a $150 Million EUV Machine
>> https://www.youtube.com/watch?v=jJIO7aRXUCg
>
> Yeah, I did some work for them on that gizmo (not as much as JL though).
> The CO2 laser is impressive in person.
> Cheers
> Phil Hobbs
IBM has announced a 2nm process, and a new fet design:

IBM's 2nm transistors could supercharge your phone (in a few years)
https://www.youtube.com/watch?v=OTZcxPCrppo

--
The best designs occur in the theta state. - sw

Steve Wilson wrote:
> Phil Hobbs <pcdhSpamMeSenseless@electrooptical.net> wrote:
>
>> Steve Wilson wrote:
>
> [...]
>>> Here's some videos on EUV machines by ASML:
>>>
>>> 1. The Extreme Physics Pushing Moore’s Law to the Next Level
>>> https://www.youtube.com/watch?v=f0gMdGrVteI
>>>
>>> 2. ASML: TSMC's Critical Supplier, Explained
>>> https://www.youtube.com/watch?v=CFsn1CUyXWs
>>>
>>> 3. How ASML Builds a $150 Million EUV Machine
>>> https://www.youtube.com/watch?v=jJIO7aRXUCg
>>
>> Yeah, I did some work for them on that gizmo (not as much as JL though).
>> The CO2 laser is impressive in person.
>
>> Cheers
>
>> Phil Hobbs
>
> IBM has announced a 2nm process, and a new fet design:
>
> IBM's 2nm transistors could supercharge your phone (in a few years)
> https://www.youtube.com/watch?v=OTZcxPCrppo

IBM has produced a larger proportion of all silicon processing
technology than any other organization. I haven't been there for a
dozen years now, but I'm glad to see that that part of the IBM legacy
continues.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510

http://electrooptical.net
http://hobbs-eo.com

On Sun, 30 May 2021 13:23:17 -0400, Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:

>Steve Wilson wrote:
>> Phil Hobbs <pcdhSpamMeSenseless@electrooptical.net> wrote:
>>
>>> maitre Aliboron wrote:
>>>>> I believe this feature size has to do with the electrical channel and
>>>>> is not a physical feature.
>>>>
>>>> As far as I know, you are completely right. The "2nm" or "1nm" is
>>>> related to the geometrical feature that would have an "equivalent"
>>>> conventional device producing the expected extrapolated performances
>>>> (speed, power consumption, leakage or whatever...). Just for
>>>> comparison, bear in mind that the silicon lattice constant is about
>>>> 0.5nm, so the 1nm channel is barely two silicon atomic layers. A device
>>>> really sized at this scale should require a true technology
>>>> breakthrough, where quantum or mesoscopic effects are not negligible.
>>>>
>>>> The progress in manufacturing is mostly due to unconventional new
>>>> structures (e.g. 3D fin fets) or brand new material or exhoteric
>>>> semiconductor compounds. Indeed, a field of applied research that I am
>>>> far for claiming trivial.
>>>>
>>>
>>> Classically the nodes were named by the minimum FET gate length. (You
>>> resize the device by changing the gate width, which is almost always
>>> much larger than the length.)
>>>
>>> FinFETs started coming in at 32 nm iirc, in response to the creeping
>>> failure of Mead-Conway VLSI scaling. With VDD limited by gate length
>>> (a proxy for the width of the channel) and gate oxide thickness limited
>>> by leakage due to tunnelling, the only way to get enough E field to turn
>>> the FET on completely was to wrap the gate around three sides of the
>>> channel.
>>>
>>> Since then processing has got hugely more complicated--instead of just
>>> silicon, oxygen, nitrogen, boron, phosphorus, aluminum, and copper,
>>> chips now contain most of the stable elements.
>>>
>>> Ten years ago one of the major problems was huge variations in threshold
>>> voltage due to dopant atom statistics--it makes a lot of difference
>>> whether you have 90 or 100 dopant atoms in the channel, for instance.
>>> AIUI they solved that by atomic-layer deposition followed by local
>>> diffusion. Not your grandpa's quartz furnace anymore!
>>>
>>> Cheers
>>>
>>> Phil Hobbs
>>
>> Here's some videos on EUV machines by ASML:
>>
>> 1. The Extreme Physics Pushing Moore’s Law to the Next Level
>> https://www.youtube.com/watch?v=f0gMdGrVteI
>>
>> 2. ASML: TSMC's Critical Supplier, Explained
>> https://www.youtube.com/watch?v=CFsn1CUyXWs
>>
>> 3. How ASML Builds a $150 Million EUV Machine
>> https://www.youtube.com/watch?v=jJIO7aRXUCg
>
>Yeah, I did some work for them on that gizmo (not as much as JL though).
> The CO2 laser is impressive in person.
>
>Cheers
>
>Phil Hobbs

There is a next-generation machine, somewhat more expensive.

--

John Larkin Highland Technology, Inc

The best designs are necessarily accidental.

On 19/05/2021 16.57, David Hutchinson wrote:
>
>
>
> I was in the hospital and happened to watch an interview with new CEO of Intel and that got me thinking.
>
> What is the smallest IC being manufactured?
>
> I have heard 4 nm.
> If not 4nm, then what is?
>
> I have heard that TMSC and Samsung produce the smallest. True?
>
> Which US company produces the smallest - produces, not buys.
>
>
I am more interested in the technology I can actually use for custom ASIC

Recently, the Efabless Google program allows for custom first try ASICs
with no cost at all. Both free shuttle runs and free SW development tools

https://efabless.com/open_shuttle_program/2

Magic dev tools:

https://info.efabless.com/knowledgebase/magic-tutorial-01-highlight-of-magic-features/

ASIC is no longer for big dollar firms ;-)

Cheers

Klaus

On 5/30/2021 3:48 PM, Klaus Vestergaard Kragelund wrote:
> I am more interested in the technology I can actually use for custom ASIC
>
> Recently, the Efabless Google program allows for custom first try ASICs with no
> cost at all. Both free shuttle runs and free SW development tools
> https://efabless.com/open_shuttle_program/2
> Magic dev tools:
> https://info.efabless.com/knowledgebase/magic-tutorial-01-highlight-of-magic-features/
> ASIC is no longer for big dollar firms ;-)

As I understand it, they effectively pay for the *second* turn of the crank
(unless, of course, you only need qty one?) as you still have to find a
real fab to make your parts...

(the free offer just increases the likelihood that the selected fab will
be able to make "good" parts)

On 06/06/2021 07:58, Don Y wrote:
> On 5/30/2021 3:48 PM, Klaus Vestergaard Kragelund wrote:
>> I am more interested in the technology I can actually use for custom ASIC
>>
>> Recently, the Efabless Google program allows for custom first try
>> ASICs with no cost at all. Both free shuttle runs and free SW
>> development tools
>>    https://efabless.com/open_shuttle_program/2
>> Magic dev tools:
>>
>> https://info.efabless.com/knowledgebase/magic-tutorial-01-highlight-of-magic-features/
>> ASIC is no longer for big dollar firms ;-)
>
> As I understand it, they effectively pay for the *second* turn of the crank
> (unless, of course, you only need qty one?)

https://efabless.com/open_mpw_faq

You get 50 parts.

Probably you could get more parts if you pay for some extra wafers to be
run with the same MPW masks, and processing a few wafers is cheap
compared to a maskset.

On 6/6/2021 5:35 AM, Chris Jones wrote:
> On 06/06/2021 07:58, Don Y wrote:
>> On 5/30/2021 3:48 PM, Klaus Vestergaard Kragelund wrote:
>>> I am more interested in the technology I can actually use for custom ASIC
>>>
>>> Recently, the Efabless Google program allows for custom first try ASICs with
>>> no cost at all. Both free shuttle runs and free SW development tools
>>> https://efabless.com/open_shuttle_program/2
>>> Magic dev tools:
>>> https://info.efabless.com/knowledgebase/magic-tutorial-01-highlight-of-magic-features/
>>> ASIC is no longer for big dollar firms ;-)
>>
>> As I understand it, they effectively pay for the *second* turn of the crank
>> (unless, of course, you only need qty one?)
>
> https://efabless.com/open_mpw_faq
>
> You get 50 parts.

50 = 1. How often do you only build 50 of something? If it's an open source
project, how often is the "world market" JUST 50 pieces?

> Probably you could get more parts if you pay for some extra wafers to be run
> with the same MPW masks, and processing a few wafers is cheap compared to a
> maskset.

You're assuming they want to become a production fab. "I want 10,000 pieces
at the same 'low, low' price!"