On Mon, 4 Apr 2022 00:07:07 +0300, Dimiter_Popoff <dp@tgi-sci.com>
wrote:

>On 4/3/2022 23:12, Joe Gwinn wrote:
>> On Sun, 3 Apr 2022 01:06:24 +0300, Dimiter_Popoff <dp@tgi-sci.com>
>> wrote:
>>
>>> On 4/2/2022 23:50, Joe Gwinn wrote:
>>>> On Sat, 2 Apr 2022 22:15:00 +0300, Dimiter_Popoff <dp@tgi-sci.com>
>>>> wrote:
>>>>
>>>>> On 4/2/2022 21:51, Joe Gwinn wrote:
>>>>>> On Sat, 2 Apr 2022 21:38:30 +0300, Dimiter_Popoff <dp@tgi-sci.com>
>>>>>> wrote:
>>>>>>
>>>>>>> On 4/2/2022 20:47, John Larkin wrote:
>>>>>>>> On Sat, 2 Apr 2022 20:33:11 +0300, Dimiter_Popoff <dp@tgi-sci.com>
>>>>>>>> wrote:
>>>>>>>>
>>>>>>>>> On 4/2/2022 19:52, John Larkin wrote:
>>>>>>>>>> On Sat, 2 Apr 2022 18:54:50 +0300, Dimiter_Popoff <dp@tgi-sci.com>
>>>>>>>>>> wrote:
>>>>>>>>>>
>>>>>>>>>>> On 4/2/2022 1:37, John Larkin wrote:
>>>>>>>>>>>> On 1 Apr 2022 22:28:41 GMT, Uwe Bonnes
>>>>>>>>>>>> <bon@hertz.ikp.physik.tu-darmstadt.de> wrote:
>>>>>>>>>>>>
>>>>>>>>>>>>> John Larkin <jlarkin@highland_atwork_technology.com> wrote:
>>>>>>>>>>>>>> We're designing a biggish dual power supply, and the customer wants
>>>>>>>>>>>>>> remote sense. We'd add a small D9 connector or something for the four
>>>>>>>>>>>>>> sense inputs.
>>>>>>>>>>>>>>
>>>>>>>>>>>>>> This seems non-trivial. The supply should work normally if the rs pins
>>>>>>>>>>>>>> are not connected. We could put 50 ohm or somesuch resistors from the
>>>>>>>>>>>>>> main outputs to the rs pins, and then drive a high-z feedback circuit.
>>>>>>>>>>>>>>
>>>>>>>>>>>>>> If the two supplies are paralleled, the customer would use just two
>>>>>>>>>>>>>> sense wires.
>>>>>>>>>>>>>>
>>>>>>>>>>>>>> If rs is connected wrong, the supply can go bonkers or we could fry
>>>>>>>>>>>>>> the 50 ohm resistors.
>>>>>>>>>>>>>>
>>>>>>>>>>>>>> Sounds like we need current limiters and maybe diodes and maybe FPGA
>>>>>>>>>>>>>> logic.
>>>>>>>>>>>>>>
>>>>>>>>>>>>>
>>>>>>>>>>>>> Why FPGA? Why not some uC?
>>>>>>>>>>>>
>>>>>>>>>>>> Every plugin board in this box has an FPGA. We need to do a lot of
>>>>>>>>>>>> signal processing. The isolated ADCs are ADUM7703 delta-sigmas with a
>>>>>>>>>>>> 20 MHz bit rate, which need a heap of decimation processing. We'll do
>>>>>>>>>>>> some 100 Mbit communications with the motherboard too.
>>>>>>>>>>>>
>>>>>>>>>>>> The little Trion FPGAs are about $10. We could even run a riscV
>>>>>>>>>>>> processor inside.
>>>>>>>>>>>>
>>>>>>>>>>>
>>>>>>>>>>> Thanks for mentioning these Trion FPGA-s, they look very interesting
>>>>>>>>>>> to me.
>>>>>>>>>>> Do you have any impression on their software licensing? I saw they
>>>>>>>>>>> sell it at $35 but does it turn into yet another subscription
>>>>>>>>>>> after some time?
>>>>>>>>>>
>>>>>>>>>> I'll ask my FPGA guy. I get the impression that it's not bad.
>>>>>>>>>>
>>>>>>>>>> They look cool. They are simple, with no ADC or high-end serdes or
>>>>>>>>>> things like that. They do have a dram controller (I think), lvds i/o,
>>>>>>>>>> schmitts, and a soft core riscV. 1Mbit of sram.
>>>>>>>>>>
>>>>>>>>>> We're about to make a test board that includes the T20F256C4. We plan
>>>>>>>>>> to measure a lot of stuff: pin-pin delays, Fmax on counters, LVDS
>>>>>>>>>> common-mode levels, delay-vs-Vcore and temperature, jitter, drive
>>>>>>>>>> strengths, things like that.
>>>>>>>>>>
>>>>>>>>>> We asked their support people about some details of using the LVDS
>>>>>>>>>> receivers at other levels, and they said "don't do that."
>>>>>>>>>>
>>>>>>>>>> I might make an ADC using an LVDS receiver as a comparator. The
>>>>>>>>>> minimal ADC would use three fpga pins and one external RC. That could
>>>>>>>>>> be v-to-f, pwm, delta-sigma, or single-slope. Fun.
>>>>>>>>>>
>>>>>>>>>> We've designed a flash manager with bootstrap and field upgrade and
>>>>>>>>>> such.
>>>>>>>>>>
>>>>>>>>>
>>>>>>>>> I am only after standard functions, and if their lvds will do for
>>>>>>>>> hdmi video out I'll be happy.
>>>>>>>>> What I feel nervous about are their design tools, looks like they
>>>>>>>>> are just $35 for now but how quickly can they become prohibitive
>>>>>>>>> for someone who does not sell millions of units.
>>>>>>>>
>>>>>>>> I never understood why FPGA vendors should charge for tools or use
>>>>>>>> insane licensing stuff. Makes more sense to just give it away, maybe
>>>>>>>> charge for support.
>>>>>>>>
>>>>>>>
>>>>>>> For many years - >20 - the electronica industry has been closing things
>>>>>>> down so only "politburo members" can do real development. Probably this
>>>>>>> is part of the same effort, FPGA vendors are interested in selling more
>>>>>>> chips but their large customers likely give them contracts against
>>>>>>> guarantees the tools will not be available to everybody.
>>>>>>
>>>>>> I'd bet it's an attempt to lock their customers in forever.
>>>>>
>>>>> Could be if it is a one time fee. Not sure what is in at the moment.
>>>>> But it started a long time ago so it is more likely to be the work
>>>>> of some 'visionary' to prevent the spread of knowledge which would
>>>>> cost them zillions. Look at how they closed down all things wifi,
>>>>> the first - prism or something - was documented etc. until it got
>>>>> bought out and hidden from there on. Even T10 started selling their
>>>>> documents many years ago... So far the rfc-s are not hidden, but for
>>>>> how long. Some Sauron seems to be be lurking in the shadows :-).
>>>>
>>>> A common problem.
>>>>
>>>>
>>>>>> A have MS Word 2016. Now MS Updater nags me to convert to Word365,
>>>>>> which is only by subscription. Strangely, Word 2016 is now developing
>>>>>> problems.
>>>>>>
>>>>>>
>>>>>>> I wonder if the $35 tool one can buy now will work on a PC with
>>>>>>> no internet connection. Guess I have only one way to know for sure.
>>>>>>
>>>>>> Very good question. And companies who want to protect their critical
>>>>>> computers and networks from ransomware attacks et al may well have an
>>>>>> air-gapped system.
>>>>>
>>>>> I am not concerned about our design critical stuff, it is all under
>>>>> dps. They got a foot in when xilinx bought the coolrunner some 20 years
>>>>> ago, we had a logic compiler I had written; the cpld-s we have now
>>>>> use an old xilinx tool, old enough to work with no internet.
>>>>
>>>> dps? Maybe Texas DPS?
>>>
>>> No, it is the OS run here, written/built on over the years by me.
>>>
>>> Just did a shot of what my screen can look like (usually not as
>>> cluttered):
>>> http://tgi-sci.com/misc/dps.gif
>>
>> Ahh. That looks suspiciously like assembly code. The horror!
>
>It sort of is - but is meant to not be tied to a specific architecture.
>And it lets me do a lot of things I haven't seen done elsewhere (so I
>implemented them into my tool when I needed them).
>Has my life been/is it "the horror"? Probably.
>
>>
>>>>> Guess I'll try some of these (too?) new fpga-s out, once I have a
>>>>> working logic as I need it I typically don't need to change it for
>>>>> many years. They seem new enough to be yet preoccupied with how
>>>>> to change one time sales into subscription, guess we'll see.
>>>>> Their fpga-s look really good on paper for what I am after.
>>>>
>>>> I'd say that my system of the future is air-gapped, as it's too hard
>>>> to keep up with the threat of the day, so all Internet-dependent tools
>>>> are excluded from consideration, and see what happens. You may need
>>>> to stop talking to the sales droids to convince them that you mean it.
>>>
>>> I don't have the muscle to make them change policy so I try - have been
>>> doing if for nearly 30 years now - to just be independent on software
>>> written by anyone but me.
>>
>> There are lots of customers with air-gapped systems. The point of the
>> query is to force the sales droid to tell you how to get that option,
>> or admit (through clenched teeth) that they do not support that
>> option.
>>
>>
>>> The one thing in our products we cannot
>>> reproduce without a wintel PC is a jedec file for a coolrunner CPLD,
>>> xilinx would not disclose its insides (we had a tool for it while
>>> it was Philips). Now I guess I'll settle for using someone else's
>>> fpga tool... Once I have the binary and a supply of silicon - which
>>> in our case it not large at all to be even a lifetime supply - I'll
>>> still have things under control I guess.
>>
>> Hmm. War story: Twenty years ago, I worked with a small company
>> whose chief designer had been a cryptographer at NSA.
>>
>> The FPGA design program (don't recall which one) did not allow one to
>> fix the identity and location of the I/O pins, so every FPGA program
>> spin randomly scrambled the pins, which raised havoc with the PC board
>> layout, and so on. The FPGA design program had closed file formats,
>> so the designer could not manually force things.
>>
>> So the designer's inner cryptographer came out - he cracked the file
>> format, if I recall using differential cryptanalysis methods, and then
>> he could manually edit the files to maintain pin locations from spin
>> to spin.
>>
>> .<https://en.wikipedia.org/wiki/Differential_cryptanalysis>
>
>I had a similar wartime story some 20+ years ago for the
>Philips coolrunner.
>I thught I had all the data to write the logic compiler for it so I
>designed it in. Then discovered they had not given me the multiplexor
>data... good luck doing it without that.

Classic trapping maneuver.

>So I wrote a tool and multiple simple sources for their tool and
>from the jedecs they generated gradually deciphered the multiplexor.

Yep. This is also a form of differential cryptanalysis. At NSA, they
would use a big computer and a lot of permutation matrix math to solve
for the wiring diagrams.

Like Gordon Welchman and Hut 6, as discussed on SED some time ago.

>Took me about a month of work...

I don't know how long it took the FPGA designer, but probably much
less. I don't think the files were encrypted or anything of the kind.
Just obscure and undocumented.

>I think I still have that mux decode data online, let me see...
>I do, <http://tgi-sci.com/misc/ziarev.txt>.
>And one of the coolrunners I did with my logic compiler using it
>back then: <http://tgi-sci.com/misc/mb2ata.txt>

Trans Galactic. There's gotta be a warp drive in there somewhere.

Joe Gwinn