EricP <ThatWouldBeTelling@thevillage.com> writes:
>Anton Ertl wrote:
>>
>> The 8008 fits an 8x14bits stack in its 3500 (PMOS) transistors, and
>> has a more complex architecture. And it probably was static rather
>> than dynamic RAM, because AFAIK there is no way to refresh it by
>> storing it to memory at regular intervals.
>
>8008 (circa 1972) and 8080 (circa 1974) were both dynamic internally.

Now I remember that the 6502 was dynamic, too, and the 65C02 was
static.

However, it was never really clear to me what this "dynamic" means,
other than having a lower limit on the clock rate.

Does it mean that these dynamic CPUs used DRAM for their registers?
If so, how were they refreshed?

>8008 required an externally generated 2 phase non overlapping
>pulsed clock with some rather strict timing requirements.
>Cycle time of each phase had minimum of 2 us, max of 3 us
>taking 2 clock cycles for 1 machine state cycle.
>First cycle, phase 1 is the precharge to internal memory and buses,
>phase 2 is read, second cycle phase 1 is precharge, phase 2 is write.

This sounds like each bit would require more transistors than the two
that Bernd Paysan assumed for the b16 variant (and for which he
suggested software refresh).

- anton
--
'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'
Mitch Alsup, <c17fcd89-f024-40e7-a594-88a85ac10d20o@googlegroups.com>

anton@mips.complang.tuwien.ac.at (Anton Ertl) writes:
>Bernd Paysan <bernd@net2o.de> writes:
>>Am Sat, 24 Jul 2021 10:22:08 GMT schrieb Anton Ertl:
>>> https://bernd-paysan.de/b16-presentation.pdf
....
>Today I lean more towards having a 16-bit ALU and letting the software
>synthesize 16-bit memory accesses out of 8-bit accesses, to avoid the
>need for a sequencer. Maybe I will revert that again when I think
>more about how to deal with immediate arguments.

For immediate arguments one could take a transputer-like approach (or
RISC-like, but the transputer seems more relevant given that we are
discussing a stack machine):

Immediates are synthesized on the top of return stack (that works out
better for conditional branches that deal with data on the top of the
data stack): Have an instruction that has a 7-bit immediate field and
pushes it sign-extended on the return stack; have another instruction
that has a 6-bit immediate field, shifts the top of return stack to
the left by 6 bits and puts the immediate field in the bottom 6 bits.

This means that in many cases we can have an immediate operand and the
instruction consuming the operand in the same number of bytes as the
6502. It leaves 64 encodings for other instructions, which should be
ample (the 6502 has 56).

It also means that I have now departed from the c18/b16 way of
encoding more than one instruction per word, and having immediate
arguments in extra words. I think that way would require more
transistors than just treating each byte as one instruction.

Concerning the need for multi-cycle instructions (and thus a
sequencer; but that could be cheap to implement), at least load and
store instructions need to be multi-cycle (one cycle for loading the
instruction, and at least one for loading or storing the data). And
given that multi-cycle instructions are needed anyway, having a
two-byte load and two-byte store may add few transistors.

- anton
--
'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'
Mitch Alsup, <c17fcd89-f024-40e7-a594-88a85ac10d20o@googlegroups.com>

Anton Ertl wrote:
> EricP <ThatWouldBeTelling@thevillage.com> writes:
>> Anton Ertl wrote:
>>> The 8008 fits an 8x14bits stack in its 3500 (PMOS) transistors, and
>>> has a more complex architecture. And it probably was static rather
>>> than dynamic RAM, because AFAIK there is no way to refresh it by
>>> storing it to memory at regular intervals.
>> 8008 (circa 1972) and 8080 (circa 1974) were both dynamic internally.
>
> Now I remember that the 6502 was dynamic, too, and the 65C02 was
> static.
>
> However, it was never really clear to me what this "dynamic" means,
> other than having a lower limit on the clock rate.
>
> Does it mean that these dynamic CPUs used DRAM for their registers?
> If so, how were they refreshed?

I don't know of any reason that any device would have a a minimum clock
rate unless its' internal state required a dynamic refresh to retain.
However the storage cells may not be identical to an actual DRAM,
i.e. not a single capacitor.

The only reason I can think of, and I don't think this applies here,
that a device might be static logic internally and not require periodic
refresh but still has a minimum clock, is if the some of the substrate
voltages are generated internally by charge pumps driven by the clock.
If the clock stops then the charge bleeds off, the voltages disappear,
and the logic looses its state.

The 4004 is pMOS and the manual explicitly says the register file
is dynamic ram. The internal functional diagram has a refresh counter
muxed into the register file.

The 8008 is pMOS and has the same timing as 4004 and the functional
diagram has the same refresh counter attached to the register file.

The 8080 is nMOS and has similar clocking to 4004 and 8008.
The manual does not show a refresh counter on the internal functional
diagram but it does state that it is a "a dynamic device" that requires
a clock for refresh and timing control.

>> 8008 required an externally generated 2 phase non overlapping
>> pulsed clock with some rather strict timing requirements.
>> Cycle time of each phase had minimum of 2 us, max of 3 us
>> taking 2 clock cycles for 1 machine state cycle.
>> First cycle, phase 1 is the precharge to internal memory and buses,
>> phase 2 is read, second cycle phase 1 is precharge, phase 2 is write.
>
> This sounds like each bit would require more transistors than the two
> that Bernd Paysan assumed for the b16 variant (and for which he
> suggested software refresh).
>
> - anton

EricP <ThatWouldBeTelling@thevillage.com> writes:
>The 4004 is pMOS and the manual explicitly says the register file
>is dynamic ram. The internal functional diagram has a refresh counter
>muxed into the register file.
>
>The 8008 is pMOS and has the same timing as 4004 and the functional
>diagram has the same refresh counter attached to the register file.

My current understanding from this description is that the counter
counts through the various registers, and at some point during
instruction execution one register is read and written back.

Looking at the 6502 microarchitecture as described in
https://i.imgur.com/BkZ9o.png, with its individual registers on 4 or
so buses, and the way it is clocked, at first it seemed unplausible to
me that it could do automatic refreshing of DRAM registers.

But thinking about it, it's not that outlandish: When loading the next
instruction, the SB and DB buses are unused and can be used for
reading from one of the registers that can keep data for a long time
without being necessarily updated (in all bits): A, X, Y, S, P; and
the control logic can produce the right signals to do it. I don't see
anything like a refresh counter for counting through these registers,
but then not all of the signals from the timing generation logic are
clear to me, nor the control flip-flops; so the refresh counter might
hide in there.

It's interesting that despite the hardware limitations none of these
architectures fell back on software assist for refresh.

- anton
--
'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'
Mitch Alsup, <c17fcd89-f024-40e7-a594-88a85ac10d20o@googlegroups.com>

On Wednesday, July 28, 2021 at 7:50:08 PM UTC-5, EricP wrote:
> Anton Ertl wrote:
> > EricP <ThatWould...@thevillage.com> writes:
> >> Anton Ertl wrote:
> >>> The 8008 fits an 8x14bits stack in its 3500 (PMOS) transistors, and
> >>> has a more complex architecture. And it probably was static rather
> >>> than dynamic RAM, because AFAIK there is no way to refresh it by
> >>> storing it to memory at regular intervals.
> >> 8008 (circa 1972) and 8080 (circa 1974) were both dynamic internally.
> >
> > Now I remember that the 6502 was dynamic, too, and the 65C02 was
> > static.
> >
> > However, it was never really clear to me what this "dynamic" means,
> > other than having a lower limit on the clock rate.
> >
> > Does it mean that these dynamic CPUs used DRAM for their registers?
> > If so, how were they refreshed?
<
> I don't know of any reason that any device would have a a minimum clock
> rate unless its' internal state required a dynamic refresh to retain.
> However the storage cells may not be identical to an actual DRAM,
> i.e. not a single capacitor.
<
Mc 68020 had a minimum clock rate. There were latches between stages
that were a capacitor followed by an inverter driving the next stage, (also
there were pairs of capacitors driving a sense amplifier driving true-comp
to the next stage.)
>
> The only reason I can think of, and I don't think this applies here,
> that a device might be static logic internally and not require periodic
> refresh but still has a minimum clock, is if the some of the substrate
> voltages are generated internally by charge pumps driven by the clock.
> If the clock stops then the charge bleeds off, the voltages disappear,
> and the logic looses its state.
>
> The 4004 is pMOS and the manual explicitly says the register file
> is dynamic ram. The internal functional diagram has a refresh counter
> muxed into the register file.
>
> The 8008 is pMOS and has the same timing as 4004 and the functional
> diagram has the same refresh counter attached to the register file.
>
> The 8080 is nMOS and has similar clocking to 4004 and 8008.
> The manual does not show a refresh counter on the internal functional
> diagram but it does state that it is a "a dynamic device" that requires
> a clock for refresh and timing control.
> >> 8008 required an externally generated 2 phase non overlapping
> >> pulsed clock with some rather strict timing requirements.
> >> Cycle time of each phase had minimum of 2 us, max of 3 us
> >> taking 2 clock cycles for 1 machine state cycle.
> >> First cycle, phase 1 is the precharge to internal memory and buses,
> >> phase 2 is read, second cycle phase 1 is precharge, phase 2 is write.
> >
> > This sounds like each bit would require more transistors than the two
> > that Bernd Paysan assumed for the b16 variant (and for which he
> > suggested software refresh).
> >
> > - anton

Anton Ertl wrote:
> EricP <ThatWouldBeTelling@thevillage.com> writes:
>> The 4004 is pMOS and the manual explicitly says the register file
>> is dynamic ram. The internal functional diagram has a refresh counter
>> muxed into the register file.
>>
>> The 8008 is pMOS and has the same timing as 4004 and the functional
>> diagram has the same refresh counter attached to the register file.
>
> My current understanding from this description is that the counter
> counts through the various registers, and at some point during
> instruction execution one register is read and written back.
>
> Looking at the 6502 microarchitecture as described in
> https://i.imgur.com/BkZ9o.png, with its individual registers on 4 or
> so buses, and the way it is clocked, at first it seemed unplausible to
> me that it could do automatic refreshing of DRAM registers.
>
> But thinking about it, it's not that outlandish: When loading the next
> instruction, the SB and DB buses are unused and can be used for
> reading from one of the registers that can keep data for a long time
> without being necessarily updated (in all bits): A, X, Y, S, P; and
> the control logic can produce the right signals to do it. I don't see
> anything like a refresh counter for counting through these registers,
> but then not all of the signals from the timing generation logic are
> clear to me, nor the control flip-flops; so the refresh counter might
> hide in there.
>
> It's interesting that despite the hardware limitations none of these
> architectures fell back on software assist for refresh.
>
> - anton

The wikipedia article on 6501/6502 is an interesting read.
https://en.wikipedia.org/wiki/MOS_Technology_6501

The 650x designers left Motorola after designing the nMOS 6800.
6800 nMOS required 3 voltages -5V, (gnd), +5V, +12V.
One of 6800 features was the on-chip voltage inverter for generating -5V,
and the voltage doubler for +12V invented and patented by John Buchanan
(the charge pumps I referred to earlier.)

Patent 3942047 MOS DC Voltage booster circuit, Buchanan, 1974
https://patents.google.com/patent/US3942047A/en?oq=3942047

On 8080 these voltages were externally supplied from DC-to-DC converters,
which are expensive, inefficient, and get quite hot.

Buchanan was left Motorola for MOS Technologies with the others
and designed the 650x's voltage generators.

6501 was pin compatible with 6800 and had the same 2 clocks phase
(phase 2 was just the compliment of phase 1 so its not clear why
6800 did that - maybe current draw for volt generators).
At any rate, the 6502 used just a single 5V clock.

So I'm guessing that 6800 and 650x used static latches for their registers,
the phi-1 and phi-2 clocks referred to on the JPG are generated internally
from clock edge-triggered, self-timed circuits to precharge the bus,
and the minimum clock was for the voltage generators as I suggested.

The nMOS 8080 had no such on-chip voltage generators so I have no idea
why it has a minimum clock of 0.5 MHz.

EricP <ThatWouldBeTelling@thevillage.com> schrieb:

> So I'm guessing that 6800 and 650x used static latches for their registers,

https://downloads.reactivemicro.com/Electronics/CPU/6502%20Schematic.pdf
has the schematics, if you can read them, you could look it up :-)

On 7/29/21 1:48 PM, EricP wrote:
> 6501 was pin compatible with 6800 and had the same 2 clocks phase
> (phase 2 was just the compliment of phase 1 so its not clear why
> 6800 did that - maybe current draw for volt generators).
> At any rate, the 6502 used just a single 5V clock.

The MC6800 clocks were required to be nonoverlapping. Usually supplied
by a MC6875.

--
http://davesrocketworks.com
David Schultz

EricP <ThatWouldBeTelling@thevillage.com> writes:
>The wikipedia article on 6501/6502 is an interesting read.
>https://en.wikipedia.org/wiki/MOS_Technology_6501
>
>The 650x designers left Motorola after designing the nMOS 6800.
>6800 nMOS required 3 voltages -5V, (gnd), +5V, +12V.
>One of 6800 features was the on-chip voltage inverter for generating -5V,
>and the voltage doubler for +12V invented and patented by John Buchanan
>(the charge pumps I referred to earlier.)
>
>Patent 3942047 MOS DC Voltage booster circuit, Buchanan, 1974
>https://patents.google.com/patent/US3942047A/en?oq=3942047
....
>So I'm guessing that 6800 and 650x used static latches for their registers,
>the phi-1 and phi-2 clocks referred to on the JPG are generated internally
>from clock edge-triggered, self-timed circuits to precharge the bus,
>and the minimum clock was for the voltage generators as I suggested.

According to the article you linked above, the 6501/6502 used
depletion-load NMOS:

|depletion-load NMOS is a form of digital logic family that uses only a
|single power supply voltage, unlike earlier nMOS (n-type metal-oxide
|semiconductor) logic families that needed more than one different
|power supply voltage.

<https://en.wikipedia.org/wiki/Depletion-load_NMOS>

So the 6501/6502 do not need such voltage generators.

>The nMOS 8080 had no such on-chip voltage generators so I have no idea
>why it has a minimum clock of 0.5 MHz.

Your earlier theory that Intel used DRAM for registers is plausible
given that they already had experience with that.

- anton
--
'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'
Mitch Alsup, <c17fcd89-f024-40e7-a594-88a85ac10d20o@googlegroups.com>

On Tuesday, July 27, 2021 at 4:56:42 PM UTC-6, MitchAlsup wrote:

> The utility of reinventing this wheel in today's world and market is so close
> to zero it nears exponent underflow.

Oh, that may be, but I never thought that this was what the OP's question
was about.
The original 6502 was a masterpiece of economical design.
Could it be bettered by a designer today?
I would suspect:
- not by much, because it was done so well;
- but it is not the case that modern designers have forgotten how to design
circuits efficiently. They still want to pack *more* on each die, even if that
more is 11 cores instead of 10, and those cores are GBOoO.

John Savard

On 28.07.2021 11:46, Anton Ertl wrote:
> EricP <ThatWouldBeTelling@thevillage.com> writes:
>
> Now I remember that the 6502 was dynamic, too, and the 65C02 was
> static.
>
> However, it was never really clear to me what this "dynamic" means,
> other than having a lower limit on the clock rate.
>
> Does it mean that these dynamic CPUs used DRAM for their registers?
> If so, how were they refreshed?
>
>
> This sounds like each bit would require more transistors than the two
> that Bernd Paysan assumed for the b16 variant (and for which he
> suggested software refresh).
>
> - anton
>

See https://en.wikipedia.org/wiki/Dynamic_logic_(digital_electronics) .

However, the distinction made in this article is not clear enough, as
there is as well clocked static logic.

To put it short, signals in dynamic logic circuits are always "in
flight" and only buffered by (small) capacitors between the gates, thus
the need for a minimal clock rate specification (roughly 5 tau of the
buffers), while static logic has latches between functional blocks that
keep the signals up as long as Vcc is applied, so that even if the clock
is stopped, the circuit state is held.

Besides, the maximum clock rate for dynamic logic may also be
constrained to a substantial lower clock rate than resulting from
switching times, because the capacitors can only be charged/discharged
with rates depending on gate fan-out.

On the other hand, the clock rate for static logic is restrained by the
additional latch switching times.

In summary, dynamic logic needs less silicon and less energy (if
designed correctly), but static logic is less dependent on clock phase
and stability, and has the advantage of a wide frequency range.

Today's big chips usually incorporate a mixture of both.

--
Regards,
Bernd

On Friday, July 30, 2021 at 11:40:36 AM UTC-5, Bernd Linsel wrote:
> On 28.07.2021 11:46, Anton Ertl wrote:
> > EricP <ThatWould...@thevillage.com> writes:
> >
> > Now I remember that the 6502 was dynamic, too, and the 65C02 was
> > static.
> >
> > However, it was never really clear to me what this "dynamic" means,
> > other than having a lower limit on the clock rate.
> >
> > Does it mean that these dynamic CPUs used DRAM for their registers?
> > If so, how were they refreshed?
> >
> >
> > This sounds like each bit would require more transistors than the two
> > that Bernd Paysan assumed for the b16 variant (and for which he
> > suggested software refresh).
> >
> > - anton
> >
> See https://en.wikipedia.org/wiki/Dynamic_logic_(digital_electronics) .
>
> However, the distinction made in this article is not clear enough, as
> there is as well clocked static logic.
>
> To put it short, signals in dynamic logic circuits are always "in
> flight" and only buffered by (small) capacitors between the gates, thus
<
During the precharge time period, the signals are not "in flight" they are
solidly driven in one direction (usually high). It is only in the evaluation
period that the signals can be pulled low and then float until the precharge
period comes back around.
<
> the need for a minimal clock rate specification (roughly 5 tau of the
> buffers), while static logic has latches between functional blocks that
> keep the signals up as long as Vcc is applied, so that even if the clock
> is stopped, the circuit state is held.
>
> Besides, the maximum clock rate for dynamic logic may also be
> constrained to a substantial lower clock rate than resulting from
> switching times, because the capacitors can only be charged/discharged
> with rates depending on gate fan-out.
<
Some circuits such as integer adders are actually faster and lower power
in static implementations than in dynamic implementations.
>
> On the other hand, the clock rate for static logic is restrained by the
> additional latch switching times.
>
> In summary, dynamic logic needs less silicon and less energy (if
> designed correctly), but static logic is less dependent on clock phase
> and stability, and has the advantage of a wide frequency range.
>
> Today's big chips usually incorporate a mixture of both.
<
Mostly, the dynamic parts are hidden from designers inside macros that
the designer is not allowed to even look at. So, while there are dynamic
parts to modern chips, 99% of the designers work in purely static design
capacities. SRAM macros have internal dynamic components (bit lines
sense amplifiers,...) but the interface given to the designers using said
macro smells distinctly static (except that some libraries mandate that
the read out from the sense amplifiers are latched (or floped) before
used==seen by other signals. Very few things "on the data path" are
dynamic these days, essentially nothing in the control path is dynamic.
>
> --
> Regards,
> Bernd

Quadibloc <jsavard@ecn.ab.ca> schrieb:
> On Tuesday, July 27, 2021 at 4:56:42 PM UTC-6, MitchAlsup wrote:
>
>> The utility of reinventing this wheel in today's world and market is so close
>> to zero it nears exponent underflow.
>
> Oh, that may be, but I never thought that this was what the OP's question
> was about.
> The original 6502 was a masterpiece of economical design.
> Could it be bettered by a designer today?
> I would suspect:
> - not by much, because it was done so well;
> - but it is not the case that modern designers have forgotten how to design
> circuits efficiently. They still want to pack *more* on each die, even if that
> more is 11 cores instead of 10, and those cores are GBOoO.

If you take the basic concept of a 6502 (single-byte instructions,
heavy on sequencing, but not as heavy as the Z80) I think they
were pretty close to optimum on the cost/performance curve.

To expand a little on a previous post, I still think that a
proto-RISC design could have been superior. A design with

- All 16 bit instructions only
- Load/store architecture
- 16 registers of 16 bits each
- Eight bit opcode, eight bit data
- Possibility of 16-bit immediates for all arithmetic
operations, load and store for the address
- Format: op Ra, Ra or op Ra, #immediate (4 bits)

can probably be made to fit on a 6502-sized die using the
technology of the day.

Of course, such a design would be screaming to have a 16-bit
data bus. Power, Ground, Memory ready, IRQ, Reset, Read/Write,
NMI, Clock. Would that be enough?

Thomas Koenig wrote:
> EricP <ThatWouldBeTelling@thevillage.com> schrieb:
>
>> So I'm guessing that 6800 and 650x used static latches for their registers,
>
> https://downloads.reactivemicro.com/Electronics/CPU/6502%20Schematic.pdf
> has the schematics, if you can read them, you could look it up :-)

Thanks.

At the top right, latches for stack pointer, X and Y -
two inverters back to back, with the 2 pass gates cp2 and x6 being a mux,
and pass gate x7 output onto the bus.
To set the latch, put the data on the bus, set cp2=0 and x6=1.
Then x6=0 and cp2=1 to hold that value.

Since cp2 is clock pulse 2, it goes 0 every 1/2 cycle which leaves
its inverter gate input floating. I was taught to never do this.
Anyway, that might be a source of the minimum clock - if cp2 is
missing the gate charge bleeds off and loses its feedback state.

Anton Ertl wrote:
> EricP <ThatWouldBeTelling@thevillage.com> writes:
>> The wikipedia article on 6501/6502 is an interesting read.
>> https://en.wikipedia.org/wiki/MOS_Technology_6501
>>
>> The 650x designers left Motorola after designing the nMOS 6800.
>> 6800 nMOS required 3 voltages -5V, (gnd), +5V, +12V.
>> One of 6800 features was the on-chip voltage inverter for generating -5V,
>> and the voltage doubler for +12V invented and patented by John Buchanan
>> (the charge pumps I referred to earlier.)
>
> According to the article you linked above, the 6501/6502 used
> depletion-load NMOS:
>
> |depletion-load NMOS is a form of digital logic family that uses only a
> |single power supply voltage, unlike earlier nMOS (n-type metal-oxide
> |semiconductor) logic families that needed more than one different
> |power supply voltage.
>
> <https://en.wikipedia.org/wiki/Depletion-load_NMOS>
>
> So the 6501/6502 do not need such voltage generators.

Oops, right. Sorry about that. I was multitasking too much with
the 6800 article and mixed them up.

Never mind.

>> The nMOS 8080 had no such on-chip voltage generators so I have no idea
>> why it has a minimum clock of 0.5 MHz.
>
> Your earlier theory that Intel used DRAM for registers is plausible
> given that they already had experience with that.
>
> - anton

On 7/30/21 1:55 PM, Thomas Koenig wrote:
> Quadibloc <jsavard@ecn.ab.ca> schrieb:
>> On Tuesday, July 27, 2021 at 4:56:42 PM UTC-6, MitchAlsup wrote:
>>
>>> The utility of reinventing this wheel in today's world and market is so close
>>> to zero it nears exponent underflow.
>>
>> Oh, that may be, but I never thought that this was what the OP's question
>> was about.
>> The original 6502 was a masterpiece of economical design.
>> Could it be bettered by a designer today?
>> I would suspect:
>> - not by much, because it was done so well;
>> - but it is not the case that modern designers have forgotten how to design
>> circuits efficiently. They still want to pack *more* on each die, even if that
>> more is 11 cores instead of 10, and those cores are GBOoO.
>
> If you take the basic concept of a 6502 (single-byte instructions,
> heavy on sequencing, but not as heavy as the Z80) I think they
> were pretty close to optimum on the cost/performance curve.
>
> To expand a little on a previous post, I still think that a
> proto-RISC design could have been superior. A design with
>
> - All 16 bit instructions only
> - Load/store architecture
> - 16 registers of 16 bits each
> - Eight bit opcode, eight bit data
> - Possibility of 16-bit immediates for all arithmetic
> operations, load and store for the address
> - Format: op Ra, Ra or op Ra, #immediate (4 bits)
>

I think you just described the Motorola MCore except for 16-bit immediates.

> can probably be made to fit on a 6502-sized die using the
> technology of the day.
>
> Of course, such a design would be screaming to have a 16-bit
> data bus. Power, Ground, Memory ready, IRQ, Reset, Read/Write,
> NMI, Clock. Would that be enough?
>

On Friday, July 30, 2021 at 1:53:54 PM UTC-6, Brian G. Lucas wrote:
> On 7/30/21 1:55 PM, Thomas Koenig wrote:

> > To expand a little on a previous post, I still think that a
> > proto-RISC design could have been superior. A design with

> > - All 16 bit instructions only
> > - Load/store architecture
> > - 16 registers of 16 bits each
> > - Eight bit opcode, eight bit data
> > - Possibility of 16-bit immediates for all arithmetic
> > operations, load and store for the address
> > - Format: op Ra, Ra or op Ra, #immediate (4 bits)

> I think you just described the Motorola MCore except for 16-bit immediates.

If somebody designed a bare-bones 16-bit processor that fit on
an 8-bit sized die, what prevented it from becoming an amazing success
that made people forget all about the 6502, the 8080, and even the 6800?

Oh. Introduced in late 1997. Unfortunately, it was a little late to the party;
and so in real life, the TI 9900 was the only minimalist 16-bit chip that
tried to hasten the transition from 8-bit to 16-bit.

John Savard

John Levine <johnl@taugh.com> writes:

> According to Quadibloc <jsavard@ecn.ab.ca>:
>
>> On Friday, July 23, 2021 at 4:59:30 AM UTC-6, Thomas Koenig wrote:
>>
>>> Another direction for retro-architectures... I've been looking
>>> at the 6502 a bit, and it really is quite an interesting design.
>>> Squeezing the functionality of a CPU into ~3500 transistors (plus
>>> ~1000 transistors used as resistors) was quite an achievement.
>>
>> Indeed.
>>
>> However, even the 6502, let alone the 6800 or the 8080, seemed
>> to me to have very complicated instruction sets compared to the
>> PDP-8.
>
> The original PDP-8 had only 1409 transisors, each one in a separate can,
> so it's not surprising. The first computer I programmed was a PDP-8 and
> it was a fantastically well-done tradeoff between extreme simplicity and
> usability.

Amusing data point: the LGP-30 had 19 flip-flops.

On 7/30/21 5:36 PM, Quadibloc wrote:
> On Friday, July 30, 2021 at 1:53:54 PM UTC-6, Brian G. Lucas wrote:
>> On 7/30/21 1:55 PM, Thomas Koenig wrote:
>
>>> To expand a little on a previous post, I still think that a
>>> proto-RISC design could have been superior. A design with
>
>>> - All 16 bit instructions only
>>> - Load/store architecture
>>> - 16 registers of 16 bits each
>>> - Eight bit opcode, eight bit data
>>> - Possibility of 16-bit immediates for all arithmetic
>>> operations, load and store for the address
>>> - Format: op Ra, Ra or op Ra, #immediate (4 bits)
>
>> I think you just described the Motorola MCore except for 16-bit immediates.
>
> If somebody designed a bare-bones 16-bit processor that fit on
> an 8-bit sized die, what prevented it from becoming an amazing success
> that made people forget all about the 6502, the 8080, and even the 6800?
>
> Oh. Introduced in late 1997. Unfortunately, it was a little late to the party;
> and so in real life, the TI 9900 was the only minimalist 16-bit chip that
> tried to hasten the transition from 8-bit to 16-bit.
>
The MCore is a 32-bit processor with 16-bit instructions.

> John Savard
>

On 7/30/2021 11:55 AM, Thomas Koenig wrote:
> Quadibloc <jsavard@ecn.ab.ca> schrieb:
>> On Tuesday, July 27, 2021 at 4:56:42 PM UTC-6, MitchAlsup wrote:
>>
>>> The utility of reinventing this wheel in today's world and market is so close
>>> to zero it nears exponent underflow.
>>
>> Oh, that may be, but I never thought that this was what the OP's question
>> was about.
>> The original 6502 was a masterpiece of economical design.
>> Could it be bettered by a designer today?
>> I would suspect:
>> - not by much, because it was done so well;
>> - but it is not the case that modern designers have forgotten how to design
>> circuits efficiently. They still want to pack *more* on each die, even if that
>> more is 11 cores instead of 10, and those cores are GBOoO.
>
> If you take the basic concept of a 6502 (single-byte instructions,
> heavy on sequencing, but not as heavy as the Z80) I think they
> were pretty close to optimum on the cost/performance curve.
>
> To expand a little on a previous post, I still think that a
> proto-RISC design could have been superior. A design with
>
> - All 16 bit instructions only
> - Load/store architecture
> - 16 registers of 16 bits each
> - Eight bit opcode, eight bit data
> - Possibility of 16-bit immediates for all arithmetic
> operations, load and store for the address
> - Format: op Ra, Ra or op Ra, #immediate (4 bits)
>
> can probably be made to fit on a 6502-sized die using the
> technology of the day.
>
> Of course, such a design would be screaming to have a 16-bit
> data bus.

Yes. With only an 8 bit bus, every instruction will require two memory
reads to fetch the instruction, which will substantially hurt
performance. 8088 anyone? :-(

--
- Stephen Fuld
(e-mail address disguised to prevent spam)

Quadibloc <jsavard@ecn.ab.ca> writes:
>If somebody designed a bare-bones 16-bit processor that fit on
>an 8-bit sized die, what prevented it from becoming an amazing success
>that made people forget all about the 6502, the 8080, and even the 6800?
>
>Oh. Introduced in late 1997. Unfortunately, it was a little late to the party;
>and so in real life, the TI 9900 was the only minimalist 16-bit chip that
>tried to hasten the transition from 8-bit to 16-bit.

There are all the Nova-like microprocessors (National Semiconductor
IPC-16A/520 PACE, microNOVA mN601, Fairchild 9440), but from what I
read, they tended to be not particularly fast, more expensive than the
6502 (6502: $25, mn601: $95 in lots of 100, 9440: $395 in lots of
100), and not marketed as aggressively as the 6502.

- anton
--
'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'
Mitch Alsup, <c17fcd89-f024-40e7-a594-88a85ac10d20o@googlegroups.com>

Thomas Koenig <tkoenig@netcologne.de> writes:
>If you take the basic concept of a 6502 (single-byte instructions,
>heavy on sequencing, but not as heavy as the Z80) I think they
>were pretty close to optimum on the cost/performance curve.

What makes you think so? Admittedly, we have not seen anything
guaranteed to be better, but then it's expensive (maybe a person-year)
and commercially pointless to design a CPU with 1975 technology today.

>To expand a little on a previous post, I still think that a
>proto-RISC design could have been superior. A design with
>
>- All 16 bit instructions only
>- Load/store architecture
>- 16 registers of 16 bits each
>- Eight bit opcode, eight bit data
>- Possibility of 16-bit immediates for all arithmetic
> operations, load and store for the address
>- Format: op Ra, Ra or op Ra, #immediate (4 bits)
>
>can probably be made to fit on a 6502-sized die using the
>technology of the day.

I see lots of things that make it more expensive:

16-bit ALU
16 registers of 16 bits (in addition to PC and status? or are they included?)
Bernd Paysan's suggestion of using DRAM for registers might help here.
longer instruction buffer (especially with the 16-bit immediates)

What might make it cheaper:

Depending on the instruction set: A simpler decoder with fewer cycles
to generate signals for (although 6502 was ingenious in minimizing the
microcode for its instruction set). Looking at the 6502 die shot
description in
<https://en.wikipedia.org/wiki/MOS_Technology_6502#Technical_description>,
apparently half of the 6502 was dedicated to control (microcode PLA
and random), so there is substantial room for improvement here.

>Of course, such a design would be screaming to have a 16-bit
>data bus. Power, Ground, Memory ready, IRQ, Reset, Read/Write,
>NMI, Clock. Would that be enough?

The 6502 has an extra VSS pin, 3 N.C. (not connected?) pins, a sync
pin, an S0 pin and two clock-out pins in addition. Not sure what the
sync and S0 pins are good for, but if you can do without all these
pins, a 16-bit data bus would be technically possible.

But the result does not fit your original requirements, and in 1975
would have been a commercial failure. Remember that for the 1981 IBM
PC, IBM chose the 8088 over the 8086, because a system with a 16-bit
data bus is significantly more expensive than one with an 8-bit data
bus.

If we stick with an 8-bit data bus as you originally required, your
16-bit instructions may be suboptimal. I also thought about something
RISC-like, but this aspect steered me to something b16-like.

- anton
--
'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'
Mitch Alsup, <c17fcd89-f024-40e7-a594-88a85ac10d20o@googlegroups.com>

Anton Ertl <anton@mips.complang.tuwien.ac.at> schrieb:
> Thomas Koenig <tkoenig@netcologne.de> writes:
>>If you take the basic concept of a 6502 (single-byte instructions,
>>heavy on sequencing, but not as heavy as the Z80) I think they
>>were pretty close to optimum on the cost/performance curve.
>
> What makes you think so? Admittedly, we have not seen anything
> guaranteed to be better, but then it's expensive (maybe a person-year)
> and commercially pointless to design a CPU with 1975 technology today.
>
>>To expand a little on a previous post, I still think that a
>>proto-RISC design could have been superior. A design with
>>
>>- All 16 bit instructions only
>>- Load/store architecture
>>- 16 registers of 16 bits each
>>- Eight bit opcode, eight bit data
>>- Possibility of 16-bit immediates for all arithmetic
>> operations, load and store for the address
>>- Format: op Ra, Ra or op Ra, #immediate (4 bits)
>>
>>can probably be made to fit on a 6502-sized die using the
>>technology of the day.
>
> I see lots of things that make it more expensive:
>
> 16-bit ALU

The ALU should perform:

- ADD, SUB, ADDC, SUBC
- OR, AND, NOT, XOR
- ROL, ROR, ASL

The most expensive part is the adder (used as adder subtractor
of course). A 16-bit ripple-carry adder (have to leave _some_
room for improvement) including the xor is about 500 transistors

Shift instructions are just wiring. AND, OR and NOT are cheap, for
XOR, the XOR from the adder/subtractor can be re-used.

The processor should probably be set up so that the ALU also
does branch calculations.

So, ~ 700-800 transistors for the ALU including the multiplexers.

> 16 registers of 16 bits (in addition to PC and status? or are they included?)

16 registers of 16 bits is 256 bits, four transistors each (like they
did on the actual 6502), with multiplexers, lets's say 1200 transistors.

2000 so far.

> Bernd Paysan's suggestion of using DRAM for registers might help here.
> longer instruction buffer (especially with the 16-bit immediates)
>
> What might make it cheaper:
>
> Depending on the instruction set: A simpler decoder with fewer cycles
> to generate signals for (although 6502 was ingenious in minimizing the
> microcode for its instruction set). Looking at the 6502 die shot
> description in
><https://en.wikipedia.org/wiki/MOS_Technology_6502#Technical_description>,
> apparently half of the 6502 was dedicated to control (microcode PLA
> and random), so there is substantial room for improvement here.

That was the point I was trying to get across. A proto-RISC 16-bit
processor could get by without much of the sequencing and control
logic on the 6502. Let's say the additional logic is implemented
in 1500 transistors (not unreasonable), and we're up to 3500.

>>Of course, such a design would be screaming to have a 16-bit
>>data bus. Power, Ground, Memory ready, IRQ, Reset, Read/Write,
>>NMI, Clock. Would that be enough?
>
> The 6502 has an extra VSS pin, 3 N.C. (not connected?) pins, a sync
> pin, an S0 pin and two clock-out pins in addition. Not sure what the
> sync and S0 pins are good for, but if you can do without all these
> pins, a 16-bit data bus would be technically possible.

> But the result does not fit your original requirements, and in 1975
> would have been a commercial failure. Remember that for the 1981 IBM
> PC, IBM chose the 8088 over the 8086, because a system with a 16-bit
> data bus is significantly more expensive than one with an 8-bit data
> bus.

You're right, this could be a significant bottleneck, but maybe still
better than a 6502.

Stephen Fuld wrote:
> On 7/30/2021 11:55 AM, Thomas Koenig wrote:
>> Of course, such a design would be screaming to have a 16-bit
>> data bus.
>
> Yes.  With only an 8 bit bus, every instruction will require two memory
> reads to fetch the instruction, which will substantially hurt
> performance.  8088 anyone?  :-(

The only good thing about 8088 was the fact that you could statically
calculate the number of cycles a given code construct would use, i.e.
"number of bytes touched/read/written by code or data" multiplied by 4.

Terje

--
- <Terje.Mathisen at tmsw.no>
"almost all programming can be viewed as an exercise in caching"

On Saturday, July 31, 2021 at 7:23:02 AM UTC-5, Thomas Koenig wrote:
> Anton Ertl <an...@mips.complang.tuwien.ac.at> schrieb:
> > Thomas Koenig <tko...@netcologne.de> writes:
> >>If you take the basic concept of a 6502 (single-byte instructions,
> >>heavy on sequencing, but not as heavy as the Z80) I think they
> >>were pretty close to optimum on the cost/performance curve.
> >
> > What makes you think so? Admittedly, we have not seen anything
> > guaranteed to be better, but then it's expensive (maybe a person-year)
> > and commercially pointless to design a CPU with 1975 technology today.
> >
> >>To expand a little on a previous post, I still think that a
> >>proto-RISC design could have been superior. A design with
> >>
> >>- All 16 bit instructions only
> >>- Load/store architecture
> >>- 16 registers of 16 bits each
> >>- Eight bit opcode, eight bit data
> >>- Possibility of 16-bit immediates for all arithmetic
> >> operations, load and store for the address
> >>- Format: op Ra, Ra or op Ra, #immediate (4 bits)
> >>
> >>can probably be made to fit on a 6502-sized die using the
> >>technology of the day.
> >
> > I see lots of things that make it more expensive:
> >
> > 16-bit ALU
> The ALU should perform:
>
> - ADD, SUB, ADDC, SUBC
> - OR, AND, NOT, XOR
> - ROL, ROR, ASL
>
> The most expensive part is the adder (used as adder subtractor
> of course). A 16-bit ripple-carry adder (have to leave _some_
> room for improvement) including the xor is about 500 transistors
>
> Shift instructions are just wiring. AND, OR and NOT are cheap, for
> XOR, the XOR from the adder/subtractor can be re-used.
<
Shift instructions require multiplexers.
>
> The processor should probably be set up so that the ALU also
> does branch calculations.
>
> So, ~ 700-800 transistors for the ALU including the multiplexers.
> > 16 registers of 16 bits (in addition to PC and status? or are they included?)
> 16 registers of 16 bits is 256 bits, four transistors each (like they
> did on the actual 6502), with multiplexers, lets's say 1200 transistors.
<
The 4 transistors make up the storage unit, but you have not added the
read (mux) or write ports, so the count is a bit higher.
>
> 2000 so far.
> > Bernd Paysan's suggestion of using DRAM for registers might help here.
> > longer instruction buffer (especially with the 16-bit immediates)
> >
> > What might make it cheaper:
> >
> > Depending on the instruction set: A simpler decoder with fewer cycles
> > to generate signals for (although 6502 was ingenious in minimizing the
> > microcode for its instruction set). Looking at the 6502 die shot
> > description in
> ><https://en.wikipedia.org/wiki/MOS_Technology_6502#Technical_description>,
> > apparently half of the 6502 was dedicated to control (microcode PLA
> > and random), so there is substantial room for improvement here.
<
Like Mc 88100, 6502 used a single NOR plane as microcode.
<
> That was the point I was trying to get across. A proto-RISC 16-bit
> processor could get by without much of the sequencing and control
> logic on the 6502. Let's say the additional logic is implemented
> in 1500 transistors (not unreasonable), and we're up to 3500.
> >>Of course, such a design would be screaming to have a 16-bit
> >>data bus. Power, Ground, Memory ready, IRQ, Reset, Read/Write,
> >>NMI, Clock. Would that be enough?
> >
> > The 6502 has an extra VSS pin, 3 N.C. (not connected?) pins, a sync
> > pin, an S0 pin and two clock-out pins in addition. Not sure what the
> > sync and S0 pins are good for, but if you can do without all these
> > pins, a 16-bit data bus would be technically possible.
>
> > But the result does not fit your original requirements, and in 1975
> > would have been a commercial failure. Remember that for the 1981 IBM
> > PC, IBM chose the 8088 over the 8086, because a system with a 16-bit
> > data bus is significantly more expensive than one with an 8-bit data
> > bus.
> You're right, this could be a significant bottleneck, but maybe still
> better than a 6502.