MitchAlsup <MitchAlsup@aol.com> schrieb:
> On Saturday, July 31, 2021 at 12:31:34 PM UTC-5, Marcus wrote:
>> On 2021-07-31 18:48, MitchAlsup wrote:
>> > On Saturday, July 31, 2021 at 7:23:02 AM UTC-5, Thomas Koenig wrote:

>> >> The ALU should perform:
>> >>
>> >> - ADD, SUB, ADDC, SUBC
>> >> - OR, AND, NOT, XOR
>> >> - ROL, ROR, ASL
>> >>
>> >> The most expensive part is the adder (used as adder subtractor
>> >> of course). A 16-bit ripple-carry adder (have to leave _some_
>> >> room for improvement) including the xor is about 500 transistors
>> >>
>> >> Shift instructions are just wiring. AND, OR and NOT are cheap, for
>> >> XOR, the XOR from the adder/subtractor can be re-used.
>> > <
>> > Shift instructions require multiplexers.
>>
>> Are we talking about variable shifts, or 6502-style single-step shifts?
>>
>> The latter would only be wiring (one fixed wiring per shift opcode).
><
> You still need to select between the ROR, ROL, and ASL and that requires
> said multiplexer.

I've looked at this some more, and it has been done better in
the past.

Shift left can be done with an add with identical input (as it
was on the 6502). For shift right, you need a switch to the right
(again, as on the 6502). Handling carry is then just a few gates
on the fist and the last bit.

For retro-designing this kind of chip, it helps not to think about
the large muxes in textbooks, but rather of the ALU being made up
of individual one-bit units.

MitchAlsup <MitchAlsup@aol.com> schrieb:

> a) this was a design that prospered in the realm of embarrassing frugality,
> There is not a SINGLE flip-flop in the design, there is no clock tree, there is
> no scan path,...........it is delicious in its simplicity.

Agreed.

><
> b) modern tools know nothing of this realm and impose a huge burden on
> designs targeting this corner of the design space.

If by modern tools you mean the tools that people use for CPU design,
agreed. However, there are tools which are more suitable for a
gate- or transistor-level design, and the low number of transistors
makes this feasible at least down to the transistor, less for the
actual chip design.

> c) the concept that we, who have exploited billions of transistors, could perform
> well in the ares of a handful of thousands of transistors is ludicrous. That we
> who have dozens of metal layers could "do" a design with only 1 is also ludicrous.
> No modern "tool" software can operate in this realm

> d) Modern design software (Verilog, simulators, FPGA breadboarding)
> is all designed to help those with industrial scale issues, not those of
> "significantly smaller than a modern hobbiest"

See above - designing something in the 6502 or Z80 league seems doable.

><
> I take my hat off to them; And give them a well deserved bow !

Agreed.

Thomas Koenig <tkoenig@netcologne.de> schrieb:
> pec...@gmail.com <peceed@gmail.com> schrieb:
>
>>> Yes. With only an 8 bit bus, every instruction will require two memory
>>> reads to fetch the instruction, which will substantially hurt
>>> performance. 8088 anyone? :-(
>> 6502 fetches 2 bytes per instruction anyway, so what is the problem?
>
> Still awkward, like I said, such a design screams for a 16-bit
> data bus.
>
> [...]
>
>> There is no 2r1w register file (too expensive), so processor needs much higher internal clock like Z80.
>
> 2r1w seems doable,

I took a look at this now.

It would be doable to use the basic design of the Z80 registers
which as been described at
http://www.righto.com/2014/10/how-z80s-registers-are-implemented-down.html

So, two inverters (one transistor and one depletion load transistor
each), plus two pass transistors from the positive and negative side
for driving them. The Z80, like the Intel designs at the time,
simply used bigger transistors to overrule the inverters. So,
six transistors per bit plus the driving logic. Add another pass
transistor per bit for a second, read-only bus, and you're up to 7.

Having 16 16-bit registers is also not out of this world. With its
register pairs, the Z80 had 14 pairs of 8-bit registers, so it
was quite possible to fit that many registers into the technology
of the era.

Thomas Koenig <tkoenig@netcologne.de> writes:
>Having 16 16-bit registers is also not out of this world. With its
>register pairs, the Z80 had 14 pairs of 8-bit registers, so it
>was quite possible to fit that many registers into the technology
>of the era.

The Z80 has 8500 transistors, pretty far from the target you set
earlier. The Z80 was also "introduced to the market" in July 1976,
while MOS sold the 6502 at the time of the Wescon in September 1975,
10 months earlier.

- anton
--
'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'
Mitch Alsup, <c17fcd89-f024-40e7-a594-88a85ac10d20o@googlegroups.com>

Anton Ertl <anton@mips.complang.tuwien.ac.at> schrieb:
> Thomas Koenig <tkoenig@netcologne.de> writes:
>>Having 16 16-bit registers is also not out of this world. With its
>>register pairs, the Z80 had 14 pairs of 8-bit registers, so it
>>was quite possible to fit that many registers into the technology
>>of the era.
>
> The Z80 has 8500 transistors, pretty far from the target you set
> earlier.

That is, of course, correct.

> The Z80 was also "introduced to the market" in July 1976,
> while MOS sold the 6502 at the time of the Wescon in September 1975,
> 10 months earlier.

Hm... I think I will continue to explore a bit more (in other words,
play around with Digital and see how many transistors I end up
with using parts of a reasonable micro-architecture).

On 8/8/21 8:03 AM, Anton Ertl wrote:
> Thomas Koenig <tkoenig@netcologne.de> writes:
>> Having 16 16-bit registers is also not out of this world. With its
>> register pairs, the Z80 had 14 pairs of 8-bit registers, so it
>> was quite possible to fit that many registers into the technology
>> of the era.
>
> The Z80 has 8500 transistors, pretty far from the target you set
> earlier. The Z80 was also "introduced to the market" in July 1976,
> while MOS sold the 6502 at the time of the Wescon in September 1975,
> 10 months earlier.
>
> - anton
>

The 1802 of course had 16 16-bit registers and appeared at about the
same time. Earlier if you count the two chip 1801.

I am not sure what the transistor count was (do I/O pads count?) but it
saved a few by using a 1 bit ALU.

--
http://davesrocketworks.com
David Schultz

Thomas Koenig <tkoenig@netcologne.de> writes:
>MitchAlsup <MitchAlsup@aol.com> schrieb:
>> You still need to select between the ROR, ROL, and ASL and that requires
>> said multiplexer.
>
>I've looked at this some more, and it has been done better in
>the past.
>
>Shift left can be done with an add with identical input (as it
>was on the 6502).

And ROL is ADC with identical input (yes, 6502 ROL is what is RCL in
IA-32/AMD64).

>For shift right, you need a switch to the right
>(again, as on the 6502).

A switch?

You certainly need some way to mux the outputs between this shift
right and the rest of the ALU, although I guess a MUX in NMOS is not
that expensive.

- anton
--
'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'
Mitch Alsup, <c17fcd89-f024-40e7-a594-88a85ac10d20o@googlegroups.com>

On Sunday, August 8, 2021 at 6:14:51 AM UTC-5, Thomas Koenig wrote:
> Thomas Koenig <tko...@netcologne.de> schrieb:
> > pec...@gmail.com <pec...@gmail.com> schrieb:
> >
> >>> Yes. With only an 8 bit bus, every instruction will require two memory
> >>> reads to fetch the instruction, which will substantially hurt
> >>> performance. 8088 anyone? :-(
> >> 6502 fetches 2 bytes per instruction anyway, so what is the problem?
> >
> > Still awkward, like I said, such a design screams for a 16-bit
> > data bus.
> >
> > [...]
> >
> >> There is no 2r1w register file (too expensive), so processor needs much higher internal clock like Z80.
> >
> > 2r1w seems doable,
>
> I took a look at this now.
>
> It would be doable to use the basic design of the Z80 registers
> which as been described at
> http://www.righto.com/2014/10/how-z80s-registers-are-implemented-down.html
>
> So, two inverters (one transistor and one depletion load transistor
> each), plus two pass transistors from the positive and negative side
> for driving them. The Z80, like the Intel designs at the time,
> simply used bigger transistors to overrule the inverters. So,
> six transistors per bit plus the driving logic. Add another pass
> transistor per bit for a second, read-only bus, and you're up to 7.
<
The cell described is a typical SAM cell (depletion style). The read
port read port requires 2 transistors, one to the true bus and one to
complement bus. Both buses (on a read) are precharged high and
one of the pass transistors pulls one of the buses down. A sense
amplifier detects the movement of the bus voltage and amplifies
it into a solid logic signal.
<
Adding a second port requires 2 more wires (true and complement)
and 2 more pass transistors.
<
Also note: a write is performed when the bus is driven (hi-low or low-hi)
and the pass gate driven high. The port is bidirectional.
<
If the bus is driven low-low and the pass gate asserted, it is likely
that the SRAM cell will self destruct as both side fight each other
for a logic value.
>
> Having 16 16-bit registers is also not out of this world. With its
> register pairs, the Z80 had 14 pairs of 8-bit registers, so it
> was quite possible to fit that many registers into the technology
> of the era.

Thomas Koenig wrote:
> > The Z80 has 8500 transistors, pretty far from the target you set
> > earlier.
> That is, of course, correct.
And 4 times more registers and about 3 times the die area in feature size units.
There are problems with better 6502:
1) The 6502 was designed as the cheapest possible processor for the embedded systems market with very window of opportunity. In this market, the lack of software was not a problem. We want to improve it in the context of the microcomputer market, which was not there in 1975.
2) The Z80 is designed to be the best processor in terms of reusing existing software and ease of programming.
3) Moore's Law was galloping. Any initial cost advantage was exponentially shrinking. A few years later, the Z80 and 6502 were sold at the same retail price.
3) The problem you really want to solve is "the best possible processor to start and dominate the microcomputer revolution." This chip must be preferred by Steve Wozniak over the 6502 and available at the time of the Apple I development.
Beware, doubling the die size will make the chip 3 times more expensive (70% yield for the 6502) - when it matters most.

On Sunday, August 8, 2021 at 1:12:41 PM UTC-5, pec...@gmail.com wrote:
> Thomas Koenig wrote:
> > > The Z80 has 8500 transistors, pretty far from the target you set
> > > earlier.
> > That is, of course, correct.
> And 4 times more registers and about 3 times the die area in feature size units.
> There are problems with better 6502:
> 1) The 6502 was designed as the cheapest possible processor for the embedded systems market with very window of opportunity. In this market, the lack of software was not a problem. We want to improve it in the context of the microcomputer market, which was not there in 1975.
> 2) The Z80 is designed to be the best processor in terms of reusing existing software and ease of programming.
> 3) Moore's Law was galloping. Any initial cost advantage was exponentially shrinking. A few years later, the Z80 and 6502 were sold at the same retail price.
<
When 6502 was originally brought out it was die cost limited.
By the time Z80 caught up ($$$) both were package cost limited.
<
This is the funny thing about More's law and the packaging of semiconductors. The initial cost is
dominated by die cost (design, manufacture, yield, testing} while the cost several years down the
road has seen the die cost decrease by something like a factor of 4× wile the cost to put it in a
package and the cost of the package itself have gone down only 10%.
<
> 3) The problem you really want to solve is "the best possible processor to start and dominate the microcomputer revolution." This chip must be preferred by Steve Wozniak over the 6502 and available at the time of the Apple I development.
> Beware, doubling the die size will make the chip 3 times more expensive (70% yield for the 6502) - when it matters most.

David Schultz <david.schultz@earthlink.net> writes:
>On 8/8/21 8:03 AM, Anton Ertl wrote:
>> The Z80 has 8500 transistors, pretty far from the target you set
>> earlier.

6,813 without the pull-up transistors (and the 6502 has 4528 with such
transistors).

>The 1802 of course had 16 16-bit registers and appeared at about the
>same time. Earlier if you count the two chip 1801.
>
>I am not sure what the transistor count was (do I/O pads count?) but it
>saved a few by using a 1 bit ALU.

According to
<https://en.wikipedia.org/wiki/Transistor_count#Microprocessors>, it
has 5000 transistors. It is also a CMOS CPU, which uses significantly
more transistors than equivalent NMOS circuits.

The process and die size metrics are also interesting:
proc size 8um equiv
6502 8um 21mm^2 21mm^2
1802 5um 27mm^2 69mm^2
Z80 4um 18mm^2 72mm^2

The 8um equiv numbers assume that each dimension scales as the process
size indicates.

- anton
--
'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'
Mitch Alsup, <c17fcd89-f024-40e7-a594-88a85ac10d20o@googlegroups.com>

On 8/8/21 4:20 PM, Anton Ertl wrote:

> The process and die size metrics are also interesting:
> proc size 8um equiv
> 6502 8um 21mm^2 21mm^2
> 1802 5um 27mm^2 69mm^2
> Z80 4um 18mm^2 72mm^2

The original CDP1802 used a 6um process while the later CDP1802A
switched to 5um. Chip size went from 6.0mm X 4.4mm to 4.8mm X 3.5mm.

The IEEE article I pulled those numbers from says 5,500 transistors.

--
http://davesrocketworks.com
David Schultz

On Sunday, August 8, 2021 at 9:29:50 AM UTC-5, David Schultz wrote:
> On 8/8/21 8:03 AM, Anton Ertl wrote:
> > Thomas Koenig <tko...@netcologne.de> writes:
> >> Having 16 16-bit registers is also not out of this world. With its
> >> register pairs, the Z80 had 14 pairs of 8-bit registers, so it
> >> was quite possible to fit that many registers into the technology
> >> of the era.
> >
> > The Z80 has 8500 transistors, pretty far from the target you set
> > earlier. The Z80 was also "introduced to the market" in July 1976,
> > while MOS sold the 6502 at the time of the Wescon in September 1975,
> > 10 months earlier.
> >
> > - anton
> >
> The 1802 of course had 16 16-bit registers and appeared at about the
> same time. Earlier if you count the two chip 1801.
>
> I am not sure what the transistor count was (do I/O pads count?) but it
> saved a few by using a 1 bit ALU.
<
I/O pads are an interesting "counting" problem back in the 2+µ days.
<
a) do you count the transistors and diodes used to protect the pads
from electrostatic discharges?
b) you you count the pull down transistor as 1 transistor or as the
8 transistors wired up to perform as 1 ?
c) same as b but for the P-channels or depletion devices ?
<
So you could get a small number like 2-4 or a large number like 32-40
depending on what you consider a transistor.
>
>
> --
> http://davesrocketworks.com
> David Schultz

MitchAlsup wrote:
> I/O pads are an interesting "counting" problem back in the 2+µ days.
Is "2 + µ" about layers?
As I understand, pads have no process scalability and they waste a lot of potential logic area when only 2 connection layers are available, so I have few questions:
Could MOS Tech simply add yet another layer without prohibitive R&D cost, or was MOS inherently restricted to 1 metallic layer?
Do you remember when more advanced processes with more metallization layers were introduced?

On Sunday, August 8, 2021 at 7:03:07 PM UTC-5, pec...@gmail.com wrote:
> MitchAlsup wrote:
> > I/O pads are an interesting "counting" problem back in the 2+µ days.
> Is "2 + µ" about layers?
<
It is about the lithography. 2+µ means everything bigger then 2µ
<
> As I understand, pads have no process scalability and they waste a lot of potential logic area when only 2 connection layers are available, so I have few questions:
> Could MOS Tech simply add yet another layer without prohibitive R&D cost, or was MOS inherently restricted to 1 metallic layer?
<
It was all about FAB technology.
<
> Do you remember when more advanced processes with more metallization layers were introduced?
<
In/at Motorola::
2.5µ: n-channel and depletion devices, 1 metal layer no silicide.
2.0µ: n-channel, p-channel, depletion devices, 1 metal layer, silicide..
1.5µ: n-channel, p-channel, 2 metal, silicide.
1.25µ: mostly a shrink of 1.5µ, a titanium base metal layer was allowed; so almost a 3M process.
1.0µ: n-channel, p-channel, 3 metal, salicide.
0.65µ: shrink of 1.0µ
0.5µ: n-channel, p-channel, bipolar transistors & diodes, 4 metal, salicide

silicide was a low resist metal diffusion added to polysilicon changing the poly from 500 Ohms/sq to 50 ohm/sq
salicide was a low resist metal diffusion added to both polysilicon and to crystal silicon reducing poly resistivity to 50 ohm/sq and crystalline resistance to ~100 ohm/sq.

It took a couple of generations to work out how to properly form the vias (barrier metals, current densities) before metal became "as many as you are willing to pay for". But basically anything after 0.5µ falls into that camp. {also note: while aluminum is a rather clean FAB substance, copper is a very nasty substance for the FAB.}

On Friday, August 6, 2021 at 12:01:29 AM UTC+1, chris wrote:
> You saw far more in the wdc effort than I did and the same for
> the Manx C complier. 6502 was off the shelf here in the uk, well
> supported and understood, while wdc was far away and don't
> remember if there was even a uk agent for the devices. Iirc, I
> did a grey import to the uk for Manx C, probably after seeing
> it advertised in Byte mag, and also having been fired up by
> things like the AT&T programmers workbench report, blue book,
> which seemed like another world. Still an asm programmer, didn't
> really have the knowledge base at the time to make best use of
> it, wasn't impressed with the code it produced and eventually
> gave up.

To be fair, the competition was often not hand-written assembly
but interpreted BASIC. I worked with Apple IIs on production
lines. Everything was BASIC for maintainability and portability.
We used Microsoft's Applesoft BASIC compiler (TASC) and got
a significant speedup, although not a huge one given that
multi-byte arithmetic, floating-point, strings, I/O etc. called into
a runtime library, just as it did when interpreted.

Of course hand-written assembly would have been faster and
smaller, but for those applications it wouldn't have made sense
for all sorts of reasons.

On 08/09/21 11:54, Al Grant wrote:
> On Friday, August 6, 2021 at 12:01:29 AM UTC+1, chris wrote:
>> You saw far more in the wdc effort than I did and the same for
>> the Manx C complier. 6502 was off the shelf here in the uk, well
>> supported and understood, while wdc was far away and don't
>> remember if there was even a uk agent for the devices. Iirc, I
>> did a grey import to the uk for Manx C, probably after seeing
>> it advertised in Byte mag, and also having been fired up by
>> things like the AT&T programmers workbench report, blue book,
>> which seemed like another world. Still an asm programmer, didn't
>> really have the knowledge base at the time to make best use of
>> it, wasn't impressed with the code it produced and eventually
>> gave up.
>
> To be fair, the competition was often not hand-written assembly
> but interpreted BASIC. I worked with Apple IIs on production
> lines. Everything was BASIC for maintainability and portability.
> We used Microsoft's Applesoft BASIC compiler (TASC) and got
> a significant speedup, although not a huge one given that
> multi-byte arithmetic, floating-point, strings, I/O etc. called into
> a runtime library, just as it did when interpreted.
>
> Of course hand-written assembly would have been faster and
> smaller, but for those applications it wouldn't have made sense
> for all sorts of reasons.

I think what some seem to forget is that in the early days of
micros, they were thought of not so much for computing, but as
a logic replacement. Where a single micro and a few support
devices could replace several boards full of TTL and CMOS
logic. After buying the first micro board it was a while before
a light switched on, as I realised just how powerful programmed
solutions could be. That's the point where I became completely
hooked on computing. Having the hardware background was a real
advantage later, when learning about comp sci principles and
system organisation...

On Friday, July 23, 2021 at 6:00:15 AM UTC-6, Quadibloc wrote:
> On Friday, July 23, 2021 at 4:59:30 AM UTC-6, Thomas Koenig wrote:
> > Another direction for retro-architectures... I've been looking
> > at the 6502 a bit, and it really is quite an interesting design.
> > Squeezing the functionality of a CPU into ~3500 transistors (plus
> > ~1000 transistors used as resistors) was quite an achievement.

> Indeed.

> However, even the 6502, let alone the 6800 or the 8080, seemed
> to me to have very complicated instruction sets compared to the
> PDP-8.

> But interestingly enough, the 12-bit SDS 92 had an instruction set
> that in many ways resembled those of the early 8-bit micros. (A
> manual describing its instruction set is, of course, on Bitsavers.)

Given that the PDP-8 was a very successful minicomputer, while
the SDS 92, even though it was the first commercially available
computer made from monolithic integrated circuits, is merely an
obscure historical footnote:

*why* were the first microprocessors designed with such
complicated instruction sets, if they could have used fewer
transistors with a simpler design?

John Savard

Quadibloc <jsavard@ecn.ab.ca> schrieb:
> On Friday, July 23, 2021 at 6:00:15 AM UTC-6, Quadibloc wrote:
>> On Friday, July 23, 2021 at 4:59:30 AM UTC-6, Thomas Koenig wrote:
>> > Another direction for retro-architectures... I've been looking
>> > at the 6502 a bit, and it really is quite an interesting design.
>> > Squeezing the functionality of a CPU into ~3500 transistors (plus
>> > ~1000 transistors used as resistors) was quite an achievement.
>
>> Indeed.
>
>> However, even the 6502, let alone the 6800 or the 8080, seemed
>> to me to have very complicated instruction sets compared to the
>> PDP-8.
>
>> But interestingly enough, the 12-bit SDS 92 had an instruction set
>> that in many ways resembled those of the early 8-bit micros. (A
>> manual describing its instruction set is, of course, on Bitsavers.)
>
> Given that the PDP-8 was a very successful minicomputer, while
> the SDS 92, even though it was the first commercially available
> computer made from monolithic integrated circuits, is merely an
> obscure historical footnote:
>
> *why* were the first microprocessors designed with such
> complicated instruction sets, if they could have used fewer
> transistors with a simpler design?

.... which is more or less the question which propted me to ask
if we could build a better 6502 :-)

One important point is the extreme cost of memory at the time.
People designed their ISAs for a very high code density because
of that.

> *why* were the first microprocessors designed with such
> complicated instruction sets, if they could have used fewer
> transistors with a simpler design?

Which part of the 6502's instruction set do you find "complicated" and
what kind of change do you think would have reduced the number of
transistors needed to implement it?

Stefan

Stefan Monnier <monnier@iro.umontreal.ca> schrieb:

> Which part of the 6502's instruction set do you find "complicated" and
> what kind of change do you think would have reduced the number of
> transistors needed to implement it?

The memory operands. A load/store architecture would have saved
a lot of decoding and sequencing and associated transistor (or,
better measure area), which could have been used for more and bigger
registers.

The Z80 is even stranger, with its 4-bit ALU for an 8-bit design,
and taking multiple CPU cycles for each "machine cycle" and multiple
machine cycles for each instruction.

Note that I am not confident that we can actually do better for
overall performance per transistor for the 6502. For the Z80,
I would be.

Thomas Koenig [2021-08-15 13:45:54] wrote:
> Stefan Monnier <monnier@iro.umontreal.ca> schrieb:
>> Which part of the 6502's instruction set do you find "complicated" and
>> what kind of change do you think would have reduced the number of
>> transistors needed to implement it?
> The memory operands. A load/store architecture would have saved
> a lot of decoding and sequencing and associated transistor (or,
> better measure area), which could have been used for more and bigger
> registers.

I think the discussion so far hasn't reached a clear conclusion on
whether it would have lead to something better (smaller or faster or
both). You might be right, but I think it's hard to tell without trying
it out [ and compared to the original designers we benefit from what
we've learned from history, so I really can't blame them. ].
I suspect that it could end up smaller but slower (because of the extra
memory accesses needed because of a less compact code).

> The Z80 is even stranger, with its 4-bit ALU for an 8-bit design,
> and taking multiple CPU cycles for each "machine cycle" and multiple
> machine cycles for each instruction.

For the Z80 I think the question is closed, indeed: we can clearly do
better with those resources. But note that part of its appeal/goal was
backward compatibility.

Stefan

Thomas Koenig <tkoenig@netcologne.de> writes:
>One important point is the extreme cost of memory at the time.
>People designed their ISAs for a very high code density because
>of that.

Not so sure about the 6502 in that respect, with having to often put a
CLC before an ADC, having to use one or two address bytes in addition
to the opcode for many instructions, and having to use at least twice
as many instructions for 16-bit operations.

- anton
--
'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'
Mitch Alsup, <c17fcd89-f024-40e7-a594-88a85ac10d20o@googlegroups.com>

On 8/15/21 10:58 AM, Anton Ertl wrote:
> Thomas Koenig <tkoenig@netcologne.de> writes:
>> One important point is the extreme cost of memory at the time.
>> People designed their ISAs for a very high code density because
>> of that.
>
> Not so sure about the 6502 in that respect, with having to often put a
> CLC before an ADC, having to use one or two address bytes in addition
> to the opcode for many instructions, and having to use at least twice
> as many instructions for 16-bit operations.
>

It could be worse. I still remember writing code for a PIC16F628 and my
shock at the lack of an add with carry instruction. You could fake it
but it took more than one extra instruction to do it. A real PITA

I suspect that it was more important that the design tools were nearly
non-existent. At best you could start with a design that was built using
TTL. Then you had to transfer that to a collection of transistors. Laid
out by hand using tape and a sharp knife.

That took a lot of time and because of the costs and slow turn around
from fabrication there would be a premium on getting it right the first
time. So go with what you know.

I will have to dig out the BYTE magazine article on the design of the
6809. That happened a few years later with slightly better design tools.

It looks like I will not have to dig into the paper archives:
https://tlindner.macmess.org/?page_id=119

--
http://davesrocketworks.com
David Schultz

On Sunday, August 15, 2021 at 1:15:38 AM UTC-5, Quadibloc wrote:
> On Friday, July 23, 2021 at 6:00:15 AM UTC-6, Quadibloc wrote:
> > On Friday, July 23, 2021 at 4:59:30 AM UTC-6, Thomas Koenig wrote:
> > > Another direction for retro-architectures... I've been looking
> > > at the 6502 a bit, and it really is quite an interesting design.
> > > Squeezing the functionality of a CPU into ~3500 transistors (plus
> > > ~1000 transistors used as resistors) was quite an achievement.
> > Indeed.
>
> > However, even the 6502, let alone the 6800 or the 8080, seemed
> > to me to have very complicated instruction sets compared to the
> > PDP-8.
>
> > But interestingly enough, the 12-bit SDS 92 had an instruction set
> > that in many ways resembled those of the early 8-bit micros. (A
> > manual describing its instruction set is, of course, on Bitsavers.)
>
> Given that the PDP-8 was a very successful minicomputer, while
> the SDS 92, even though it was the first commercially available
> computer made from monolithic integrated circuits, is merely an
> obscure historical footnote:
>
> *why* were the first microprocessors designed with such
> complicated instruction sets, if they could have used fewer
> transistors with a simpler design?
<
They were designed to use every available bus cycle and developed
instructions sets to accomplish same.
<
As to 6502, its ISA is a simplified and slightly altered 6800.
>
> John Savard