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If A = B and B = C, then A = C, except where void or prohibited by law. -- Roy Santoro

devel / comp.arch.fpga / PLL dynamic phase shift

PLL dynamic phase shift

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https://www.novabbs.com/devel/article-flat.php?id=194&group=comp.arch.fpga#194

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Subject: PLL dynamic phase shift
From: feiph...@gmail.com (promach)
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by: promach - Sun, 1 Aug 2021 17:02 UTC

Why ck_dynamic is having period of 0.822ns when it is stated to be of 333MHz frequency?

https://i.imgur.com/Rr1jS8Q.png

https://i.imgur.com/jgfvxk6.png