On 13/03/2022 11:08, Tom Gardner wrote:
> On 12/03/22 14:42, David Brown wrote:
>> On 11/03/2022 13:38, Michael S wrote:
>>> On Friday, March 11, 2022 at 2:27:57 PM UTC+2, Michael S wrote:
>>>> Not being an expert of English English or of American English or of
>>>> any other English variation...
>>>> In this particular case I'd use 'which' rather than 'that'. Because
>>>> I don't like a look of the same word 'that' appearing twice just two
>>>> words apart. In different meanings, which probably makes things worse.
>>>
>>> Thinking about it, not "probably". different meanings certainly make
>>> things worse.
>>> Repeated  (recurring?)  'that' in the same meaning, like that, is o.k
>>> with me:
>>>
>> Here's a grammar challenge for you regarding repeated words - can you
>> punctuate the following?
>>
>> Peter where John had had had had had had had had had had had the
>> examiners approval
>>
>>
>> (Hint - it's not just one sentence.)
>>
>
> These are one sentence, apparently :)

I'd like to see that. I only know of two answers, which are minor
variations of each other, and it requires two sentences. But there may
be more.

> I've seen code that is as
> difficult to parse and understand as these :(
>

Have you tried Forth? It can be as bad, except it is written backwards.
And you can redefine the meaning of "had" in the middle!

(Of course you can write clear Forth too. But there is no Obfuscated
Forth Code Contest - I think mostly because it would upset the IOCCC
folks too much as they get completely outclassed!)

> "In Middle English, there was no difference between & and and, and
> and and &, and this situation persists in the present day."
>

Well, the ligature & is just a contraction of "et", so that's not
surprising.

> "Wouldn't the sentence 'I want to put two hyphens between the words
> Pig and And, and And and Whistle in my Pig-And-Whistle sign' have
> been clearer if quotation marks had been placed before Pig, and
> between Pig and and, and and and And, and And and and, and and and
> And, and And and and, and and and Whistle, and after Whistle?"

Stephen Fuld wrote:
> On 3/12/2022 4:09 AM, Terje Mathisen wrote:
>> George Neuner wrote:
>>> On Wed, 9 Mar 2022 11:36:53 -0000 (UTC), Thomas Koenig
>>> <tkoenig@netcologne.de> wrote:
>>>
>>>> If you want, you can have a softcore for your CPU and define special
>>>> instructions for your special needs.  I don't think it is easy
>>>> to modify the FPGA programming on the fly.
>>>
>>> With the right architecture, it can be relatively easy.
>>>
>
> snip
>
>>> Unfortunately, it never turned into a commercial product ... CPU
>>> speeds were rapidly improving and it was thought that the proprietary
>>> accelerator - even if it could be sold as a separate product - would
>>> not remain cost effective for long.  But for a couple of years it was
>>> fun to work on (and with).
>>
>> We discussed several of these approaches at the time, here on c.arch,
>> every single time the main problem was effectively Moore's Law: Each
>> time somebody had developed another FPGA accelerator board for
>> function X, I (or anyone else like me) could take the same algorithm,
>> more or less, turn it into hand-optimized x86 asm, and either
>> immediately or within two years, that SW would be just as fast as the
>> FPGA and far cheaper.
>
> Agreed.  However, with the current situation of CPU not getting (much)
> faster, and, of course larger capacity FPGAs, I wonder if that is still
> true.  Or does using graphics chips for this provide similar functionality

You are correct, GPGPU has probably absorbed most of the potential
market. As soon as you find a significant problem area with need for
that final power of 10 performance/watt (or $), like AI training or
crypto mining, then VLSI swoops in. FPGA remains a borderline tech, for
when you have a medium-large market that requires a stable platform with
ultimate programmability.

The only sizeable market like that in my personal experience is for cell
tower base stations, where the FPGA provides software defined radio
flexible enough to upgrade thousands of base stations without having to
actually visit them.
>
>> Programming-wise it sounds sort of similar to the Cell Broadband
>> Engine of the Playstation: Could deliver excellent results but
>> required hardcore programming support from a quite small pool of
>> available/competent programmers.
>
> Yes.  But perhaps it could be that this pool of programmers provides a
> "library" of low level primitives, that mere mortals can use fazirly
> easily.
>
> I don't know if any of this is real - just wondering.
>
Ditto, but until proven otherwise I'll assume that FPGA remains a
relatively small market.

Make it standard on a mainstream CPU and I would reconsider! :-)

Terje

--
- <Terje.Mathisen at tmsw.no>
"almost all programming can be viewed as an exercise in caching"

On 13/03/22 11:03, David Brown wrote:
> On 13/03/2022 11:08, Tom Gardner wrote:
>> On 12/03/22 14:42, David Brown wrote:
>>> On 11/03/2022 13:38, Michael S wrote:
>>>> On Friday, March 11, 2022 at 2:27:57 PM UTC+2, Michael S wrote:
>>>>> Not being an expert of English English or of American English or of
>>>>> any other English variation...
>>>>> In this particular case I'd use 'which' rather than 'that'. Because
>>>>> I don't like a look of the same word 'that' appearing twice just two
>>>>> words apart. In different meanings, which probably makes things worse.
>>>>
>>>> Thinking about it, not "probably". different meanings certainly make
>>>> things worse.
>>>> Repeated  (recurring?)  'that' in the same meaning, like that, is o.k
>>>> with me:
>>>>
>>> Here's a grammar challenge for you regarding repeated words - can you
>>> punctuate the following?
>>>
>>> Peter where John had had had had had had had had had had had the
>>> examiners approval
>>>
>>>
>>> (Hint - it's not just one sentence.)
>>>
>>
>> These are one sentence, apparently :)
>
> I'd like to see that. I only know of two answers, which are minor
> variations of each other, and it requires two sentences. But there may
> be more.
>
>> I've seen code that is as
>> difficult to parse and understand as these :(
>>
>
> Have you tried Forth? It can be as bad, except it is written backwards.

I like the RPN mindset: gather everything you need and then
operate on it.

Apocryphal story about simultaneous translation of German
into English... The translator is silent and getting ever
more agitated until they finally say "Professor, the verb
/please/".

> And you can redefine the meaning of "had" in the middle!

Yes, that is, um, entertaining.

Almost as entertaining as Java, where you can redefine the
value of Integer(1) at runtime. The trick is that small
values of Integer are predefined/cached, and you can use
reflection to fiddle with it.

Too many developers think reflection is "cute", and try to
employ it where it isn't necessary.

BGB wrote:
> On 3/11/2022 12:37 PM, Ivan Godard wrote:
>> Even long-standing language notion can die. I use both the conditional
>> - "if I were a rich man..." instead of "if I was a rich man...", and
>> distinguish "shall" from "will" - simple future instead of
>> intentional. Both the conditional and and use of shall have largely
>> disappeared in my lifetime.
>>
>> But then, I've sometimes been told I have a somewhat antiquated style :-)
>>
>>
>
> Possibly similar in my case, though as can be noted, I am autistic, so
> my interpretation and usage of language semantics may be potentially
> non-standard even in areas where there would seem to be agreement.
>
> Also, half wonders if that example were intended to be a "Fiddler on the
> Roof" reference, or if this merely happened by chance...

Possibly, but "If I were a rich man" is almost the canonical example of
where you can use "I were", i.e. the singer is implying that this is of
course pretty much impossible.

Terje

--
- <Terje.Mathisen at tmsw.no>
"almost all programming can be viewed as an exercise in caching"

On 13/03/2022 13:06, Terje Mathisen wrote:
> BGB wrote:
>> On 3/11/2022 12:37 PM, Ivan Godard wrote:
>>> Even long-standing language notion can die. I use both the
>>> conditional - "if I were a rich man..." instead of "if I was a rich
>>> man...", and distinguish "shall" from "will" - simple future instead
>>> of intentional. Both the conditional and and use of shall have
>>> largely disappeared in my lifetime.
>>>
>>> But then, I've sometimes been told I have a somewhat antiquated style
>>> :-)
>>>
>>>
>>
>> Possibly similar in my case, though as can be noted, I am autistic, so
>> my interpretation and usage of language semantics may be potentially
>> non-standard even in areas where there would seem to be agreement.
>>
>> Also, half wonders if that example were intended to be a "Fiddler on
>> the Roof" reference, or if this merely happened by chance...
>
> Possibly, but "If I were a rich man" is almost the canonical example of
> where you can use "I were", i.e. the singer is implying that this is of
> course pretty much impossible.
>

I think the most common use would be something like "I'd go for it, if I
were you".

I'm not sure that "If I were" necessarily implies "pretty much
impossible" - I think it just means you have no expectation of the event
happening. "If I were to get a new house, I'd look for somewhere with a
big garden" - it's certainly not impossible, but you are not planning on
moving at the moment.

On 13/03/2022 13:05, Tom Gardner wrote:
> On 13/03/22 11:03, David Brown wrote:
>> On 13/03/2022 11:08, Tom Gardner wrote:
>>> On 12/03/22 14:42, David Brown wrote:
>>>> On 11/03/2022 13:38, Michael S wrote:
>>>>> On Friday, March 11, 2022 at 2:27:57 PM UTC+2, Michael S wrote:
>>>>>> Not being an expert of English English or of American English or of
>>>>>> any other English variation...
>>>>>> In this particular case I'd use 'which' rather than 'that'. Because
>>>>>> I don't like a look of the same word 'that' appearing twice just two
>>>>>> words apart. In different meanings, which probably makes things
>>>>>> worse.
>>>>>
>>>>> Thinking about it, not "probably". different meanings certainly make
>>>>> things worse.
>>>>> Repeated  (recurring?)  'that' in the same meaning, like that, is o.k
>>>>> with me:
>>>>>
>>>> Here's a grammar challenge for you regarding repeated words - can you
>>>> punctuate the following?
>>>>
>>>> Peter where John had had had had had had had had had had had the
>>>> examiners approval
>>>>
>>>>
>>>> (Hint - it's not just one sentence.)
>>>>
>>>
>>> These are one sentence, apparently :)
>>
>> I'd like to see that.  I only know of two answers, which are minor
>> variations of each other, and it requires two sentences.  But there may
>> be more.
>>
>>> I've seen code that is as
>>> difficult to parse and understand as these :(
>>>
>>
>> Have you tried Forth?  It can be as bad, except it is written backwards.
>
> I like the RPN mindset: gather everything you need and then
> operate on it.

It does make sense in terms of the order things actually work. But it
doesn't order we are used to from English - in the imperative, we use
verb, noun ordering. A recipe usually says "Beat the eggs, then mix in
the sugar", not "Eggs beat sugar mix".

Most of all, I think it is a matter of practice and familiarity.

>
> Apocryphal story about simultaneous translation of German
> into English... The translator is silent and getting ever
> more agitated until they finally say "Professor, the verb
> /please/".
>
>
>>   And you can redefine the meaning of "had" in the middle!
>
> Yes, that is, um, entertaining.
>
> Almost as entertaining as Java, where you can redefine the
> value of Integer(1) at runtime. The trick is that small
> values of Integer are predefined/cached, and you can use
> reflection to fiddle with it.
>

But is that defined behaviour in Java, or cheating? In Forth, you can
redefine 1 /legally/ in the language:

1 1 + .

Result: 2

: 1 2 ; 1 1 + .

Result: 4

> Too many developers think reflection is "cute", and try to
> employ it where it isn't necessary.

And too many languages don't have it when it would be useful. (I wish
the C++ standards committee would stop beating about the bush and add it
to the language. Sure, it will open new ways to write confusing code,
but C++ has so many of these it won't matter. And it would allow many
new ways to write simpler and clearer code.)

On 2022-03-13 14:16, David Brown wrote:
> On 13/03/2022 13:06, Terje Mathisen wrote:
>> BGB wrote:
>>> On 3/11/2022 12:37 PM, Ivan Godard wrote:
>>>> Even long-standing language notion can die. I use both the
>>>> conditional - "if I were a rich man..." instead of "if I was a rich
>>>> man...", and distinguish "shall" from "will" - simple future instead
>>>> of intentional. Both the conditional and and use of shall have
>>>> largely disappeared in my lifetime.
>>>>
>>>> But then, I've sometimes been told I have a somewhat antiquated style
>>>> :-)
>>>>
>>>>
>>>
>>> Possibly similar in my case, though as can be noted, I am autistic, so
>>> my interpretation and usage of language semantics may be potentially
>>> non-standard even in areas where there would seem to be agreement.
>>>
>>> Also, half wonders if that example were intended to be a "Fiddler on
>>> the Roof" reference, or if this merely happened by chance...
>>
>> Possibly, but "If I were a rich man" is almost the canonical example of
>> where you can use "I were", i.e. the singer is implying that this is of
>> course pretty much impossible.
>>
>
> I think the most common use would be something like "I'd go for it, if I
> were you".

"If I Were You" is the title of a novel by P.G. Wodehouse. One of his
best, IMO.

> > Peter where John had had had had had had had had had had had the
> > examiners approval

The moment when I realized I was going to have to use a Prolog-ish
engine to parse English:

Is the frog on the log?
Is the frog on the log red?

Andy Valencia
Home page: https://www.vsta.org/andy/
To contact me: https://www.vsta.org/contact/andy.html

On 2022-03-13 14:26, David Brown wrote:

> In Forth, you can redefine 1 /legally/ in the language:
>
> 1 1 + .
>
> Result: 2
>
> : 1 2 ; 1 1 + .
>
> Result: 4

I had some interest in Forth long ago, when I was doing astronomy and
Forth was fairly prominent in that field, for the small embedded systems
we had then. I finally lost interest after encountering a Forth program,
in an astronomical context, where the token 1950.0 was defined as a
subroutine "word" that converted stellar coordinates from the current
coordinate system to the system defined for the standard epoch year 1950.

Well, that Forth had no floating-point literals, so it was not really
ambiguous...

On 13/03/2022 15:28, Niklas Holsti wrote:
> On 2022-03-13 14:16, David Brown wrote:
>> On 13/03/2022 13:06, Terje Mathisen wrote:
>>> BGB wrote:
>>>> On 3/11/2022 12:37 PM, Ivan Godard wrote:
>>>>> Even long-standing language notion can die. I use both the
>>>>> conditional - "if I were a rich man..." instead of "if I was a rich
>>>>> man...", and distinguish "shall" from "will" - simple future instead
>>>>> of intentional. Both the conditional and and use of shall have
>>>>> largely disappeared in my lifetime.
>>>>>
>>>>> But then, I've sometimes been told I have a somewhat antiquated style
>>>>> :-)
>>>>>
>>>>>
>>>>
>>>> Possibly similar in my case, though as can be noted, I am autistic, so
>>>> my interpretation and usage of language semantics may be potentially
>>>> non-standard even in areas where there would seem to be agreement.
>>>>
>>>> Also, half wonders if that example were intended to be a "Fiddler on
>>>> the Roof" reference, or if this merely happened by chance...
>>>
>>> Possibly, but "If I were a rich man" is almost the canonical example of
>>> where you can use "I were", i.e. the singer is implying that this is of
>>> course pretty much impossible.
>>>
>>
>> I think the most common use would be something like "I'd go for it, if I
>> were you".
>
>
> "If I Were You" is the title of a novel by P.G. Wodehouse. One of his
> best, IMO.

I must admit I have never actually read a Wodehouse novel. There are
too many authors, and too few hours to read all that is worth reading.
I expect I'd enjoy his books.

On 13/03/2022 15:43, Niklas Holsti wrote:
> On 2022-03-13 14:26, David Brown wrote:
>
>
>> In Forth, you can redefine 1 /legally/ in the language:
>>
>>     1 1 + .
>>
>> Result: 2
>>
>>     : 1 2 ; 1 1 + .
>>
>> Result: 4
>
>
> I had some interest in Forth long ago, when I was doing astronomy and
> Forth was fairly prominent in that field, for the small embedded systems
> we had then. I finally lost interest after encountering a Forth program,
> in an astronomical context, where the token 1950.0 was defined as a
> subroutine "word" that converted stellar coordinates from the current
> coordinate system to the system defined for the standard epoch year 1950.
>
> Well, that Forth had no floating-point literals, so it was not really
> ambiguous...

It is a language with enormous flexibility. While I've had very little
use of it myself, I've read about several impressive Forth systems over
the years. I've heard of Forth systems where the assembly for the
microcontroller was so well integrated that there is no real boundary
between "high level" Forth and assembly. I've read about soft
processors written in Forth (from which synthesizable Verilog or VHDL is
generated) where you can have a single system and choose where to draw
the line between hardware and software according to your choice of
balance between performance and cost.

But Forth code can also be written in a way that makes binary files look
self-documenting. And all the flexibility severely limits the aid you
can get from tools. The real power of a programming language, according
to some, is in what the language /prevents/ you from doing, not what it
allows you to do. And Forth prevents very little.

On Sunday, March 13, 2022 at 2:47:33 AM UTC+2, JimBrakefield wrote:
> On Saturday, March 12, 2022 at 2:07:10 PM UTC-6, Michael S wrote:
> > On Saturday, March 12, 2022 at 9:12:24 PM UTC+2, JimBrakefield wrote:
> > > On Saturday, March 12, 2022 at 11:38:27 AM UTC-6, Anton Ertl wrote:
> > > > Stephen Fuld <sf...@alumni.cmu.edu.invalid> writes:
> > > > > However, with the current situation of CPU not getting (much)
> > > > >faster, and, of course larger capacity FPGAs, I wonder if that is still
> > > > >true.
> > > > What is still true is that softcores are still a factor of 10 (typical
> > > > numbers I remember are 250MHz for fast-clocked softcores) slower than
> > > > custom-designed silicon CPUs, and I guess the same is true for other
> > > > logic functions implemented in FPGAs. So the niche for FPGA stuff
> > > > seems quite small to me: Functions that are not implemented in custom
> > > > silicon, take many steps in software, yet can be implemented with few
> > > > steps in hardware (and FPGAs); i.e., something like new crypto
> > > > algorithms that have not found their way into hardware accelerators
> > > > yet.
> > > >
> > > > At least as far as performance is relevant; a larger niche for FPGAs
> > > > is helper chips for boards that do not have enough volume for
> > > > full-custom chips.
> > > >
> > > > At least that's how the situation looks to me.
> > > >
> > > > - anton
> > > > --
> > > > 'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'
> > > > Mitch Alsup, <c17fcd89-f024-40e7...@googlegroups.com>
> > > If power consumption is the metric, FPGAs have several advantages:
> > >
> > > 1) Power consumption is proportional to computation as unused FPGA fabric has low power consumption. FPGAs are designed to have low static power?
> > It depends on what you consider low.
> > Certainly, no FPGA is going to consume 1mW when idle.
> > Big FPGA is not going to consume 100mW either. But 1-2 Wats are possible, except in certain unfortunate families, like Arria-2, luckily not likely to be used for new projects.
> > > 2) FPGAs tend to require less memory traffic. Memory data flow is more efficient, e.g. fewer loads and stores required. And memories are scaled in size to their usage.
> > > 3) Much computation is done outside of hard or soft cores and requires no instruction pipeline. In many cases a simple state machine suffices.
> > > 4) Moore's law still applies to FPGAs. E.g., they continue to get faster and more power efficient.
> > More efficient - yes.
> > Bigger - yes. But the biggest FPGA offerings are already MCM (tiles) under the hood.
> > Faster - I am not sure. Quite possibly we will not see anything faster than Stratix-10 (available for ~4 years) for quite some time.
> > I mean, from the Big 2. I don't follow Achronix and similar exotic players.
> > > 5) Single chip hybrid hard core(s) + FPGA fabric are readily available in many different combinations.
> > > 6) There is little internal fragmentation. Data sizes (and FPGA resources) are set to data requirements, not the register size.
>
> |> Quite possibly we will not see anything faster than Stratix-10 (available for ~4 years) for quite some time.
> I'm showing Stratix-10 at the "IA" 14nm node and Versal at the "AX" 7nm node.

Currently, I have no access to version of Vivado that supports Versal. So, can't compare vs S10.

>Going to smaller process nodes should reduce wire delay if nothing else.

No, wire (RC) delay is a function of shape of the wire and material. It does not depend on the absolute dimensions.
Every gain that a shrink gives in C component is taken back by R component.
As to next shrinks, situation is going to become worse, because the width and depth of finer layers of wires is approaching Mean Free Path of conduction electrons in copper. It means that effective conductivity of copper wires is already lower than in bulk copper and the disparity will only grow.
That's sought to be one of the reasons (the other one being electormigration) of Intel recently experimenting with Cobalt wires. I don't know all details but it seems that their experiments encountered serious problems. However even if they were 100% successful, thin cobalt will never be as good conductor as bulk copper which means that in the future inner wires are going to be either very much slower (if cobalt does not work) or much slower (if it does).

> Further process nodes will take place slowly?

If Intel and Samsung continue to compete against TSMC then yes, new nodes will arrive slowly.
But if both of them throw a towel, like the rest of the industry did several years ago, then TSMC
will have all economical reasons to move not just slowly, but extremely slowly.

> |>Big FPGA is not going to consume 100mW either.
> Agreed, compared to 10 watts of an idle x86-64 however?

Intel and AMD Ultramobile x64 SOCs are well under 1W when in C4 or lower modes. Probably around 1W in C3.
And Apple M1 is significantly lower yet.

> Of course if the ASIC is ten times faster, guess the power contest is ~tied.

On 3/13/2022 7:06 AM, Terje Mathisen wrote:
> BGB wrote:
>> On 3/11/2022 12:37 PM, Ivan Godard wrote:
>>> Even long-standing language notion can die. I use both the
>>> conditional - "if I were a rich man..." instead of "if I was a rich
>>> man...", and distinguish "shall" from "will" - simple future instead
>>> of intentional. Both the conditional and and use of shall have
>>> largely disappeared in my lifetime.
>>>
>>> But then, I've sometimes been told I have a somewhat antiquated style
>>> :-)
>>>
>>>
>>
>> Possibly similar in my case, though as can be noted, I am autistic, so
>> my interpretation and usage of language semantics may be potentially
>> non-standard even in areas where there would seem to be agreement.
>>
>> Also, half wonders if that example were intended to be a "Fiddler on
>> the Roof" reference, or if this merely happened by chance...
>
> Possibly, but "If I were a rich man" is almost the canonical example of
> where you can use "I were", i.e. the singer is implying that this is of
> course pretty much impossible.
>

I guess it being a reference is pretty much confirmed at this point.
I wasn't previously aware that this play / movie was quite so popular.

I don't think it implies though that it was impossible, but rather that
it is hypothetical (eg, not part of the planned / expected future). This
would be contrast more with, say, "when I am", which would imply a
future that is expected to happen.

Though, in this context, I would be less inclined to the latter, as life
tends to be on the thin edge of "everything going to crap", and best one
can do is try to buffer against it.

Like, while one can't be rich, they can at least try to limit expenses
enough that they are not totally broke (trying to limit spending mostly
to things that are either "technically necessary" or have a reasonable
probability of giving a return-on-investment).

Say, for example, one has some money burning a hole in their pocket, do
they buy:
A new / semi-fancy car;
Or, a Haas machining center.

One of these things will (merely) cost money, the other can potentially
be used to make parts, pay for itself, and maybe turn a profit. May be
potentially still a boondoggle, and can't ride down the street in it,
but it can be used for making parts (more effectively than a converted
manual mill with a CNC kit), and would be bigger and more capable than a
lot of the Tormach machines (sorta works, intermediate cost, but suffer
from being limited to fairly small tooling).

Or, one could buy neither, the money remains for another day (well,
unless one spends it all on overpriced food products or similar, or a
small mountain of Gundam models, ...).

Side note: No, I don't personally have enough money to buy either of
these things at present.

....

On 3/13/2022 12:58 PM, Michael S wrote:
> On Sunday, March 13, 2022 at 2:47:33 AM UTC+2, JimBrakefield wrote:
>> On Saturday, March 12, 2022 at 2:07:10 PM UTC-6, Michael S wrote:
>>> On Saturday, March 12, 2022 at 9:12:24 PM UTC+2, JimBrakefield wrote:
>>>> On Saturday, March 12, 2022 at 11:38:27 AM UTC-6, Anton Ertl wrote:
>>>>> Stephen Fuld <sf...@alumni.cmu.edu.invalid> writes:
>>>>>> However, with the current situation of CPU not getting (much)
>>>>>> faster, and, of course larger capacity FPGAs, I wonder if that is still
>>>>>> true.
>>>>> What is still true is that softcores are still a factor of 10 (typical
>>>>> numbers I remember are 250MHz for fast-clocked softcores) slower than
>>>>> custom-designed silicon CPUs, and I guess the same is true for other
>>>>> logic functions implemented in FPGAs. So the niche for FPGA stuff
>>>>> seems quite small to me: Functions that are not implemented in custom
>>>>> silicon, take many steps in software, yet can be implemented with few
>>>>> steps in hardware (and FPGAs); i.e., something like new crypto
>>>>> algorithms that have not found their way into hardware accelerators
>>>>> yet.
>>>>>
>>>>> At least as far as performance is relevant; a larger niche for FPGAs
>>>>> is helper chips for boards that do not have enough volume for
>>>>> full-custom chips.
>>>>>
>>>>> At least that's how the situation looks to me.
>>>>>
>>>>> - anton
>>>>> --
>>>>> 'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'
>>>>> Mitch Alsup, <c17fcd89-f024-40e7...@googlegroups.com>
>>>> If power consumption is the metric, FPGAs have several advantages:
>>>>
>>>> 1) Power consumption is proportional to computation as unused FPGA fabric has low power consumption. FPGAs are designed to have low static power?
>>> It depends on what you consider low.
>>> Certainly, no FPGA is going to consume 1mW when idle.
>>> Big FPGA is not going to consume 100mW either. But 1-2 Wats are possible, except in certain unfortunate families, like Arria-2, luckily not likely to be used for new projects.
>>>> 2) FPGAs tend to require less memory traffic. Memory data flow is more efficient, e.g. fewer loads and stores required. And memories are scaled in size to their usage.
>>>> 3) Much computation is done outside of hard or soft cores and requires no instruction pipeline. In many cases a simple state machine suffices.
>>>> 4) Moore's law still applies to FPGAs. E.g., they continue to get faster and more power efficient.
>>> More efficient - yes.
>>> Bigger - yes. But the biggest FPGA offerings are already MCM (tiles) under the hood.
>>> Faster - I am not sure. Quite possibly we will not see anything faster than Stratix-10 (available for ~4 years) for quite some time.
>>> I mean, from the Big 2. I don't follow Achronix and similar exotic players.
>>>> 5) Single chip hybrid hard core(s) + FPGA fabric are readily available in many different combinations.
>>>> 6) There is little internal fragmentation. Data sizes (and FPGA resources) are set to data requirements, not the register size.
>>
>> |> Quite possibly we will not see anything faster than Stratix-10 (available for ~4 years) for quite some time.
>> I'm showing Stratix-10 at the "IA" 14nm node and Versal at the "AX" 7nm node.
>
> Currently, I have no access to version of Vivado that supports Versal. So, can't compare vs S10.
>

The Vivado I have does Spartan, Artix, and some of the Kintex line.
The higher end of the chips that it supports though, are already out of
my price range...

>> Going to smaller process nodes should reduce wire delay if nothing else.
>
> No, wire (RC) delay is a function of shape of the wire and material. It does not depend on the absolute dimensions.
> Every gain that a shrink gives in C component is taken back by R component.
> As to next shrinks, situation is going to become worse, because the width and depth of finer layers of wires is approaching Mean Free Path of conduction electrons in copper. It means that effective conductivity of copper wires is already lower than in bulk copper and the disparity will only grow.
> That's sought to be one of the reasons (the other one being electormigration) of Intel recently experimenting with Cobalt wires. I don't know all details but it seems that their experiments encountered serious problems. However even if they were 100% successful, thin cobalt will never be as good conductor as bulk copper which means that in the future inner wires are going to be either very much slower (if cobalt does not work) or much slower (if it does).
>
>> Further process nodes will take place slowly?
>
> If Intel and Samsung continue to compete against TSMC then yes, new nodes will arrive slowly.
> But if both of them throw a towel, like the rest of the industry did several years ago, then TSMC
> will have all economical reasons to move not just slowly, but extremely slowly.
>

I suspect the practical limit is rapidly approaching.

Within a few years, new nodes will become impractical, or maybe they
will backtrack slightly, say if an older node happens to be cheaper and
more reliable.

>> |>Big FPGA is not going to consume 100mW either.
>> Agreed, compared to 10 watts of an idle x86-64 however?
>
> Intel and AMD Ultramobile x64 SOCs are well under 1W when in C4 or lower modes. Probably around 1W in C3.
> And Apple M1 is significantly lower yet.
>
>> Of course if the ASIC is ten times faster, guess the power contest is ~tied.

On Sunday, March 13, 2022 at 12:58:22 PM UTC-5, Michael S wrote:
> On Sunday, March 13, 2022 at 2:47:33 AM UTC+2, JimBrakefield wrote:
> > On Saturday, March 12, 2022 at 2:07:10 PM UTC-6, Michael S wrote:
> > > On Saturday, March 12, 2022 at 9:12:24 PM UTC+2, JimBrakefield wrote:
> > > > On Saturday, March 12, 2022 at 11:38:27 AM UTC-6, Anton Ertl wrote:
> > > > > Stephen Fuld <sf...@alumni.cmu.edu.invalid> writes:
> > > > > > However, with the current situation of CPU not getting (much)
> > > > > >faster, and, of course larger capacity FPGAs, I wonder if that is still
> > > > > >true.
> > > > > What is still true is that softcores are still a factor of 10 (typical
> > > > > numbers I remember are 250MHz for fast-clocked softcores) slower than
> > > > > custom-designed silicon CPUs, and I guess the same is true for other
> > > > > logic functions implemented in FPGAs. So the niche for FPGA stuff
> > > > > seems quite small to me: Functions that are not implemented in custom
> > > > > silicon, take many steps in software, yet can be implemented with few
> > > > > steps in hardware (and FPGAs); i.e., something like new crypto
> > > > > algorithms that have not found their way into hardware accelerators
> > > > > yet.
> > > > >
> > > > > At least as far as performance is relevant; a larger niche for FPGAs
> > > > > is helper chips for boards that do not have enough volume for
> > > > > full-custom chips.
> > > > >
> > > > > At least that's how the situation looks to me.
> > > > >
> > > > > - anton
> > > > > --
> > > > > 'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'
> > > > > Mitch Alsup, <c17fcd89-f024-40e7...@googlegroups.com>
> > > > If power consumption is the metric, FPGAs have several advantages:
> > > >
> > > > 1) Power consumption is proportional to computation as unused FPGA fabric has low power consumption. FPGAs are designed to have low static power?
> > > It depends on what you consider low.
> > > Certainly, no FPGA is going to consume 1mW when idle.
> > > Big FPGA is not going to consume 100mW either. But 1-2 Wats are possible, except in certain unfortunate families, like Arria-2, luckily not likely to be used for new projects.
> > > > 2) FPGAs tend to require less memory traffic. Memory data flow is more efficient, e.g. fewer loads and stores required. And memories are scaled in size to their usage.
> > > > 3) Much computation is done outside of hard or soft cores and requires no instruction pipeline. In many cases a simple state machine suffices.
> > > > 4) Moore's law still applies to FPGAs. E.g., they continue to get faster and more power efficient.
> > > More efficient - yes.
> > > Bigger - yes. But the biggest FPGA offerings are already MCM (tiles) under the hood.
> > > Faster - I am not sure. Quite possibly we will not see anything faster than Stratix-10 (available for ~4 years) for quite some time.
> > > I mean, from the Big 2. I don't follow Achronix and similar exotic players.
> > > > 5) Single chip hybrid hard core(s) + FPGA fabric are readily available in many different combinations.
> > > > 6) There is little internal fragmentation. Data sizes (and FPGA resources) are set to data requirements, not the register size.
> >
> > |> Quite possibly we will not see anything faster than Stratix-10 (available for ~4 years) for quite some time.
> > I'm showing Stratix-10 at the "IA" 14nm node and Versal at the "AX" 7nm node.
>
> Currently, I have no access to version of Vivado that supports Versal. So, can't compare vs S10.
>
> >Going to smaller process nodes should reduce wire delay if nothing else.
>
> No, wire (RC) delay is a function of shape of the wire and material. It does not depend on the absolute dimensions.
> Every gain that a shrink gives in C component is taken back by R component.
<
Every wire is surrounded by barrier metals (a couple of atoms thick),
So every shrink, wires get slower, even though capacitance goes down.
Vias also get slower, somewhat more than proportionately.
So, a wire that stays on one layer only gets a bit slower when shrunk,
whereas a wire that goes up and down the wire hierarchy gets much slower when shrunk.
FPGAs have almost no control over wires going up and down the wire hierarchy.
<
> As to next shrinks, situation is going to become worse, because the width and depth of finer layers of wires is approaching Mean Free Path of conduction electrons in copper. It means that effective conductivity of copper wires is already lower than in bulk copper and the disparity will only grow.
<
It gets even worse when you consider how much current can be put through a wire and
for how long before grain boundaries line up and the wire "breaks".
<
> That's sought to be one of the reasons (the other one being electormigration) of Intel recently experimenting with Cobalt wires. I don't know all details but it seems that their experiments encountered serious problems. However even if they were 100% successful, thin cobalt will never be as good conductor as bulk copper which means that in the future inner wires are going to be either very much slower (if cobalt does not work) or much slower (if it does).
>
> > Further process nodes will take place slowly?
>
> If Intel and Samsung continue to compete against TSMC then yes, new nodes will arrive slowly.
> But if both of them throw a towel, like the rest of the industry did several years ago, then TSMC
> will have all economical reasons to move not just slowly, but extremely slowly.
<
Then what does the world do if China invades Taiwan ??
<
Every 'bigger than person' weapon system is already dependent on computer chips.
>
> > |>Big FPGA is not going to consume 100mW either.
> > Agreed, compared to 10 watts of an idle x86-64 however?
>
> Intel and AMD Ultramobile x64 SOCs are well under 1W when in C4 or lower modes. Probably around 1W in C3.
> And Apple M1 is significantly lower yet.
>
> > Of course if the ASIC is ten times faster, guess the power contest is ~tied.

On Sunday, March 13, 2022 at 1:41:59 PM UTC-5, BGB wrote:
> On 3/13/2022 7:06 AM, Terje Mathisen wrote:
> > BGB wrote:
> >> On 3/11/2022 12:37 PM, Ivan Godard wrote:
> >>> Even long-standing language notion can die. I use both the
> >>> conditional - "if I were a rich man..." instead of "if I was a rich
> >>> man...", and distinguish "shall" from "will" - simple future instead
> >>> of intentional. Both the conditional and and use of shall have
> >>> largely disappeared in my lifetime.
> >>>
> >>> But then, I've sometimes been told I have a somewhat antiquated style
> >>> :-)
> >>>
> >>>
> >>
> >> Possibly similar in my case, though as can be noted, I am autistic, so
> >> my interpretation and usage of language semantics may be potentially
> >> non-standard even in areas where there would seem to be agreement.
> >>
> >> Also, half wonders if that example were intended to be a "Fiddler on
> >> the Roof" reference, or if this merely happened by chance...
> >
> > Possibly, but "If I were a rich man" is almost the canonical example of
> > where you can use "I were", i.e. the singer is implying that this is of
> > course pretty much impossible.
> >
> I guess it being a reference is pretty much confirmed at this point.
> I wasn't previously aware that this play / movie was quite so popular.
>
>
> I don't think it implies though that it was impossible, but rather that
> it is hypothetical (eg, not part of the planned / expected future). This
> would be contrast more with, say, "when I am", which would imply a
> future that is expected to happen.
>
>
> Though, in this context, I would be less inclined to the latter, as life
> tends to be on the thin edge of "everything going to crap", and best one
> can do is try to buffer against it.
>
> Like, while one can't be rich, they can at least try to limit expenses
> enough that they are not totally broke (trying to limit spending mostly
> to things that are either "technically necessary" or have a reasonable
> probability of giving a return-on-investment).
<
Apparently about 50% of the people/families in this country are failing
in this metric with $0 savings, and $0 net-worth--but they all have cell
phones.....
>
>
> Say, for example, one has some money burning a hole in their pocket, do
> they buy:
> A new / semi-fancy car;
> Or, a Haas machining center.
>
> One of these things will (merely) cost money, the other can potentially
> be used to make parts, pay for itself, and maybe turn a profit. May be
> potentially still a boondoggle, and can't ride down the street in it,
> but it can be used for making parts (more effectively than a converted
> manual mill with a CNC kit), and would be bigger and more capable than a
> lot of the Tormach machines (sorta works, intermediate cost, but suffer
> from being limited to fairly small tooling).
>
> Or, one could buy neither, the money remains for another day (well,
> unless one spends it all on overpriced food products or similar, or a
> small mountain of Gundam models, ...).
>
>
> Side note: No, I don't personally have enough money to buy either of
> these things at present.
>
> ...

On 3/13/2022 3:20 PM, MitchAlsup wrote:
> On Sunday, March 13, 2022 at 1:41:59 PM UTC-5, BGB wrote:
>> On 3/13/2022 7:06 AM, Terje Mathisen wrote:
>>> BGB wrote:
>>>> On 3/11/2022 12:37 PM, Ivan Godard wrote:
>>>>> Even long-standing language notion can die. I use both the
>>>>> conditional - "if I were a rich man..." instead of "if I was a rich
>>>>> man...", and distinguish "shall" from "will" - simple future instead
>>>>> of intentional. Both the conditional and and use of shall have
>>>>> largely disappeared in my lifetime.
>>>>>
>>>>> But then, I've sometimes been told I have a somewhat antiquated style
>>>>> :-)
>>>>>
>>>>>
>>>>
>>>> Possibly similar in my case, though as can be noted, I am autistic, so
>>>> my interpretation and usage of language semantics may be potentially
>>>> non-standard even in areas where there would seem to be agreement.
>>>>
>>>> Also, half wonders if that example were intended to be a "Fiddler on
>>>> the Roof" reference, or if this merely happened by chance...
>>>
>>> Possibly, but "If I were a rich man" is almost the canonical example of
>>> where you can use "I were", i.e. the singer is implying that this is of
>>> course pretty much impossible.
>>>
>> I guess it being a reference is pretty much confirmed at this point.
>> I wasn't previously aware that this play / movie was quite so popular.
>>
>>
>> I don't think it implies though that it was impossible, but rather that
>> it is hypothetical (eg, not part of the planned / expected future). This
>> would be contrast more with, say, "when I am", which would imply a
>> future that is expected to happen.
>>
>>
>> Though, in this context, I would be less inclined to the latter, as life
>> tends to be on the thin edge of "everything going to crap", and best one
>> can do is try to buffer against it.
>>
>> Like, while one can't be rich, they can at least try to limit expenses
>> enough that they are not totally broke (trying to limit spending mostly
>> to things that are either "technically necessary" or have a reasonable
>> probability of giving a return-on-investment).
> <
> Apparently about 50% of the people/families in this country are failing
> in this metric with $0 savings, and $0 net-worth--but they all have cell
> phones.....

Yeah.

This is a thing...

In my case, I never tried moving out on my own, partly because I didn't
have enough money built up, and didn't feel my job situation was stable
enough, so I felt trying to do so would (most likely) lead to ruin.

As is, not going to "move out" if I would just end up burning through
all my money in a few months or so. Would prefer not to end up living on
the street...

But, I guess many people couldn't do this either, if their home
situation wasn't ideal (say, parents who either can't afford this, or
were unwilling to let them stay any longer).

Can't seem to get a job either, but some of my relatives are working on
getting a machine shop set up, with the idea that I could machine stuff
there and probably get some money making contracted parts (and hopefully
pay off the cost of setting up the shop).

Some of the stuff they are buying for this is well outside the range of
stuff I could afford to buy on my own (with what money I currently have).

Though, the theory goes, if one has a proper machine shop, parts to
make, ..., then they can in theory make up for the cost of the machining
center and tooling.

This is given, granted, that there is no real obvious way to make any
income off my current projects.

....

>>
>>
>> Say, for example, one has some money burning a hole in their pocket, do
>> they buy:
>> A new / semi-fancy car;
>> Or, a Haas machining center.
>>
>> One of these things will (merely) cost money, the other can potentially
>> be used to make parts, pay for itself, and maybe turn a profit. May be
>> potentially still a boondoggle, and can't ride down the street in it,
>> but it can be used for making parts (more effectively than a converted
>> manual mill with a CNC kit), and would be bigger and more capable than a
>> lot of the Tormach machines (sorta works, intermediate cost, but suffer
>> from being limited to fairly small tooling).
>>
>> Or, one could buy neither, the money remains for another day (well,
>> unless one spends it all on overpriced food products or similar, or a
>> small mountain of Gundam models, ...).
>>
>>
>> Side note: No, I don't personally have enough money to buy either of
>> these things at present.
>>
>> ...

Niklas Holsti wrote:
> On 2022-03-13 14:16, David Brown wrote:
>> On 13/03/2022 13:06, Terje Mathisen wrote:
>>> BGB wrote:
>>>> On 3/11/2022 12:37 PM, Ivan Godard wrote:
>>>>> Even long-standing language notion can die. I use both the
>>>>> conditional - "if I were a rich man..." instead of "if I was a rich
>>>>> man...", and distinguish "shall" from "will" - simple future instead
>>>>> of intentional. Both the conditional and and use of shall have
>>>>> largely disappeared in my lifetime.
>>>>>
>>>>> But then, I've sometimes been told I have a somewhat antiquated style
>>>>> :-)
>>>>>
>>>>>
>>>>
>>>> Possibly similar in my case, though as can be noted, I am autistic, so
>>>> my interpretation and usage of language semantics may be potentially
>>>> non-standard even in areas where there would seem to be agreement.
>>>>
>>>> Also, half wonders if that example were intended to be a "Fiddler on
>>>> the Roof" reference, or if this merely happened by chance...
>>>
>>> Possibly, but "If I were a rich man" is almost the canonical example of
>>> where you can use "I were", i.e. the singer is implying that this is of
>>> course pretty much impossible.
>>>
>>
>> I think the most common use would be something like "I'd go for it, if I
>> were you".
>
>
> "If I Were You" is the title of a novel by P.G. Wodehouse. One of his
> best, IMO.

I have probably read that one. I did read every single PGW book in my
(very good!) local library, co-located with my primary school. Those
books plus "The Complete Sherlock Holmes Short Stories" was how I taught
myself English after learning the basics in school.

Terje
--
- <Terje.Mathisen at tmsw.no>
"almost all programming can be viewed as an exercise in caching"

Michael S wrote:
> On Sunday, March 13, 2022 at 2:47:33 AM UTC+2, JimBrakefield wrote:
>> On Saturday, March 12, 2022 at 2:07:10 PM UTC-6, Michael S wrote:
>>> On Saturday, March 12, 2022 at 9:12:24 PM UTC+2, JimBrakefield wrote:
>>>> On Saturday, March 12, 2022 at 11:38:27 AM UTC-6, Anton Ertl wrote:
>>>>> Stephen Fuld <sf...@alumni.cmu.edu.invalid> writes:
>>>>>> However, with the current situation of CPU not getting (much)
>>>>>> faster, and, of course larger capacity FPGAs, I wonder if that is still
>>>>>> true.
>>>>> What is still true is that softcores are still a factor of 10 (typical
>>>>> numbers I remember are 250MHz for fast-clocked softcores) slower than
>>>>> custom-designed silicon CPUs, and I guess the same is true for other
>>>>> logic functions implemented in FPGAs. So the niche for FPGA stuff
>>>>> seems quite small to me: Functions that are not implemented in custom
>>>>> silicon, take many steps in software, yet can be implemented with few
>>>>> steps in hardware (and FPGAs); i.e., something like new crypto
>>>>> algorithms that have not found their way into hardware accelerators
>>>>> yet.
>>>>>
>>>>> At least as far as performance is relevant; a larger niche for FPGAs
>>>>> is helper chips for boards that do not have enough volume for
>>>>> full-custom chips.
>>>>>
>>>>> At least that's how the situation looks to me.
>>>>>
>>>>> - anton
>>>>> --
>>>>> 'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'
>>>>> Mitch Alsup, <c17fcd89-f024-40e7...@googlegroups.com>
>>>> If power consumption is the metric, FPGAs have several advantages:
>>>>
>>>> 1) Power consumption is proportional to computation as unused FPGA fabric has low power consumption. FPGAs are designed to have low static power?
>>> It depends on what you consider low.
>>> Certainly, no FPGA is going to consume 1mW when idle.
>>> Big FPGA is not going to consume 100mW either. But 1-2 Wats are possible, except in certain unfortunate families, like Arria-2, luckily not likely to be used for new projects.
>>>> 2) FPGAs tend to require less memory traffic. Memory data flow is more efficient, e.g. fewer loads and stores required. And memories are scaled in size to their usage.
>>>> 3) Much computation is done outside of hard or soft cores and requires no instruction pipeline. In many cases a simple state machine suffices.
>>>> 4) Moore's law still applies to FPGAs. E.g., they continue to get faster and more power efficient.
>>> More efficient - yes.
>>> Bigger - yes. But the biggest FPGA offerings are already MCM (tiles) under the hood.
>>> Faster - I am not sure. Quite possibly we will not see anything faster than Stratix-10 (available for ~4 years) for quite some time.
>>> I mean, from the Big 2. I don't follow Achronix and similar exotic players.
>>>> 5) Single chip hybrid hard core(s) + FPGA fabric are readily available in many different combinations.
>>>> 6) There is little internal fragmentation. Data sizes (and FPGA resources) are set to data requirements, not the register size.
>>
>> |> Quite possibly we will not see anything faster than Stratix-10 (available for ~4 years) for quite some time.
>> I'm showing Stratix-10 at the "IA" 14nm node and Versal at the "AX" 7nm node.
>
> Currently, I have no access to version of Vivado that supports Versal. So, can't compare vs S10.
>
>> Going to smaller process nodes should reduce wire delay if nothing else.
>
> No, wire (RC) delay is a function of shape of the wire and material. It does not depend on the absolute dimensions.
> Every gain that a shrink gives in C component is taken back by R component.
> As to next shrinks, situation is going to become worse, because the width and depth of finer layers of wires is approaching Mean Free Path of conduction electrons in copper. It means that effective conductivity of copper wires is already lower than in bulk copper and the disparity will only grow.
> That's sought to be one of the reasons (the other one being electormigration) of Intel recently experimenting with Cobalt wires. I don't know all details but it seems that their experiments encountered serious problems. However even if they were 100% successful, thin cobalt will never be as good conductor as bulk copper which means that in the future inner wires are going to be either very much slower (if cobalt does not work) or much slower (if it does).

I thought I read somewhere that back-to-back NOT gates are already much
faster than the wire they would replace?

Terje

--
- <Terje.Mathisen at tmsw.no>
"almost all programming can be viewed as an exercise in caching"

On Sunday, March 13, 2022 at 2:17:41 PM UTC-6, MitchAlsup wrote:

> Then what does the world do if China invades Taiwan ??

As long as they don't invade the Netherlands, the problem will
only be temporary.

John Savard

On Sunday, March 13, 2022 at 11:58:22 AM UTC-6, Michael S wrote:
> On Sunday, March 13, 2022 at 2:47:33 AM UTC+2, JimBrakefield wrote:

> > Further process nodes will take place slowly?

> If Intel and Samsung continue to compete against TSMC then yes, new nodes will arrive slowly.
> But if both of them throw a towel, like the rest of the industry did several years ago, then TSMC
> will have all economical reasons to move not just slowly, but extremely slowly.

But what is the benefit of a new process node?

Now that Dennard scaling is no longer with us, shrinking to a new
process node hasn't meant that microprocessors have gone from
3 GHz to 5 GHz to 6 GHz to 10 GHz and so on and on.

The only advantages of a new process node is that one can put
more cores on a single die, and one's chips use less power.

These are not worthless, but they're not nearly as critical to have.
There are workarounds for not having them, whereas there is _no_
workaround for a lack of raw circuit speed. The workaround for not
having chips that use less power is to find a cheaper source of
electricity, and use an improved cooling solution. The workaround
for not being able to put as much on a single die is to use a multi-chip
module with a fast interconnect.

For example, look at this article:

https://www.nextplatform.com/2022/03/11/pondering-the-cpu-inside-chinas-sunway-oceanlight-supercomputer/

about how China built an exascale supercomputer... from 14nm
chips.

One could go back further - as far back as 45nm - and get 3 GHz speeds
without having to artificially boost the clock rate by going to a design
like that of the Pentium 4 (or the Bulldozer, *or the chips IBM uses in
its System z computers*).

This is _not_ to say, though, that a high clock rate achieved by having
shorter pipeline stages, the Pentium 4 trick, is a bad thing. It's like
having more cores, but with closer coupling, so it is "better" if it is
possible. The reason why it is often _not_ possible is that it tends to
have a higher power density, so cooling often becomes unachievable.

John Savard

On 3/14/2022 6:57 AM, Quadibloc wrote:
> On Sunday, March 13, 2022 at 11:58:22 AM UTC-6, Michael S wrote:
>> On Sunday, March 13, 2022 at 2:47:33 AM UTC+2, JimBrakefield wrote:
>
>>> Further process nodes will take place slowly?
>
>> If Intel and Samsung continue to compete against TSMC then yes, new nodes will arrive slowly.
>> But if both of them throw a towel, like the rest of the industry did several years ago, then TSMC
>> will have all economical reasons to move not just slowly, but extremely slowly.
>
> But what is the benefit of a new process node?
>
> Now that Dennard scaling is no longer with us, shrinking to a new
> process node hasn't meant that microprocessors have gone from
> 3 GHz to 5 GHz to 6 GHz to 10 GHz and so on and on.
>
> The only advantages of a new process node is that one can put
> more cores on a single die, and one's chips use less power.

Not the *only* advantage. Newer process node with smaller gates means a
chip with a given number of gates is physically smaller. Physically
smaller chips means more chips per wafer. More chips per wafer means
lower cost per chip. (perhaps counterbalanced if the new process is more
expensive per wafer).

--
- Stephen Fuld
(e-mail address disguised to prevent spam)

Terje Mathisen <terje.mathisen@tmsw.no> schrieb:
> Niklas Holsti wrote:

>> "If I Were You" is the title of a novel by P.G. Wodehouse. One of his
>> best, IMO.
>
> I have probably read that one. I did read every single PGW book in my
> (very good!) local library, co-located with my primary school. Those
> books plus "The Complete Sherlock Holmes Short Stories" was how I taught
> myself English after learning the basics in school.

The main influence on my English was probably BFBS, the British
Forces Broadcasting Service. They were simply playing better
music than the German radio stations, so I tuned in.

And once I had discovered that science fiction reads much
better in the original language, there was no turning back.

For one of my family the impetus was Star Trek. We wanted to watch
the original series it in English (having only ever seen the German
version), and he asked if he could also watch it. We said OK,
but he would have to watch it in English. He didn't mind, so...

On 14/03/2022 17:45, Thomas Koenig wrote:
> Terje Mathisen <terje.mathisen@tmsw.no> schrieb:
>> Niklas Holsti wrote:
>
>>> "If I Were You" is the title of a novel by P.G. Wodehouse. One of his
>>> best, IMO.
>>
>> I have probably read that one. I did read every single PGW book in my
>> (very good!) local library, co-located with my primary school. Those
>> books plus "The Complete Sherlock Holmes Short Stories" was how I taught
>> myself English after learning the basics in school.
>
> The main influence on my English was probably BFBS, the British
> Forces Broadcasting Service. They were simply playing better
> music than the German radio stations, so I tuned in.
>
> And once I had discovered that science fiction reads much
> better in the original language, there was no turning back.
>
> For one of my family the impetus was Star Trek. We wanted to watch
> the original series it in English (having only ever seen the German
> version), and he asked if he could also watch it. We said OK,
> but he would have to watch it in English. He didn't mind, so...
>

And from that you learn grammar gems such as "To boldly go where no man
has gone before" - a split infinitive and ending the sentence in a
preposition.

(Both of these rules were added to Latinise English grammar.)

On Monday, March 14, 2022 at 8:22:08 AM UTC-5, Terje Mathisen wrote:
> Michael S wrote:

> I thought I read somewhere that back-to-back NOT gates are already much
> faster than the wire they would replace?
<
Properly sized back to back inverters have only about 25% more delay and
close to 3× the drive strength of a single inverter.
<
> Terje
>
>
> --
> - <Terje.Mathisen at tmsw.no>
> "almost all programming can be viewed as an exercise in caching"