On Wednesday, January 26, 2022 at 1:59:20 AM UTC+10, jpit...@gmail.com wrote:
> On Tuesday, 25 January 2022 at 14:26:42 UTC, Wayne morellini wrote:
> > On Sunday, January 23, 2022 at 7:51:00 PM UTC+10, Wayne morellini wrote:
> > > Watching videos, it mentioned a company called flair, I've in England, in the 1980's, used an ion beam chip making technique to get 2000 pound cost per run. I wonder if that sort of low cost prototyping technology is possible today.
> > Guys, Richard Rick Collins is calling on a lot of names, and we don't need them coming here and start arguing with each other. You have heard of divide and conquer. Stop concentrating on all the stuff of the past and each other. Kick a new thread name off, Rick Richard Colin's Arius, and take it there at least.
> As you might have seen, there is a thread here about our
> MIS16 in FPGA running eForth. The core is under 2500 gates.
> For the fun of it, I might actually do more research about low volume ASICs,
> one link I found recently
> https://electronics.stackexchange.com/questions/7042/how-much-does-it-cost-to-have-a-custom-asic-made
> which gives a lot of links that might be of interst.

That stack exchange is very bad. Isn't there a more useful place. A lot of people just can't run things ideally. I swapped majors st University, because the programmers had stupidity, and they also couldn't design themselves out of a thick enough paper bag. That thread was good, but viewing other threads, the moderators community is just not that good.

Anyway, I can't get to post there. But maybe you should ask them about shuttle service manufacturers who use this:

https://en.m.wikipedia.org/wiki/Maskless_lithography

No masks needed. I can also see how to do this a split second per layer, where masks could be redundant. Reading through the page now, I see they have the parallel writing technique I'm think of, but can't figure out how to do it better. Feature down to 3 or 2 manometers. But the 10-20 current nanometres is good on a low energy process.

I also hear of 50 layer chips band they are talking about 8 or more. Maybe that many layers is not available in those services.

You know what, we just solved GA's chip production issue :). They could use one of these services. Those things are so cheap, they could put thousands of trust circuits on a mm. But serious, integrating the maskless 10-20nm lithography onto the low energy 180nm process node, is the question. They could explore an in-house fab, even of they buy in wafers. That's like 100,000+ chips per wafer. They could get heaps of government and military funding to develop an in house fab product, and attach 32 bit misc chip development to the funding to run everything and as test manufacturer product, and sell the resulting paid for design chips as an end product. But, would they do it. Or complain? If they got funding to develop a high capacity in house mini lab, locking up the technology in the US fir twenty years, all American producers could affordably male their own designs. Putting a hundred together allows over ten million chips being worked on simultaneously, which is an option for large semi+conductor manufacturers. Currently, the country is too reliant on external chip production, and in case of war, the countries capacity could collapse, with the few mega chip foundries being easy targets, removing nearly 100% of in country processing chip production. With a distributed base, they are difficult to eliminate, and a war is likely over before they break down. It would also bring back in a lot of chip capacity in country. It's an idea worth making into a plan. We are also talking about 32 bit arrays of more full on processors capable of being clocked to very high frequencies over and above 6ghz. Is 10-20ghz possible? They also have the option to make the processor suitable for high speed 1-3 transistor ram types. Integrating high speed mass ram on chip, which have some limited memory retention in case of power failure. But, even an flash alternative could be integrated. Core memory, magnetic bubble alternative on a one transistor pin. I'm thinking here. A die at a time seal and dice with surface mount pads. That would be cheap. The normal chip like this is so low energy as not to require much thermal tolerance in packaging, but a heat sink can be integrated on the opposite side, will produce take significant clocking before a conventional fan or cooling set up.. That will cut big money out of packaging and mounting. We are talking about 32 bit integrated chips and memory, maybe storage, and peripheral interfaces (as memory is entirely an internal high speed lowenergy efficient bus, there is reduced pads and packaging sizes, for less than a cent each. Able to out compete high end phone chipsets, except without a you and various custom circuits. So. That would outcompete low end and maybe mid range circuited for a small fraction of the cost.
..

On Wednesday, January 26, 2022 at 2:46:26 PM UTC+10, gnuarm.del...@gmail.com wrote:
> On Wednesday, January 26, 2022 at 12:05:21 AM UTC-4, Wayne morellini wrote:
> >
> > I have already put out a contact to the guy doing chips in his garage, to make h aware that forth chips offer a compact target his next generation.. 300nm designs might be suitable for, and made home aware of a few past designs and players,who might like to contribute, including Jeff's estate, as his was the most complete fastest of the old misc designs that I know of, that he might be able to negotiate to use. I haven't heard back so far.
> Well, I'm glad my original post in this thread was of some use after all. You are welcome.
>
> --
>
> Rick C.
>
> -+- Get 1,000 miles of free Supercharging
> -+- Tesla referral code - https://ts.la/richard11209

You mean the guy I previously had been watching. Well, at least it was useful!

On Wednesday, January 26, 2022 at 1:56:16 AM UTC-4, Wayne morellini wrote:
> On Wednesday, January 26, 2022 at 2:46:26 PM UTC+10, gnuarm.del...@gmail.com wrote:
> > On Wednesday, January 26, 2022 at 12:05:21 AM UTC-4, Wayne morellini wrote:
> > >
> > > I have already put out a contact to the guy doing chips in his garage, to make h aware that forth chips offer a compact target his next generation. 300nm designs might be suitable for, and made home aware of a few past designs and players,who might like to contribute, including Jeff's estate, as his was the most complete fastest of the old misc designs that I know of, that he might be able to negotiate to use. I haven't heard back so far.
> > Well, I'm glad my original post in this thread was of some use after all. You are welcome.
> >
> > --
> >
> > Rick C.
> >
> > -+- Get 1,000 miles of free Supercharging
> > -+- Tesla referral code - https://ts.la/richard11209
> You mean the guy I previously had been watching. Well, at least it was useful!

Yeah, the post that you ripped me a new one for making, you claiming it was a "stupid" post as you were "asking about commercial services" which you didn't.

So you actually thought it was a good idea. Great, again, you are welcome.

I have no idea why you think I give a rat's rear about you or why you think I'm stalking you. I responded to a post and didn't pay attention to the name as you had not risen in my attention enough that I remembered you. But I know you now. The nutter who goes off for literally no reason at all.

Posting in the newsgroups is like talking in any public forum. If you don't like the other people using the forum, it is on you to ignore them or leave. I'm not trying to stalk you, or annoy you or anything else. I just want you to understand you are not significant enough for me to bother with even remembering your name... well, until now anyway.

--

Rick C.

-++ Get 1,000 miles of free Supercharging
-++ Tesla referral code - https://ts.la/richard11209

On Wednesday, 26 January 2022 at 04:05:21 UTC, Wayne morellini wrote:
> On Wednesday, January 26, 2022 at 1:59:20 AM UTC+10, jpit...@gmail.com wrote:
> > On Tuesday, 25 January 2022 at 14:26:42 UTC, Wayne morellini wrote:
> > > On Sunday, January 23, 2022 at 7:51:00 PM UTC+10, Wayne morellini wrote:
> > > > Watching videos, it mentioned a company called flair, I've in England, in the 1980's, used an ion beam chip making technique to get 2000 pound cost per run. I wonder if that sort of low cost prototyping technology is possible today.
> > > Guys, Richard Rick Collins is calling on a lot of names, and we don't need them coming here and start arguing with each other. You have heard of divide and conquer. Stop concentrating on all the stuff of the past and each other. Kick a new thread name off, Rick Richard Colin's Arius, and take it there at least.

> > As you might have seen, there is a thread here about our
> > MIS16 in FPGA running eForth. The core is under 2500 gates.
> > For the fun of it, I might actually do more research about low volume ASICs,
> > one link I found recently
> > https://electronics.stackexchange.com/questions/7042/how-much-does-it-cost-to-have-a-custom-asic-made
> > which gives a lot of links that might be of interest.

> I've been sick with brain dieing (yet, I'm still besting people who only think they are smart and should interfere). So, I can cover very little. But congratulations, I'm very interested. One thing I'm more interested in, is 32 bit version (per program space, with 64 bit file space support) that could be used on under $100 phones (cameras are a hobby too) real time, with hardware interfaces that can be added alongside as people customise. So, $30 touch phones could get possible.
>
> I have already put out a contact to the guy doing chips in his garage, to make h aware that forth chips offer a compact target his next generation. 300nm designs might be suitable for, and made home aware of a few past designs and players,who might like to contribute, including Jeff's estate, as his was the most complete fastest of the old misc designs that I know of, that he might be able to negotiate to use. I haven't heard back so far.
>
> I would like to suggest, maybe you might like to talk to GA about access to a latter OKCad, where the designs can be transfered to different manufacturing modes, once the right parameters are put in (like a range of designs at different parameters to see how far it can be reliably pushed).
>
> Maybe such services above are cheaper for low volume.
>
> I wish you good with this one Jurgen. That's how it's done RC!

I contacted Greg at GA many years ago, when I did consulting for MPE,
and when I started my Forth Bookshelf, had just published Chuck's book
https://www.amazon.co.uk/Juergen-Pintaske/e/B00N8HVEZM

There was no interest to have the F18 or a GA4 for understanding in Forth simulated or in VHDL,
it was seen as taking business away from GA, as Greg said.

And OKCAD I was told is the diamond in the crown of GA, no open access possible.
I wonder, how many more people than Chuck have used it to finish a project successfully.
Nothing there on the GA website.

Sorry to be a bit negative here,
but GA144 has not be seen in commercial projects to my knowledge.
To me personally it is a test chip to prove OKCAD that Chuck did and had manufactured about 10 years ago.

Is this silicon process still available, so more wafers could actually be manufactured?
And the new chip availibility seems to be shifting.
Sad, but these are the facts if nobody corrects them.

Do not get me wrong.
It takes a genius like Chuck to start with the level of a PCB layout and then
build it up to many more levels, generate GDSII and then have chips manufactured.
Many layers of software, so fits Forth perfectly.
Who else has achieved this?

Wayne morellini <waynemorellini@gmail.com> writes:
> 300nm designs might be suitable for, and made home aware of a few past
> designs and players, who might like to contribute, including Jeff's
> estate, as his was the most complete fastest of the old misc designs
> that I know of, that he might be able to negotiate to use.

300nm is a very old process and you might get higher performance from a
modern FPGA with a lot less hassle. And I wonder whether that guy in
his basement is doing anything even that modern. That used to be
considered very high tech. The Intel 8086 was done in 3 micron, and
earlier home chip fab stuff (#homecmos) was trying to do stuff at 12
microns iirc. This stuff is hard.

Why do you want to make a misc design anyway? And if you want a misc,
why not b16? If you want to play with architectures or instruction
sets, why not simulate then in software instead of making chips?

I'm a programmer and I understand the appeal of cool but useless
software projects, especially if you can put them online so other people
can download and enjoy them too. With hardware, it seems like way too
much work, plus replicating hardware requires work and expense for every
unit.

On Wednesday, 26 January 2022 at 10:09:31 UTC, Paul Rubin wrote:
> Wayne morellini <waynemo...@gmail.com> writes:
> > 300nm designs might be suitable for, and made home aware of a few past
> > designs and players, who might like to contribute, including Jeff's
> > estate, as his was the most complete fastest of the old misc designs
> > that I know of, that he might be able to negotiate to use.
> 300nm is a very old process and you might get higher performance from a
> modern FPGA with a lot less hassle. And I wonder whether that guy in
> his basement is doing anything even that modern. That used to be
> considered very high tech. The Intel 8086 was done in 3 micron, and
> earlier home chip fab stuff (#homecmos) was trying to do stuff at 12
> microns iirc. This stuff is hard.
>
> Why do you want to make a misc design anyway? And if you want a misc,
> why not b16? If you want to play with architectures or instruction
> sets, why not simulate then in software instead of making chips?
>
> I'm a programmer and I understand the appeal of cool but useless
> software projects, especially if you can put them online so other people
> can download and enjoy them too. With hardware, it seems like way too
> much work, plus replicating hardware requires work and expense for every
> unit.

This whole MISC16 project started in CPLD at the time, 25 years ago,
AND WAS RUNNING FORTH THEN
and is now in FPGA on github running an adapted eForth.
Thanks to Steve.
I was in ASIC at the time, and just want to find out if there is a way to get it into ASIC,
and what the performance would be now
and what the cost would be.
i MIGHT FIND A SPARE CORNER ON AN MPW FOR THESE 2500 GATES ...
No real BUSINESS requirement, as the FPGA is there now and flexible to mess around with if wanted.

There was an ASIC already at the time, using a modified design, manufactured at AMS in Austria as a student's final project.

On Wednesday, 26 January 2022 at 11:11:30 UTC, Jurgen Pitaske wrote:
> On Wednesday, 26 January 2022 at 10:09:31 UTC, Paul Rubin wrote:
> > Wayne morellini <waynemo...@gmail.com> writes:
> > > 300nm designs might be suitable for, and made home aware of a few past
> > > designs and players, who might like to contribute, including Jeff's
> > > estate, as his was the most complete fastest of the old misc designs
> > > that I know of, that he might be able to negotiate to use.
> > 300nm is a very old process and you might get higher performance from a
> > modern FPGA with a lot less hassle. And I wonder whether that guy in
> > his basement is doing anything even that modern. That used to be
> > considered very high tech. The Intel 8086 was done in 3 micron, and
> > earlier home chip fab stuff (#homecmos) was trying to do stuff at 12
> > microns iirc. This stuff is hard.
> >
> > Why do you want to make a misc design anyway? And if you want a misc,
> > why not b16? If you want to play with architectures or instruction
> > sets, why not simulate then in software instead of making chips?
> >
> > I'm a programmer and I understand the appeal of cool but useless
> > software projects, especially if you can put them online so other people
> > can download and enjoy them too. With hardware, it seems like way too
> > much work, plus replicating hardware requires work and expense for every
> > unit.
> This whole MISC16 project started in CPLD at the time, 25 years ago,
> AND WAS RUNNING FORTH THEN
> and is now in FPGA on github running an adapted eForth.
> Thanks to Steve.
> I was in ASIC at the time, and just want to find out if there is a way to get it into ASIC,
> and what the performance would be now
> and what the cost would be.
> i MIGHT FIND A SPARE CORNER ON AN MPW FOR THESE 2500 GATES ...
> No real BUSINESS requirement, as the FPGA is there now and flexible to mess around with if wanted.
>
> There was an ASIC already at the time, using a modified design, manufactured at AMS in Austria as a student's final project.

I know about both b16 versions
https://bernd-paysan.de/b16.html
But it is a different approach
- and MISC16 ( or 32 later, or 64 even) is for the fun of it.
I started this implementation at the time and it has come to a useful end for now.
I just translated an article from the Professor where the ASIC had been done at the time .
He was rather positive about the options, but stated as well - for FPGAs, ASICs or other specials.
And there are now sufficient readymade processors anyway here I can play with.
There are quite a few nice memories connected to this MISC.

On Wednesday, January 26, 2022 at 7:11:30 AM UTC-4, jpit...@gmail.com wrote:
> On Wednesday, 26 January 2022 at 10:09:31 UTC, Paul Rubin wrote:
> > Wayne morellini <waynemo...@gmail.com> writes:
> > > 300nm designs might be suitable for, and made home aware of a few past
> > > designs and players, who might like to contribute, including Jeff's
> > > estate, as his was the most complete fastest of the old misc designs
> > > that I know of, that he might be able to negotiate to use.
> > 300nm is a very old process and you might get higher performance from a
> > modern FPGA with a lot less hassle. And I wonder whether that guy in
> > his basement is doing anything even that modern. That used to be
> > considered very high tech. The Intel 8086 was done in 3 micron, and
> > earlier home chip fab stuff (#homecmos) was trying to do stuff at 12
> > microns iirc. This stuff is hard.
> >
> > Why do you want to make a misc design anyway? And if you want a misc,
> > why not b16? If you want to play with architectures or instruction
> > sets, why not simulate then in software instead of making chips?
> >
> > I'm a programmer and I understand the appeal of cool but useless
> > software projects, especially if you can put them online so other people
> > can download and enjoy them too. With hardware, it seems like way too
> > much work, plus replicating hardware requires work and expense for every
> > unit.
> This whole MISC16 project started in CPLD at the time, 25 years ago,
> AND WAS RUNNING FORTH THEN
> and is now in FPGA on github running an adapted eForth.
> Thanks to Steve.
> I was in ASIC at the time, and just want to find out if there is a way to get it into ASIC,
> and what the performance would be now
> and what the cost would be.
> i MIGHT FIND A SPARE CORNER ON AN MPW FOR THESE 2500 GATES ...
> No real BUSINESS requirement, as the FPGA is there now and flexible to mess around with if wanted.
>
> There was an ASIC already at the time, using a modified design, manufactured at AMS in Austria as a student's final project.

https://en.wikipedia.org/wiki/Multi-project_wafer_service

https://www.themosisservice.com/

It only takes money, but not always a lot.

--

Rick C.

+-- Get 1,000 miles of free Supercharging
+-- Tesla referral code - https://ts.la/richard11209

Rick C <gnuarm.deletethisbit@gmail.com> writes:
> https://en.wikipedia.org/wiki/Multi-project_wafer_service
> https://www.themosisservice.com/
> It only takes money, but not always a lot.

https://mycmp.fr/ is another one, and I remember there was something
about Google doing it for free for FOSS projects. Still, for something
like a cpu, I would test in an FPGA before even thinking about a custom
silicon implementation. And I would simulate in software before
thinking about an FPGA.

On Wednesday, January 26, 2022 at 2:07:37 PM UTC-4, Paul Rubin wrote:
> Rick C <gnuarm.del...@gmail.com> writes:
> > https://en.wikipedia.org/wiki/Multi-project_wafer_service
> > https://www.themosisservice.com/
> > It only takes money, but not always a lot.
> https://mycmp.fr/ is another one, and I remember there was something
> about Google doing it for free for FOSS projects. Still, for something
> like a cpu, I would test in an FPGA before even thinking about a custom
> silicon implementation. And I would simulate in software before
> thinking about an FPGA.

Of course. It is interesting that many times testing is given short shrift and bugs are allowed through. Just running "some code" is not good enough.. Even running a *lot* of code is not enough. The code to run has to exercise every detail of every function to have tested the design completely. Look at all the mistakes Intel has made over the years with the huge amount of simulation they do before hand.

But this discussion is not really about building such a design. It's more about thinking of building such a design. Even cheap ASICs are not cheap. That's why the kid made chips in his garage.

--

Rick C.

+-+ Get 1,000 miles of free Supercharging
+-+ Tesla referral code - https://ts.la/richard11209

On Wednesday, January 26, 2022 at 5:01:41 PM UTC+10, gnuarm.del...@gmail.com wrote:
> On Wednesday, January 26, 2022 at 1:56:16 AM UTC-4, Wayne morellini wrote:
> > On Wednesday, January 26, 2022 at 2:46:26 PM UTC+10, gnuarm.del...@gmail.com wrote:
> > > On Wednesday, January 26, 2022 at 12:05:21 AM UTC-4, Wayne morellini wrote:
> > > >
> > > > I have already put out a contact to the guy doing chips in his garage, to make h aware that forth chips offer a compact target his next generation. 300nm designs might be suitable for, and made home aware of a few past designs and players,who might like to contribute, including Jeff's estate, as his was the most complete fastest of the old misc designs that I know of, that he might be able to negotiate to use. I haven't heard back so far.
> > > Well, I'm glad my original post in this thread was of some use after all. You are welcome.
> > >
> > > --
> > >
> > > Rick C.
> > >
> > > -+- Get 1,000 miles of free Supercharging
> > > -+- Tesla referral code - https://ts.la/richard11209
> > You mean the guy I previously had been watching. Well, at least it was useful!

Rick Richard Collins Arius, stop hassling. You knew that was an inappropriate dim imitation reply. It wasn't about what was asked about or suitable for the purposes of commercial development, which is the only thing being discussed here. Just because I give the guy a heads up that can help him, GA, the scene, and maybe one day after a lot of effort, commercial. Yet, you are here again.. I can see why you are only a sub contractor.

> Yeah, the post that you ripped me a new one for making, you claiming it was a "stupid" post as you were "asking about commercial services" which you didn't.
>
> So you actually thought it was a good idea. Great, again, you are welcome..
>
> I have no idea why you think I give a rat's rear about you or why you think I'm stalking you. I responded to a post and didn't pay attention to the name as you had not risen in my attention enough that I remembered you. But I know you now. The nutter who goes off for literally no reason at all.

Better among righteous people who puts you in your place than the nutter that scurries about deludedly thinking he is smart trying to subversively start up trouble, while seen by others on the floor scurrying around. Who do you actually work for? Most of the stuff I know is declassified by now, so no use getting somebody to do this rubbish, this is not normal.

> Posting in the newsgroups is like talking in any public forum. If you don't like the other people using the forum, it is on you to ignore them or leave. I'm not trying to stalk you, or annoy you or anything else. I just want you to understand you are not significant enough for me to bother with even remembering your name... well, until now anyway.

BS Rick, stop saying stuff like that, you follow us around Rick Richard Collins, and always remember us. You know what you are doing. There are laws, it's up to you to cease and desist, and prove you are not a security risk. You also obstruct conversations. You don't seem to register to people, that you know how the greater responsibility, that overrides forums, works. People are having direct private conversation, or you have the official speakers, and you have nothing appropriate to contribute be respectful and stay quiet or leave the forum for good. It's not the shouting at each over the forum session. Do you think they wouldn't actually chuck somebody like that out of a physical forum? I'm the one not acting like a "nutter" as you say, who doesn't follow you around, and easily forgets you, and not inappropriately interfere with your private conversations. It's virtually only you doing this stuff, and is it up to the rest of us? Comeon! Do you work for the FSB, with thinking like that, how do you get a security clearance to do military work? If I was in the system, I would flag you and make sure you never work on such contracts. If you are Putin, I might think that might be a clever, got me, but otherwise, I don't think I have ever seen your say or do anything remarkable here. The only remarkable thing is, that you somehow think this is a good strategy, despite the contrary. I'm not going to tell you to go follow and push somebody else, just go away. It's up to you to stop.

On Wednesday, January 26, 2022 at 6:36:20 PM UTC+10, jpit...@gmail.com wrote:
> On Wednesday, 26 January 2022 at 04:05:21 UTC, Wayne morellini wrote:
> > On Wednesday, January 26, 2022 at 1:59:20 AM UTC+10, jpit...@gmail.com wrote:
> > > On Tuesday, 25 January 2022 at 14:26:42 UTC, Wayne morellini wrote:
> > > > On Sunday, January 23, 2022 at 7:51:00 PM UTC+10, Wayne morellini wrote:
> > > > > Watching videos, it mentioned a company called flair, I've in England, in the 1980's, used an ion beam chip making technique to get 2000 pound cost per run. I wonder if that sort of low cost prototyping technology is possible today.
> > > > Guys, Richard Rick Collins is calling on a lot of names, and we don't need them coming here and start arguing with each other. You have heard of divide and conquer. Stop concentrating on all the stuff of the past and each other. Kick a new thread name off, Rick Richard Colin's Arius, and take it there at least.
>
> > > As you might have seen, there is a thread here about our
> > > MIS16 in FPGA running eForth. The core is under 2500 gates.
> > > For the fun of it, I might actually do more research about low volume ASICs,
> > > one link I found recently
> > > https://electronics.stackexchange.com/questions/7042/how-much-does-it-cost-to-have-a-custom-asic-made
> > > which gives a lot of links that might be of interest.
> > I've been sick with brain dieing (yet, I'm still besting people who only think they are smart and should interfere). So, I can cover very little. But congratulations, I'm very interested. One thing I'm more interested in, is 32 bit version (per program space, with 64 bit file space support) that could be used on under $100 phones (cameras are a hobby too) real time, with hardware interfaces that can be added alongside as people customise. So, $30 touch phones could get possible.
> >
> > I have already put out a contact to the guy doing chips in his garage, to make h aware that forth chips offer a compact target his next generation.. 300nm designs might be suitable for, and made home aware of a few past designs and players,who might like to contribute, including Jeff's estate, as his was the most complete fastest of the old misc designs that I know of, that he might be able to negotiate to use. I haven't heard back so far.
> >
> > I would like to suggest, maybe you might like to talk to GA about access to a latter OKCad, where the designs can be transfered to different manufacturing modes, once the right parameters are put in (like a range of designs at different parameters to see how far it can be reliably pushed).
> >
> > Maybe such services above are cheaper for low volume.
> >
> > I wish you good with this one Jurgen. That's how it's done RC!
> I contacted Greg at GA many years ago, when I did consulting for MPE,
> and when I started my Forth Bookshelf, had just published Chuck's book
> https://www.amazon.co.uk/Juergen-Pintaske/e/B00N8HVEZM
>
> There was no interest to have the F18 or a GA4 for understanding in Forth simulated or in VHDL,
> it was seen as taking business away from GA, as Greg said.
>
> And OKCAD I was told is the diamond in the crown of GA, no open access possible.
> I wonder, how many more people than Chuck have used it to finish a project successfully.
> Nothing there on the GA website.
>
> Sorry to be a bit negative here,
> but GA144 has not be seen in commercial projects to my knowledge.
> To me personally it is a test chip to prove OKCAD that Chuck did and had manufactured about 10 years ago.
>
> Is this silicon process still available, so more wafers could actually be manufactured?
> And the new chip availibility seems to be shifting.
> Sad, but these are the facts if nobody corrects them.
>
> Do not get me wrong.
> It takes a genius like Chuck to start with the level of a PCB layout and then
> build it up to many more levels, generate GDSII and then have chips manufactured.
> Many layers of software, so fits Forth perfectly.
> Who else has achieved this?

Well, I thought the first okcad was available, and they might be using a useful more recent version of okcad in the silicon chip design training charity effort.

I'm a bit lost. Did I mention about using the ga chips here? I did mention about Jeff Foxe's F21 (was that the name?) to the young Sam. Fortunately I didn't point to here, with all the unprofessional obstruction. Anyway, if they have something more usefully through the school, off you go.

But what's your plan with the B16? I forgot to menton anti-fuse FPGA. Which works faster, which is one of the things I wanted, that the military scooped up high end parts for decade before last. What features and ports? A large amount of customisable/fpga like circuit, would allow customisation of work flow and interfaces? 16 bits is a great microcontroller, especially with 16 bit words, extra 128KB bank for writing, extra 128kB bank for reading, and a read write window into each. 384KB. I'm interested in retro gaming, and wanted to do home computers years ago.

64KB b16 computer would probably be extremely good Retro gaming machine equivalent against the 1970's era (and before anybody decides they are going photobomb in, the 1977 Bally arcade console had 64KB memory, while the slightly see Atari VCS had less than 200 bytes, relying on data in cartridge). But, if you add lots of banks, and a video circuit then you could add, video and at least 128KB video bank that's 512KB+, which would be extremely better. I've been thinking of a design for a retro CPU, using a lot of my priority graphics techniques, to use a lot less memory. But I've got a real life to do. But, it's curious. Simple quality graphics and dma circuitry adds little in comparison to the normal 8 bit CPU transistor count. I don't know about quality sound circuitry though.

I'm more interested in 32bits normally. If you going do this, why not jazz it up with a 16 and 32bit version on the same fab run, but some extended interfacing (embedded and the arm related open ones they use in phones) graphics, DMA graphics transfer and sound (maybe a few hundred transistors in compact form) and lots of memory, if the process can handle 1 transistor+ memory. The more memory padding, the better heat dissipation options to clock up the chip to higher speed. But, we already have a 6Ghz coming. Makes you think what a 16 bit could do at higher speeds for custom dsp software radio functions.

Anyway, looks like there are chip production options out there for you to get your chip done.

On Wednesday, January 26, 2022 at 8:09:31 PM UTC+10, Paul Rubin wrote:
> Wayne morellini <waynemo...@gmail.com> writes:
> > 300nm designs might be suitable for, and made home aware of a few past
> > designs and players, who might like to contribute, including Jeff's
> > estate, as his was the most complete fastest of the old misc designs
> > that I know of, that he might be able to negotiate to use.
> 300nm is a very old process and you might get higher performance from a
> modern FPGA with a lot less hassle. And I wonder whether that guy in
> his basement is doing anything even that modern. That used to be
> considered very high tech. The Intel 8086 was done in 3 micron, and
> earlier home chip fab stuff (#homecmos) was trying to do stuff at 12
> microns iirc. This stuff is hard.
>
> Why do you want to make a misc design anyway? And if you want a misc,
> why not b16? If you want to play with architectures or instruction
> sets, why not simulate then in software instead of making chips?
>
> I'm a programmer and I understand the appeal of cool but useless
> software projects, especially if you can put them online so other people
> can download and enjoy them too. With hardware, it seems like way too
> much work, plus replicating hardware requires work and expense for every
> unit.

Lost my reply. The garage silicon chip tray bed was introduced by RIck as a red herring. But, I contacted him to make him aware of forth chips, which could fit on his 300nm process as a test. I also pointed him to GA, be sure one day his work might result in something, like an commercial in house fab, and GA might be interested and has fab capacity constraints, and has an interest in silicon design education. For Jergen, it might be a way for Dam to test his chip naming skills, and for some test b16 to be made. A win, win, for everybody involved, except one person.

In designing high end silicon, they can simulate as much as they like, then still have to put in test chips 3 times, or more, to get it right. A software simulation and FPGA are not going guarantee everything, you still have to do a production prototype and test it actually works, and when you push the edge of things, to get faster and lower energy etc you get further away from normal simulations. Nobody said not to use these things, but in the end, you have to see if the silicon works well, and it's expensive.

On Wednesday, January 26, 2022 at 9:11:30 PM UTC+10, jpit...@gmail.com wrote:
> On Wednesday, 26 January 2022 at 10:09:31 UTC, Paul Rubin wrote:
> > Wayne morellini <waynemo...@gmail.com> writes:
> > > 300nm designs might be suitable for, and made home aware of a few past
> > > designs and players, who might like to contribute, including Jeff's
> > > estate, as his was the most complete fastest of the old misc designs
> > > that I know of, that he might be able to negotiate to use.
> > 300nm is a very old process and you might get higher performance from a
> > modern FPGA with a lot less hassle. And I wonder whether that guy in
> > his basement is doing anything even that modern. That used to be
> > considered very high tech. The Intel 8086 was done in 3 micron, and
> > earlier home chip fab stuff (#homecmos) was trying to do stuff at 12
> > microns iirc. This stuff is hard.
> >
> > Why do you want to make a misc design anyway? And if you want a misc,
> > why not b16? If you want to play with architectures or instruction
> > sets, why not simulate then in software instead of making chips?
> >
> > I'm a programmer and I understand the appeal of cool but useless
> > software projects, especially if you can put them online so other people
> > can download and enjoy them too. With hardware, it seems like way too
> > much work, plus replicating hardware requires work and expense for every
> > unit.
> This whole MISC16 project started in CPLD at the time, 25 years ago,
> AND WAS RUNNING FORTH THEN
> and is now in FPGA on github running an adapted eForth.
> Thanks to Steve.
> I was in ASIC at the time, and just want to find out if there is a way to get it into ASIC,
> and what the performance would be now
> and what the cost would be.
> i MIGHT FIND A SPARE CORNER ON AN MPW FOR THESE 2500 GATES ...
> No real BUSINESS requirement, as the FPGA is there now and flexible to mess around with if wanted.
>
> There was an ASIC already at the time, using a modified design, manufactured at AMS in Austria as a student's final project.

My apologies, I got your's mixed up with the b16 by Bernard.

However, about your CPLD model, what was the speed energy and instruction cycle characteristics of it? I'm interested if a modern CPLD would have an advantage of FPGA.

On Thursday, January 27, 2022 at 5:47:02 AM UTC+10, gnuarm.del...@gmail.com wrote:
> On Wednesday, January 26, 2022 at 2:07:37 PM UTC-4, Paul Rubin wrote:
> > Rick C <gnuarm.del...@gmail.com> writes:
> > > https://en.wikipedia.org/wiki/Multi-project_wafer_service
> > > https://www.themosisservice.com/
> > > It only takes money, but not always a lot.
> > https://mycmp.fr/ is another one, and I remember there was something
> > about Google doing it for free for FOSS projects. Still, for something
> > like a cpu, I would test in an FPGA before even thinking about a custom
> > silicon implementation. And I would simulate in software before
> > thinking about an FPGA.
> Of course. It is interesting that many times testing is given short shrift and bugs are allowed through. Just running "some code" is not good enough.. Even running a *lot* of code is not enough. The code to run has to exercise every detail of every function to have tested the design completely. Look at all the mistakes Intel has made over the years with the huge amount of simulation they do before hand.
>
> But this discussion is not really about building such a design. It's more about thinking of building such a design. Even cheap ASICs are not cheap. That's why the kid made chips in his garage.
>
> --
>
> Rick C.
>
> +-+ Get 1,000 miles of free Supercharging
> +-+ Tesla referral code - https://ts.la/richard11209

Well, now you are trying to say something useful.

The question was low cost prototyping services, no ifs or buts, about it.

Now, it is a bit more complicated than is being portrayed here. Combinations of features and sequences can also produce problems. So, testing all combinations long term, and setting up oscillation tests, where sequences can result in unseen build up that then cause an circuits deviation. But, this also is in combination with all stack and memory positions, pins on the chip and environmental factors and chip heat. That's a lot of testing. So, it might be worth writing a comprehensive test set, logging results with a 200mp infrared band pass filtered camera (Samsung mobile sensor) on bare silicon with a heat transparent packaging substitute. Test all chips in parallel with the camera on
the bare die. When something breaks, reference the others and what is happening on the video. You really need high speed as well, but this might show some heat build up. You will need specialised lenses to pickup at the limits, plus UV band passing (have to check if IR and UV blocking filters are removed on the camera as well) By running a lot of samples, you verify the defect rate for that batch, and can finish testing and produce a chip one day. When chips are constructed they are not nice and tidy, but things drift and go off track and can cause defects, where you need to space more to stop things from interfering with the next part of the circuit to the side.. So, if you get only one problem in say 25 chips, but they otherwise work great, then you might have trouble with something in the design not being sieved enough to compensate for manufacturing deviations. When you go smaller and smaller, you get aberration patterns. But, at larger sizes it likely has less issues with that. A straight FPGA conversion service might be a lot safer, but you miss out in all the fun stuff, like speed, and low energy etc.

On Thursday, 27 January 2022 at 05:41:33 UTC, Wayne morellini wrote:
> On Thursday, January 27, 2022 at 5:47:02 AM UTC+10, gnuarm.del...@gmail.com wrote:
> > On Wednesday, January 26, 2022 at 2:07:37 PM UTC-4, Paul Rubin wrote:
> > > Rick C <gnuarm.del...@gmail.com> writes:
> > > > https://en.wikipedia.org/wiki/Multi-project_wafer_service
> > > > https://www.themosisservice.com/
> > > > It only takes money, but not always a lot.
> > > https://mycmp.fr/ is another one, and I remember there was something
> > > about Google doing it for free for FOSS projects. Still, for something
> > > like a cpu, I would test in an FPGA before even thinking about a custom
> > > silicon implementation. And I would simulate in software before
> > > thinking about an FPGA.
> > Of course. It is interesting that many times testing is given short shrift and bugs are allowed through. Just running "some code" is not good enough. Even running a *lot* of code is not enough. The code to run has to exercise every detail of every function to have tested the design completely. Look at all the mistakes Intel has made over the years with the huge amount of simulation they do before hand.
> >
> > But this discussion is not really about building such a design. It's more about thinking of building such a design. Even cheap ASICs are not cheap.. That's why the kid made chips in his garage.
> >
> > --
> >
> > Rick C.
> >
> > +-+ Get 1,000 miles of free Supercharging
> > +-+ Tesla referral code - https://ts.la/richard11209
> Well, now you are trying to say something useful.
>
> The question was low cost prototyping services, no ifs or buts, about it.
>
> Now, it is a bit more complicated than is being portrayed here. Combinations of features and sequences can also produce problems. So, testing all combinations long term, and setting up oscillation tests, where sequences can result in unseen build up that then cause an circuits deviation. But, this also is in combination with all stack and memory positions, pins on the chip and environmental factors and chip heat. That's a lot of testing. So, it might be worth writing a comprehensive test set, logging results with a 200mp infrared band pass filtered camera (Samsung mobile sensor) on bare silicon with a heat transparent packaging substitute. Test all chips in parallel with the camera on
> the bare die. When something breaks, reference the others and what is happening on the video. You really need high speed as well, but this might show some heat build up. You will need specialised lenses to pickup at the limits, plus UV band passing (have to check if IR and UV blocking filters are removed on the camera as well) By running a lot of samples, you verify the defect rate for that batch, and can finish testing and produce a chip one day. When chips are constructed they are not nice and tidy, but things drift and go off track and can cause defects, where you need to space more to stop things from interfering with the next part of the circuit to the side. So, if you get only one problem in say 25 chips, but they otherwise work great, then you might have trouble with something in the design not being sieved enough to compensate for manufacturing deviations. When you go smaller and smaller, you get aberration patterns. But, at larger sizes it likely has less issues with that. A straight FPGA conversion service might be a lot safer, but you miss out in all the fun stuff, like speed, and low energy etc..

I got my first reply from a supplier, the first one I had asked for a general feedback, a starting point:

Our price for 180nm with a die area of 5mm2 (2.5mm x 2mm) is $5,750 for 40 sample die.
Assembly of 10 die into a 100QFN is $2,860.

Now it is back to the drawing board and see how to prepare for it
and find the right group that might be interested to help and make it real.

Yes, b16 is Bernd Paysan's baby and as I understood running in thousends of products now. I am only looking at MISC16.

Rick C <gnuarm.deletethisbit@gmail.com> writes:
> But this discussion is not really about building such a design. It's
> more about thinking of building such a design. Even cheap ASICs are
> not cheap. That's why the kid made chips in his garage.

MPW projects are not that far out of budget for serious hobbyists, plus
there is the free Google thing. Making chips in a garage is different,
it's because you want to implement the processes of making chips, not
because you want the chips as the end result.

On Thursday, January 27, 2022 at 3:54:59 AM UTC-4, Paul Rubin wrote:
> Rick C <gnuarm.del...@gmail.com> writes:
> > But this discussion is not really about building such a design. It's
> > more about thinking of building such a design. Even cheap ASICs are
> > not cheap. That's why the kid made chips in his garage.
> MPW projects are not that far out of budget for serious hobbyists, plus
> there is the free Google thing. Making chips in a garage is different,
> it's because you want to implement the processes of making chips, not
> because you want the chips as the end result.

I suppose you don't have any numbers to go with the claim of "not that far out of budget", do you?

Yeah, the kid was learning. But he could have learned with foundry chips too. But they weren't affordable, were they? The equipment the kid got was all very much on the low end of price because it was so far out of date.

--

Rick C.

++- Get 1,000 miles of free Supercharging
++- Tesla referral code - https://ts.la/richard11209

On Thursday, 27 January 2022 at 07:54:59 UTC, Paul Rubin wrote:
> Rick C <gnuarm.del...@gmail.com> writes:
> > But this discussion is not really about building such a design. It's
> > more about thinking of building such a design. Even cheap ASICs are
> > not cheap. That's why the kid made chips in his garage.
> MPW projects are not that far out of budget for serious hobbyists, plus
> there is the free Google thing. Making chips in a garage is different,
> it's because you want to implement the processes of making chips, not
> because you want the chips as the end result.

Agreed. But I look at options regarding my target:
Could I hold silicon with this MISC16 functionality in my hand some day?

This is definitely the MPW route - or other similar opportinities.
But then it all has to be ASIC ready.
Not just the VHDL files of MISC16.

The silicon out of his garage
https://www.youtube.com/watch?v=IS5ycm7VfXg
shows what can be done if you have the background, the interest ( and the space and the money ).
Great work.
This looks to me like the ideal candidate for OKCAD. A GA1 / 4 as a test chip?
I will follow this - but not for me as a basis for MISC16.

Rick C <gnuarm.deletethisbit@gmail.com> writes:
> I suppose you don't have any numbers to go with the claim of "not that
> far out of budget", do you?

See https://mycmp.fr/price-list/ it looks like CMP now starts around
$5K. I believe it used to start more like $3K. Oh well. There is
still Google. I don't know what other MPW places charge.

> Yeah, the kid was learning. But he could have learned with foundry
> chips too. But they weren't affordable, were they?

Yes but you don't make them yourself. You learn how to cook by cooking,
not by ordering from a restaurant.

Jurgen Pitaske <jpitaske@gmail.com> writes:
> This looks to me like the ideal candidate for OKCAD. A GA1 / 4 as a
> test chip?

OKCAD seems roughly comparable to other stuff that has been around since
the 1980s.

On Thursday, January 27, 2022 at 3:13:47 PM UTC-4, Paul Rubin wrote:
> Rick C <gnuarm.del...@gmail.com> writes:
> > I suppose you don't have any numbers to go with the claim of "not that
> > far out of budget", do you?
> See https://mycmp.fr/price-list/ it looks like CMP now starts around
> $5K. I believe it used to start more like $3K. Oh well. There is
> still Google. I don't know what other MPW places charge.
> > Yeah, the kid was learning. But he could have learned with foundry
> > chips too. But they weren't affordable, were they?
> Yes but you don't make them yourself. You learn how to cook by cooking,
> not by ordering from a restaurant.

The details learned from building a foundry in your garage is more like learning to cook in an open hearth and serving 18th century meals. Not of much real value in a modern kitchen unless you are outdoors camping. The value this kid got was not directly applicable to modern chip making. The skills learned from using a foundry to make your chips are just as applicable today as they were 25 years ago when a 300 nm process was state of the art. The difference is today you use more modern tools to validate your design before submitting it to a foundry.

--

Rick C.

+++ Get 1,000 miles of free Supercharging
+++ Tesla referral code - https://ts.la/richard11209

On Sunday, January 23, 2022 at 7:51:00 PM UTC+10, Wayne morellini wrote:
> Watching videos, it mentioned a company called flair, I've in England, in the 1980's, used an ion beam chip making technique to get 2000 pound cost per run. I wonder if that sort of low cost prototyping technology is possible today.

Ok, before we get into it. 180nm is an old low energy process. What is a smaller process that gets higher performance per watt, or just higher performance economically? All my own past design work goes towards doing something nobody else is able to do yet. So, lowest energy or highest performance, or lowest energy at a certain level of high performance, is a way to do this. Then, you have basically no competitive competition for a while. For instance internet of things. While Chuck's single node old designs look nice for smart dust, once you add the memory and started, and whatever else, it adds up. You get to a grain of sand etc or smart pebble. So, what I'm looking at doing, the two or three. schemes, keep the size and energy usage down and performance up

--

Well, nobody has, come back with an modern version of this commercial ion beam prototyping service, or any maskless. I'm going say, it's probably more interesting than anything here, and maybe more than stamp based chip production, as far as low cost goes. There is also laser ones, and thinking about the design last night, it's possibly possible to get that into 5/14 drive size, even smaller, in something a lot cheaper than a conventional silicon process. I've just been doing some writing on this subject, concluding depending on others to work it out the best, is like giving them the gun. You had better be able to trust them to do it right reliably. The is what has happened, the industry has chased it's tale down certain paths, and missed better alternatives. My examination is showing small featured, low cost chips, possible high performance, depending on what the materials science says, but that could possibly harm the device. It's tricky. We are talking lower cost than conventional potentially, but likely better once you cut out the suppliers and middle men. But, magnetic computing is going out do it,my optical will likely out do it. So, it's irrelevant. Within 10 years, the chip industry as we know it, might be in the way out. It is very naive, unless you are ultimate, you are normally going be replaced, so develop the better technology solution. A the time, you here of investment being diverted to the latest silicon chip, where if you changed over to a better technology, the investment in that would far exceed where we are.

I'm perplexed somebody now is promoting my original objections about proposing the garage chip 'lab' as a commercial prototyping service, like his opinion. :

Anyway, at the moment misc16 would give the garage lab something to experiment with. Making great publicity. At 300nm, he is not far off 180nm, and such things can lead to development of equipment which can be commercialised. Stop looking at the guy as a guy in a garage, and look at him as a potential Wozinak in a garage, with a bit of Steve Jobs mixed in let him role, and see if it goes anywhere. It might be a 5% chance it could go anywhere, that's up to him, what he wants.

On Thursday, 27 January 2022 at 19:15:03 UTC, Paul Rubin wrote:
> Jurgen Pitaske <jpit...@gmail.com> writes:
> > This looks to me like the ideal candidate for OKCAD. A GA1 / 4 as a
> > test chip?
> OKCAD seems roughly comparable to other stuff that has been around since
> the 1980s.

For example which product / solution?
And what were the results achieved?

Jurgen Pitaske <jpitaske@gmail.com> writes:
>> OKCAD seems roughly comparable to other stuff that has been around since
>> the 1980s.
>
> For example which product / solution? And what were the results
> achieved?

For example the Berkeley tools: Caesar, its successor Magic, Spice, and
so on. Spice is still in use and important. I wrote that Magic had
long been superseded by HDL's, but now see that it is still around:

http://opencircuitdesign.com/magic/

I have no idea if anyone uses Magic now, but lots of chips were designed
with it back in the day.