On Sunday, October 16, 2022 at 4:22:36 PM UTC-4, johnro...@gmail.com wrote:
> \ Op Code File for MFX. Generated by MAKE-OPS v13
> <clip>
> > > > > > > > > > > > > > > The Logic Compiler is working and the modules for the processor are done and tested. After the mem interface module is complete we'll be ready to put the design into the fpga. We're using a X02-7000 but the design will work in any equivalent part.
> <clip>
> > > > > > > > > > > > Sorry, I don't follow. What are you describing by, "use VHDL on an FPGA to write to it directly in Forth"?
> > > > > > > > > > > > If you are talking about a stack CPU, written in VHDL, running on an FPGA, that has been done
> > > > > > > > > > > > many, many times, some published, many not published. It would seem to be a trivial exercise.
> > > > > > > > > > > > Rick C.
>
> Verilog, NOT VHDL. I found it to be too verbose.

If you think Verilog is verbose, don't even bother trying VHDL. Perhaps is it not you, but someone in the thread is using VHDL to stand for something other than its traditional meaning of VHSIC Hardware Description Language. This gets to be very confusing.

> And if you have a trivial solution to computer optimization, please post it!

Not sure what you are referring to.

> (edited for clarity)
> > > > > > > > > > > Designing logic with the Forth VHDL
> > > > > > > > > > > 1. Write a software simulation of the design. (Forth with local varables and a MAP extension)
> > > > > > > > > > > 2. Test the design. (test program, simple compiler and simulator written in Forth)
> > > > > > > > > > > 3. Convert the simulation into a hardware definition. (ED-MGEN, ED-CTRL, ED-DFRW, ED-DCDM, ED-DSEL)
> > > > > > > > > > > 4. Link instructions to modules. (EDIT-TRAN)
> > > > > > > > > > > 5. Compile the hardware definition into logic equations. (GEN-MAP, CTRL-MAP & DFRW-MAP programs}
> > > > > > > > > > > 6. Verify the logic equations work correctly. (EDIT-DISP, SIM-R32)
> > > > > > > > > > > 7. Assign the I/O pins. (ED-PINS, able to parse the csv pin file and combine it with the schematic foot print)
> > > > > > > > > > > 8. Fit the logic equations into the device. (Diamond from Lattice Semi does this, and there are universal ones)
> > > > > > > > > > > 9. Convert the routed design into a fusemap. (Diamond)
> > > > > > > > > > > 10. Compile the OS using the OP code definition file. (MAKE-OPS)
> <clip>
> > > > > > > > > > "Forth VHDL"??? You are talking about a VHDL synthesis tool written in Forth???
> > > > > > > > > > No, that doesn't fit the description of what is going on.
> > > > > > > > > > In fact, your description doesn't seem to relate to VHDL at all.
> > > > > > > > > > I can't tell what you are talking about from this description,
> > > > > > > > > > but it sounds like it is for CPLDs, rather than FPGAs.
> > > > > > > > > > Rick C.
> Our first CNC product had three 8032 processors. One for motion, One to process files, and one for I/O.
> We replaced the motion and file processors with the RACE, (Reduced Architecture Computation Engine)
> in our new controller realased in 2000. The RACE and 4 motor controllers fit into a 1048 CPLD from Lattice.
> In 2016 we moved the design to an X02-7000 and eliminated the 8032.
> The design wasn't optomized for a LUT based part and the OS was getting too large for the address space
> so it was obvious we needed to update the design.
>
> Using verilog tools and IP express, provided by Diamond, it took about two years to move our IP to the X02,
> I've designed a wide variety of IP from servo system to networks and developed tools along to way to
> assist in making such devices. For example the software from Lattice used for the RACE could only
> achieve 80% ultization, I devised a tool that allowed us to achieve 100%,

Silicon is relatively inexpensive, these days. A project has to be very, very high volume to justify such an effort of optimization. I'm currently working on a redesign because of component optimization and I'm happy with 100% overkill on a new part, because the chip cost is only $5 each. I could use a $3 part, but it is 4 kLUT and the previous design was using 90% of a 3 kLUT part. Since it is a change of not just family, but brand, I don't look forward to spending excessive time shoehorning a design into a device. That makes alterations in the design prohibitively expensive as well.

Still, with a volume of perhaps 50,000 pieces, I might go with the smaller chip as long as I can share the footprint with the larger part.

> Designing and debuging the software for rapid processor evolution was more difficult than anticipated, as
> usual, but necessary for a reconfigurable product that could be used by small business having to compete
> with large corporate monopolies that have gained control of the regulatory bodies and are using their
> power to crush competion!
>
> > > > > > > > Ah, so he's bastardizing the term VHDL. (there's a little bit of Hugh in everyone)
> > > > > > > > > They used it on a CPLD first, and on a Lattice FPGA 7k now.
> > > > > > > > > Hugh Aguilar was involved there.
> > > > > > > > > And with all of the knowledge and experience here or elsewhere
> > > > > > > > > it could probably be ported to
> > > > > > > > > other FPGA families.
> <clip>
> > > > > > One of my early jobs involved designing a microprogrammed DMA controller using an off the shelf sequencer chip. The other, similar designs in the company all used the same assembler tool. I added a few macros and opcodes, in order to give my design additional self-test capabilities. One of the managers said that was a bad idea because no one else would know how to use this "different" tool. I realized that there are many times when standardization is preferred over technical advantages, because technical advantages are of no use if they make the design hard to work with or modify.
> > > > > >
> > > > > > In this case, there is no real utility to this "special" design process and it actually appears to be much more complex and difficult to use.
> > > > > >
> <clip>
> > > > Trying to use Forth as the language to compose logic is solving a problem that doesn't exist. We have Verilog and VHDL as the mainstream languages for logic hardware design and they work well. There are efforts to use C for hardware logic design, which is seldom used. The main justification for using C is to have a common language for hardware and software, so the dividing line is easily moved, allowing one system design to be implemented in different ways with different performance levels. In reality, this is not at all simple to do. Hardware and software require interfaces. When you change the dividing line in the code for that interface and you have to redesign everything about that interface. So it is seldom used this way.
> > > >
> > > > I stand by my statement that using Forth for both software and hardware design is of little value. The fact that you found one guy, who, six years ago, worked on using Forth as a hardware description language, does not mean it is a good idea. If that were true, why has nothing happened with it in the last six years?
> > > >
> > > > People like to think that applying Forth to a problem, will make that problem simple to solve. Digital hardware logic design is not a simple task, not because of the tools used. The tools are complicated because the problem is complicated. The existing tools have simplified the work by hiding the complexity as much as possible. This works 99.9% of the time, allowing work to proceed with reasonable speed and accuracy. I can't see where Forth is going to help this at all.
> > > > Rick C.
> Each to their own. I've spent too much time on this, got to get back to work.
> > Verilog already describes *the desired behaviour of any number of parallel processes, clocked or flow-through*.
> >I don't see a need for an exotic "Forth" front end (to generate what?).
> I don't know. You tell me.

I haven't seen anything that would seem to be a Forth description of hardware in this thread, so I can't judge if it is better than one of the existing HDLs or not. But it would need to be pretty good to make it worth learning a new tool and then to try to get it to produce VHDL that commonly available tools can use optimally.

--

Rick C.

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