whit3rd wrote:
> On Friday, October 7, 2022 at 4:10:22 PM UTC-7, Fred Bloggs wrote:
>> On Friday, October 7, 2022 at 4:41:24 PM UTC-4, John Walliker wrote:
>>> On Friday, 7 October 2022 at 18:25:51 UTC+1, Fred Bloggs wrote:
>
>>>> LS doesn't have ESD clamp diodes on its outputs, and, in fact, nothing is being
>>>> avalanched by applying a very current limited 20V to its outputs. Maybe an insignificant
>>>> elevated leakage is all that happens. The original circuit is well-designed and should be left as is.
>
>>> I can see that the original circuit might work fine, but it does depend on parameters that
>>> are not specified in the data sheet like the breakdown voltage of the output pull-down
>>> transistor, so I wouldn't be comfortable calling it "well designed".
>
>> Well I would and here's why. The ultra-fast (for its day) rise/fall times of the logic family brought
>> transmission line effects into standard logic design. If the typical LS output gate transitioned
>> a typical high impedance interconnecting trace to 5V, and that 5V pulse meets a high
>> impedance input of another LS gate as its only load. The signal will be reflected 100% positively ...
>
>> Typical margins are factor of 2x or more, making a withstanding voltage of 20V
>> a done deal, and that can be verified for the part. That's why I'm saying it's a good design.
>
> Actually, would substituting a 74HCT138 or 74ACT138 be a good solution?
> There's certainly protection diodes built into its outputs (MOS body diode).
> 74ACT138 can take 50 mA into its output pin.
>
> <https://www.ti.com/lit/ds/symlink/cd74act138.pdf>
>

The lights would be on continuously, looks like. Using HC plus cascode
FETs would be a complete solution, though.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510

http://electrooptical.net
http://hobbs-eo.com

On Saturday, October 8, 2022 at 11:27:51 AM UTC-4, Fred Bloggs wrote:
> On Friday, October 7, 2022 at 9:52:12 PM UTC-4, Ricky wrote:
> > On Friday, October 7, 2022 at 7:10:22 PM UTC-4, Fred Bloggs wrote:
> > > On Friday, October 7, 2022 at 4:41:24 PM UTC-4, John Walliker wrote:
> > > > On Friday, 7 October 2022 at 18:25:51 UTC+1, Fred Bloggs wrote:
> > > > > On Thursday, October 6, 2022 at 10:50:15 AM UTC-4, John Larkin wrote:
> > > > >
> > > > > <snip gibberish>
> > > > > > That's not clear. Got a schematic?
> > > > > > >
> > > > > He's wasting his time, there's nothing wrong with the original circuit.
> > > > >
> > > > > He's just one of those people who, when they can't understand something, think something is wrong.
> > > > > LS doesn't have ESD clamp diodes on its outputs, and, in fact, nothing is being avalanched by applying a very current limited 20V to its outputs. Maybe an insignificant elevated leakage is all that happens. The original circuit is well-designed and should be left as is.
> > > > I can see that the original circuit might work fine, but it does depend on parameters that
> > > > are not specified in the data sheet like the breakdown voltage of the output pull-down
> > > > transistor, so I wouldn't be comfortable calling it "well designed"..
> > > Well I would and here's why. The ultra-fast (for its day) rise/fall times of the logic family brought transmission line effects into standard logic design. If the typical LS output gate transitioned a typical high impedance interconnecting trace to 5V, and that 5V pulse meets a high impedance input of another LS gate as its only load. The signal will be reflected 100% positively for 5V traveling back down the trace to the driver. Since the driver pulled high is high impedance, the returning pulse again is reflected positively 100% making the voltage at the driver output 10V. The new +5V transition sends a 10V edge traveling down the line to the LS input and gets clamped at 5V which is a full negative reflection to return back to the driver and reduce the 10V at the output node ideally to 5V etc. So we know for a *fact* the process has to be designed to withstand a repetitive 10V applied to the output. And that's not just withstand to survive, that's withstand with no internal circuit disruption. Typical margins are factor of 2x or more, making a withstanding voltage of 20V a done deal, and that can be verified for the part. That's why I'm saying it's a good design.
> > I thought I was following this ok, until I got to the point of the second wave being clamped at the LS input to the 5V rail. Is that were the case, how could the first reflection be above 5V?
> >
> > That aside, your whole description is pretty off track. The LS output driving the "high impedance" trace, does not pull up to 5V in the first place. The "high impedance" trace is not high enough to be ignored. The reality is the driver output will only drive hard to maybe 3.5V. Combine that with the trace impedance loading of around 110 ohms, and you get something like a 2V initial edge on the trace. This will be doubled at the far end reflection at the LS input, to about 4V. So there's no need to worry about over voltage from reflections.
> Not going to get into those details. Theoretically your 4V return pulse would get doubled to 8V at the LS OUT pin, but it doesn't, and here's why. When the LS totem pole gets pushed into back bias, its current is immediately cut off, inducing the superposition of a 2.0V negative going pulse on the line. So the 4V incoming combined with that gets you back to your original 2V, and then the load sees a negative 2V step one line length delay later.

Except this is not what is seen. If the line at the receiver spent any time at 2V, we would see all manner of misbehavior in the circuit. Imagine this being a clock line or an edge sensitive chip enable.

> Stuff like shows why you're okay using unterminated lines most of the time for combinatorial inputs- it's the clocked inputs that are the weak link, unterminated line reflections cause the infamous glitchy double clocking problems. TTL drive levels are too weak for a DC termination but they're good enough for an AC termination. The AC termination is a series R+C shunting the line to signal COM at the load. The R is the interconnecting trace/wire characteristic impedance, and C is selected for an RC time constant equal to signal transition time. That one works pretty well. It's only needed in extreme situations where the line has to be run over 18" or so for some reason.

Funny, I've worked on tons of TTL circuits that were not terminated and had no problems with glitchy clocks. Well, maybe not tons, but at least many pounds.

It was always the ECL that required termination. But talk about power dissipation! Whew! We had machines that could overheat a high bay factory just from running the machines! The air conditioners were not designed to run in the winter, so we had to open doors.

--

Rick C.

-++ Get 1,000 miles of free Supercharging
-++ Tesla referral code - https://ts.la/richard11209

On Fri, 7 Oct 2022 16:10:18 -0700 (PDT), Fred Bloggs
<bloggs.fredbloggs.fred@gmail.com> wrote:

>On Friday, October 7, 2022 at 4:41:24 PM UTC-4, John Walliker wrote:
>> On Friday, 7 October 2022 at 18:25:51 UTC+1, Fred Bloggs wrote:
>> > On Thursday, October 6, 2022 at 10:50:15 AM UTC-4, John Larkin wrote:
>> >
>> > <snip gibberish>
>> > > That's not clear. Got a schematic?
>> > > >
>> > He's wasting his time, there's nothing wrong with the original circuit.
>> >
>> > He's just one of those people who, when they can't understand something, think something is wrong.
>> > LS doesn't have ESD clamp diodes on its outputs, and, in fact, nothing is being avalanched by applying a very current limited 20V to its outputs. Maybe an insignificant elevated leakage is all that happens. The original circuit is well-designed and should be left as is.
>> I can see that the original circuit might work fine, but it does depend on parameters that
>> are not specified in the data sheet like the breakdown voltage of the output pull-down
>> transistor, so I wouldn't be comfortable calling it "well designed".
>
>Well I would and here's why. The ultra-fast (for its day) rise/fall times of the logic family brought transmission line effects into standard logic design. If the typical LS output gate transitioned a typical high impedance interconnecting trace to 5V, and that 5V pulse meets a high impedance input of another LS gate as its only load. The signal will be reflected 100% positively for 5V traveling back down the trace to the driver. Since the driver pulled high is high impedance, the returning pulse again is reflected positively 100% making the voltage at the driver output 10V. The new +5V transition sends a 10V edge traveling down the line to the LS input and gets clamped at 5V which is a full negative reflection to return back to the driver and reduce the 10V at the output node ideally to 5V etc. So we know for a *fact* the process has to be designed to withstand a repetitive 10V applied to the output. And that's not just withstand to survive, that's withstand with no internal
circuit
>disruption. Typical margins are factor of 2x or more, making a withstanding voltage of 20V a done deal, and that can be verified for the part. That's why I'm saying it's a good design.
>
>
>>
>> John

LS has wussy pullups and is not very fast. LS is "low power schottky"
logic. Zs is around 100 ohms and rise is slow. It won't drive a
transmission line very hard.

See fig 25. Barely any reflection overshoot, certainly not over +5.

https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=&cad=rja&uact=8&ved=2ahUKEwjvpfDVgtH6AhWuKUQIHUJMA6sQFnoECDoQAQ&url=https%3A%2F%2Fwww.ti.com%2Flit%2Fpdf%2Fsdya009&usg=AOvVaw2oKKkUlZ0b2DDwfOBBKOMt

So not "for a *fact*"

On Thu, 6 Oct 2022 08:29:16 -0700 (PDT), Fred Bloggs
<bloggs.fredbloggs.fred@gmail.com> wrote:

>On Thursday, October 6, 2022 at 2:24:33 AM UTC-4, John Robertson wrote:
>> Have a circuit that needs repair. Uses a TIP125 (NPN, Darlington)
>> emitter tied to Vbb (~20VDC). Collector to load, then to ground. 1K
>> resistor (R1) pullup on Base to Vbb, and a second 1KR (R2) to the TTL
>> controller.
>>
>> Problem is of course, that R2 puts the ~20VDC to the TTL output gate on
>> a 74LS138.
>>
>> Trying to solve this without a driver transistor. The circuit is for a
>> 1ms ~20V strobe pulse repeated every ten ms.
>>
>> I thought of putting a 10ufd cap in series with R2, but don't like
>> electrolytics as they fail after a few thousand hours.
>>
>> Possible to use a 15V or so Zener Diode, but the Vbb is not regulated so
>> that won't work reliably.
>>
>> Anyone have a single component in mind that will essentially emulate
>> (isolate) an Open-Collector output for the 138?
>
>The TIP125 is a complementary dual.

It's a single TO-220 PNP.

On Saturday, October 8, 2022 at 12:43:34 PM UTC-4, Ricky wrote:
> On Saturday, October 8, 2022 at 11:27:51 AM UTC-4, Fred Bloggs wrote:
> > On Friday, October 7, 2022 at 9:52:12 PM UTC-4, Ricky wrote:
> > > On Friday, October 7, 2022 at 7:10:22 PM UTC-4, Fred Bloggs wrote:
> > > > On Friday, October 7, 2022 at 4:41:24 PM UTC-4, John Walliker wrote:
> > > > > On Friday, 7 October 2022 at 18:25:51 UTC+1, Fred Bloggs wrote:
> > > > > > On Thursday, October 6, 2022 at 10:50:15 AM UTC-4, John Larkin wrote:
> > > > > >
> > > > > > <snip gibberish>
> > > > > > > That's not clear. Got a schematic?
> > > > > > > >
> > > > > > He's wasting his time, there's nothing wrong with the original circuit.
> > > > > >
> > > > > > He's just one of those people who, when they can't understand something, think something is wrong.
> > > > > > LS doesn't have ESD clamp diodes on its outputs, and, in fact, nothing is being avalanched by applying a very current limited 20V to its outputs. Maybe an insignificant elevated leakage is all that happens. The original circuit is well-designed and should be left as is.
> > > > > I can see that the original circuit might work fine, but it does depend on parameters that
> > > > > are not specified in the data sheet like the breakdown voltage of the output pull-down
> > > > > transistor, so I wouldn't be comfortable calling it "well designed".
> > > > Well I would and here's why. The ultra-fast (for its day) rise/fall times of the logic family brought transmission line effects into standard logic design. If the typical LS output gate transitioned a typical high impedance interconnecting trace to 5V, and that 5V pulse meets a high impedance input of another LS gate as its only load. The signal will be reflected 100% positively for 5V traveling back down the trace to the driver. Since the driver pulled high is high impedance, the returning pulse again is reflected positively 100% making the voltage at the driver output 10V. The new +5V transition sends a 10V edge traveling down the line to the LS input and gets clamped at 5V which is a full negative reflection to return back to the driver and reduce the 10V at the output node ideally to 5V etc. So we know for a *fact* the process has to be designed to withstand a repetitive 10V applied to the output. And that's not just withstand to survive, that's withstand with no internal circuit disruption. Typical margins are factor of 2x or more, making a withstanding voltage of 20V a done deal, and that can be verified for the part. That's why I'm saying it's a good design.
> > > I thought I was following this ok, until I got to the point of the second wave being clamped at the LS input to the 5V rail. Is that were the case, how could the first reflection be above 5V?
> > >
> > > That aside, your whole description is pretty off track. The LS output driving the "high impedance" trace, does not pull up to 5V in the first place. The "high impedance" trace is not high enough to be ignored. The reality is the driver output will only drive hard to maybe 3.5V. Combine that with the trace impedance loading of around 110 ohms, and you get something like a 2V initial edge on the trace. This will be doubled at the far end reflection at the LS input, to about 4V. So there's no need to worry about over voltage from reflections.
> > Not going to get into those details. Theoretically your 4V return pulse would get doubled to 8V at the LS OUT pin, but it doesn't, and here's why. When the LS totem pole gets pushed into back bias, its current is immediately cut off, inducing the superposition of a 2.0V negative going pulse on the line. So the 4V incoming combined with that gets you back to your original 2V, and then the load sees a negative 2V step one line length delay later.
> Except this is not what is seen. If the line at the receiver spent any time at 2V, we would see all manner of misbehavior in the circuit. Imagine this being a clock line or an edge sensitive chip enable.
> > Stuff like shows why you're okay using unterminated lines most of the time for combinatorial inputs- it's the clocked inputs that are the weak link, unterminated line reflections cause the infamous glitchy double clocking problems. TTL drive levels are too weak for a DC termination but they're good enough for an AC termination. The AC termination is a series R+C shunting the line to signal COM at the load. The R is the interconnecting trace/wire characteristic impedance, and C is selected for an RC time constant equal to signal transition time. That one works pretty well. It's only needed in extreme situations where the line has to be run over 18" or so for some reason.
> Funny, I've worked on tons of TTL circuits that were not terminated and had no problems with glitchy clocks. Well, maybe not tons, but at least many pounds.

What's funny is that you're so knowledgeable on the basis of such limited experience. Try using signal coming in over a cable LPT port for clocks. There an AC termination into a Schmitt is advisable.

>
> It was always the ECL that required termination. But talk about power dissipation! Whew! We had machines that could overheat a high bay factory just from running the machines! The air conditioners were not designed to run in the winter, so we had to open doors.

The design rules were to use termination on distances greater than 0.8-1.4 inch depending on family- and that was to keep reflection below 20%. Terminations to 2V were the norm, and the 82/130 Thevenin split for 50R was pretty common. That adds up to a lot of current draw.

>
> --
>
> Rick C.
>
> -++ Get 1,000 miles of free Supercharging
> -++ Tesla referral code - https://ts.la/richard11209

On Thu, 6 Oct 2022 14:31:36 -0400, Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:

>Lasse Langwadt Christensen wrote:
>> torsdag den 6. oktober 2022 kl. 20.04.09 UTC+2 skrev Phil Hobbs:
>>> Lasse Langwadt Christensen wrote:
>>>> torsdag den 6. oktober 2022 kl. 18.51.13 UTC+2 skrev Phil Hobbs:
>>>>> John Robertson wrote:
>>>>>> On 2022/10/06 4:41 a.m., Phil Hobbs wrote:
>>>>>>> John Robertson wrote:
>>>>>>>> Have a circuit that needs repair. Uses a TIP125 (NPN, Darlington)
>>>>>>>> emitter tied to Vbb (~20VDC). Collector to load, then to ground. 1K
>>>>>>>> resistor (R1) pullup on Base to Vbb, and a second 1KR (R2) to the TTL
>>>>>>>> controller.
>>>>>>>>
>>>>>>>> Problem is of course, that R2 puts the ~20VDC to the TTL output gate
>>>>>>>> on a 74LS138.
>>>>>>>>
>>>>>>>> Trying to solve this without a driver transistor. The circuit is for
>>>>>>>> a 1ms ~20V strobe pulse repeated every ten ms.
>>>>>>>>
>>>>>>>> I thought of putting a 10ufd cap in series with R2, but don't like
>>>>>>>> electrolytics as they fail after a few thousand hours.
>>>>>>>>
>>>>>>>> Possible to use a 15V or so Zener Diode, but the Vbb is not regulated
>>>>>>>> so that won't work reliably.
>>>>>>>>
>>>>>>>> Anyone have a single component in mind that will essentially emulate
>>>>>>>> (isolate) an Open-Collector output for the 138?
>>>>>>>>
>>>>>>>> Thanks!
>>>>>>>>
>>>>>>>> John :-#)#
>>>>>>>>
>>>>>>> Switch it to a 139 and use a 2N7002?
>>>>>>>
>>>>>>> Cheers
>>>>>>>
>>>>>>> Phil Hobbs
>>>>>>>
>>>>>>
>>>>>> Well, this is to fix 5 x PCBs we are stuck with at the moment, next run
>>>>>> will fix the drives - either 7445s or 138 with P-Channel MOSFETs and
>>>>>> drivers.
>>>>>>
>>>>>> Circuit I am trying to fix with fewest components - one x two legged
>>>>>> device preferred per 138 output:
>>>>>>
>>>>>> https://www.flippers.com/images/delete/74LS138_Lamp_Driver.png
>>>>>>
>>>>>> VLAMP is roughly 20VDC.
>>>>>>
>>>>>> Thanks,
>>>>>>
>>>>>> John :-#)#
>>>>> The MOSFET cascode thing is pretty good actually, if you put a diode to
>>>>> the supply or want to live dangerously and rely on the ESD protection to
>>>>> discharge the gate. If it's a matter of using the boards or tossing
>>>>> them, there's not much to lose by using barefoot FETs.
>>>>>
>>>>
>>>> '138 is push-pull, though very wimpy high side
>>>>
>>> Sure, but anything above +4ish reverse-biases the upper output transistor.
>>> Cheers
>>
>> with the upper transistor on does it ever get there?
>>
>>
>
>Sure, it's an NPN emitter. If it were a NFET, it would be fine.
>
>Cheers
>
>Phil Hobbs

LS has a darlington with 110 ohms in the drain and probably no ESD
diode to +5.

It's shocking how poorly specified all those old TTL parts were.
Modern logic isn't much better. We have to measure stuff like Zout and
rise/fall times. Sometimes the results are startling.

We just yesterday decided that an efinix FPGA output was a pretty good
50 ohm source termination, so made the traces 50 ohms and deleted some
r-packs.

On Saturday, October 8, 2022 at 12:49:44 PM UTC-4, John Larkin wrote:
> On Fri, 7 Oct 2022 16:10:18 -0700 (PDT), Fred Bloggs
> <bloggs.fred...@gmail.com> wrote:
>
> >On Friday, October 7, 2022 at 4:41:24 PM UTC-4, John Walliker wrote:
> >> On Friday, 7 October 2022 at 18:25:51 UTC+1, Fred Bloggs wrote:
> >> > On Thursday, October 6, 2022 at 10:50:15 AM UTC-4, John Larkin wrote:
> >> >
> >> > <snip gibberish>
> >> > > That's not clear. Got a schematic?
> >> > > >
> >> > He's wasting his time, there's nothing wrong with the original circuit.
> >> >
> >> > He's just one of those people who, when they can't understand something, think something is wrong.
> >> > LS doesn't have ESD clamp diodes on its outputs, and, in fact, nothing is being avalanched by applying a very current limited 20V to its outputs. Maybe an insignificant elevated leakage is all that happens. The original circuit is well-designed and should be left as is.
> >> I can see that the original circuit might work fine, but it does depend on parameters that
> >> are not specified in the data sheet like the breakdown voltage of the output pull-down
> >> transistor, so I wouldn't be comfortable calling it "well designed".
> >
> >Well I would and here's why. The ultra-fast (for its day) rise/fall times of the logic family brought transmission line effects into standard logic design. If the typical LS output gate transitioned a typical high impedance interconnecting trace to 5V, and that 5V pulse meets a high impedance input of another LS gate as its only load. The signal will be reflected 100% positively for 5V traveling back down the trace to the driver. Since the driver pulled high is high impedance, the returning pulse again is reflected positively 100% making the voltage at the driver output 10V. The new +5V transition sends a 10V edge traveling down the line to the LS input and gets clamped at 5V which is a full negative reflection to return back to the driver and reduce the 10V at the output node ideally to 5V etc. So we know for a *fact* the process has to be designed to withstand a repetitive 10V applied to the output. And that's not just withstand to survive, that's withstand with no internal
> circuit
> >disruption. Typical margins are factor of 2x or more, making a withstanding voltage of 20V a done deal, and that can be verified for the part. That's why I'm saying it's a good design.
> >
> >
> >>
> >> John
> LS has wussy pullups and is not very fast. LS is "low power schottky"
> logic. Zs is around 100 ohms and rise is slow. It won't drive a
> transmission line very hard.
>
> See fig 25. Barely any reflection overshoot, certainly not over +5.
>
> https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=&cad=rja&uact=8&ved=2ahUKEwjvpfDVgtH6AhWuKUQIHUJMA6sQFnoECDoQAQ&url=https%3A%2F%2Fwww.ti.com%2Flit%2Fpdf%2Fsdya009&usg=AOvVaw2oKKkUlZ0b2DDwfOBBKOMt
>
> So not "for a *fact*"

It's about the same speed as standard TTL but with 1/3 the power supply current draw. That used to be a big deal.

My description of overshoot was "idealized" to put it mildly.

lørdag den 8. oktober 2022 kl. 19.12.59 UTC+2 skrev Fred Bloggs:
> On Saturday, October 8, 2022 at 12:43:34 PM UTC-4, Ricky wrote:
> > On Saturday, October 8, 2022 at 11:27:51 AM UTC-4, Fred Bloggs wrote:
> > > On Friday, October 7, 2022 at 9:52:12 PM UTC-4, Ricky wrote:
> > > > On Friday, October 7, 2022 at 7:10:22 PM UTC-4, Fred Bloggs wrote:
> > > > > On Friday, October 7, 2022 at 4:41:24 PM UTC-4, John Walliker wrote:
> > > > > > On Friday, 7 October 2022 at 18:25:51 UTC+1, Fred Bloggs wrote:
> > > > > > > On Thursday, October 6, 2022 at 10:50:15 AM UTC-4, John Larkin wrote:
> > > > > > >
> > > > > > > <snip gibberish>
> > > > > > > > That's not clear. Got a schematic?
> > > > > > > > >
> > > > > > > He's wasting his time, there's nothing wrong with the original circuit.
> > > > > > >
> > > > > > > He's just one of those people who, when they can't understand something, think something is wrong.
> > > > > > > LS doesn't have ESD clamp diodes on its outputs, and, in fact, nothing is being avalanched by applying a very current limited 20V to its outputs. Maybe an insignificant elevated leakage is all that happens. The original circuit is well-designed and should be left as is.
> > > > > > I can see that the original circuit might work fine, but it does depend on parameters that
> > > > > > are not specified in the data sheet like the breakdown voltage of the output pull-down
> > > > > > transistor, so I wouldn't be comfortable calling it "well designed".
> > > > > Well I would and here's why. The ultra-fast (for its day) rise/fall times of the logic family brought transmission line effects into standard logic design. If the typical LS output gate transitioned a typical high impedance interconnecting trace to 5V, and that 5V pulse meets a high impedance input of another LS gate as its only load. The signal will be reflected 100% positively for 5V traveling back down the trace to the driver. Since the driver pulled high is high impedance, the returning pulse again is reflected positively 100% making the voltage at the driver output 10V. The new +5V transition sends a 10V edge traveling down the line to the LS input and gets clamped at 5V which is a full negative reflection to return back to the driver and reduce the 10V at the output node ideally to 5V etc. So we know for a *fact* the process has to be designed to withstand a repetitive 10V applied to the output. And that's not just withstand to survive, that's withstand with no internal circuit disruption. Typical margins are factor of 2x or more, making a withstanding voltage of 20V a done deal, and that can be verified for the part. That's why I'm saying it's a good design.
> > > > I thought I was following this ok, until I got to the point of the second wave being clamped at the LS input to the 5V rail. Is that were the case, how could the first reflection be above 5V?
> > > >
> > > > That aside, your whole description is pretty off track. The LS output driving the "high impedance" trace, does not pull up to 5V in the first place. The "high impedance" trace is not high enough to be ignored. The reality is the driver output will only drive hard to maybe 3.5V. Combine that with the trace impedance loading of around 110 ohms, and you get something like a 2V initial edge on the trace. This will be doubled at the far end reflection at the LS input, to about 4V. So there's no need to worry about over voltage from reflections.
> > > Not going to get into those details. Theoretically your 4V return pulse would get doubled to 8V at the LS OUT pin, but it doesn't, and here's why. When the LS totem pole gets pushed into back bias, its current is immediately cut off, inducing the superposition of a 2.0V negative going pulse on the line. So the 4V incoming combined with that gets you back to your original 2V, and then the load sees a negative 2V step one line length delay later.
> > Except this is not what is seen. If the line at the receiver spent any time at 2V, we would see all manner of misbehavior in the circuit. Imagine this being a clock line or an edge sensitive chip enable.
> > > Stuff like shows why you're okay using unterminated lines most of the time for combinatorial inputs- it's the clocked inputs that are the weak link, unterminated line reflections cause the infamous glitchy double clocking problems. TTL drive levels are too weak for a DC termination but they're good enough for an AC termination. The AC termination is a series R+C shunting the line to signal COM at the load. The R is the interconnecting trace/wire characteristic impedance, and C is selected for an RC time constant equal to signal transition time. That one works pretty well. It's only needed in extreme situations where the line has to be run over 18" or so for some reason.
> > Funny, I've worked on tons of TTL circuits that were not terminated and had no problems with glitchy clocks. Well, maybe not tons, but at least many pounds.
> What's funny is that you're so knowledgeable on the basis of such limited experience. Try using signal coming in over a cable LPT port for clocks. There an AC termination into a Schmitt is advisable.
> >
> > It was always the ECL that required termination. But talk about power dissipation! Whew! We had machines that could overheat a high bay factory just from running the machines! The air conditioners were not designed to run in the winter, so we had to open doors.
> The design rules were to use termination on distances greater than 0.8-1.4 inch depending on family- and that was to keep reflection below 20%. Terminations to 2V were the norm, and the 82/130 Thevenin split for 50R was pretty common. That adds up to a lot of current draw.

1 inch of trace is a few hundred picoseconds

On Saturday, October 8, 2022 at 1:22:23 PM UTC-4, lang...@fonz.dk wrote:
> lørdag den 8. oktober 2022 kl. 19.12.59 UTC+2 skrev Fred Bloggs:
> > On Saturday, October 8, 2022 at 12:43:34 PM UTC-4, Ricky wrote:
> > > On Saturday, October 8, 2022 at 11:27:51 AM UTC-4, Fred Bloggs wrote:
> > > > On Friday, October 7, 2022 at 9:52:12 PM UTC-4, Ricky wrote:
> > > > > On Friday, October 7, 2022 at 7:10:22 PM UTC-4, Fred Bloggs wrote:
> > > > > > On Friday, October 7, 2022 at 4:41:24 PM UTC-4, John Walliker wrote:
> > > > > > > On Friday, 7 October 2022 at 18:25:51 UTC+1, Fred Bloggs wrote:
> > > > > > > > On Thursday, October 6, 2022 at 10:50:15 AM UTC-4, John Larkin wrote:
> > > > > > > >
> > > > > > > > <snip gibberish>
> > > > > > > > > That's not clear. Got a schematic?
> > > > > > > > > >
> > > > > > > > He's wasting his time, there's nothing wrong with the original circuit.
> > > > > > > >
> > > > > > > > He's just one of those people who, when they can't understand something, think something is wrong.
> > > > > > > > LS doesn't have ESD clamp diodes on its outputs, and, in fact, nothing is being avalanched by applying a very current limited 20V to its outputs. Maybe an insignificant elevated leakage is all that happens. The original circuit is well-designed and should be left as is.
> > > > > > > I can see that the original circuit might work fine, but it does depend on parameters that
> > > > > > > are not specified in the data sheet like the breakdown voltage of the output pull-down
> > > > > > > transistor, so I wouldn't be comfortable calling it "well designed".
> > > > > > Well I would and here's why. The ultra-fast (for its day) rise/fall times of the logic family brought transmission line effects into standard logic design. If the typical LS output gate transitioned a typical high impedance interconnecting trace to 5V, and that 5V pulse meets a high impedance input of another LS gate as its only load. The signal will be reflected 100% positively for 5V traveling back down the trace to the driver. Since the driver pulled high is high impedance, the returning pulse again is reflected positively 100% making the voltage at the driver output 10V. The new +5V transition sends a 10V edge traveling down the line to the LS input and gets clamped at 5V which is a full negative reflection to return back to the driver and reduce the 10V at the output node ideally to 5V etc. So we know for a *fact* the process has to be designed to withstand a repetitive 10V applied to the output. And that's not just withstand to survive, that's withstand with no internal circuit disruption. Typical margins are factor of 2x or more, making a withstanding voltage of 20V a done deal, and that can be verified for the part. That's why I'm saying it's a good design.
> > > > > I thought I was following this ok, until I got to the point of the second wave being clamped at the LS input to the 5V rail. Is that were the case, how could the first reflection be above 5V?
> > > > >
> > > > > That aside, your whole description is pretty off track. The LS output driving the "high impedance" trace, does not pull up to 5V in the first place. The "high impedance" trace is not high enough to be ignored. The reality is the driver output will only drive hard to maybe 3.5V. Combine that with the trace impedance loading of around 110 ohms, and you get something like a 2V initial edge on the trace. This will be doubled at the far end reflection at the LS input, to about 4V. So there's no need to worry about over voltage from reflections.
> > > > Not going to get into those details. Theoretically your 4V return pulse would get doubled to 8V at the LS OUT pin, but it doesn't, and here's why. When the LS totem pole gets pushed into back bias, its current is immediately cut off, inducing the superposition of a 2.0V negative going pulse on the line. So the 4V incoming combined with that gets you back to your original 2V, and then the load sees a negative 2V step one line length delay later.
> > > Except this is not what is seen. If the line at the receiver spent any time at 2V, we would see all manner of misbehavior in the circuit. Imagine this being a clock line or an edge sensitive chip enable.
> > > > Stuff like shows why you're okay using unterminated lines most of the time for combinatorial inputs- it's the clocked inputs that are the weak link, unterminated line reflections cause the infamous glitchy double clocking problems. TTL drive levels are too weak for a DC termination but they're good enough for an AC termination. The AC termination is a series R+C shunting the line to signal COM at the load. The R is the interconnecting trace/wire characteristic impedance, and C is selected for an RC time constant equal to signal transition time. That one works pretty well. It's only needed in extreme situations where the line has to be run over 18" or so for some reason.
> > > Funny, I've worked on tons of TTL circuits that were not terminated and had no problems with glitchy clocks. Well, maybe not tons, but at least many pounds.
> > What's funny is that you're so knowledgeable on the basis of such limited experience. Try using signal coming in over a cable LPT port for clocks. There an AC termination into a Schmitt is advisable.
> > >
> > > It was always the ECL that required termination. But talk about power dissipation! Whew! We had machines that could overheat a high bay factory just from running the machines! The air conditioners were not designed to run in the winter, so we had to open doors.
> > The design rules were to use termination on distances greater than 0.8-1.4 inch depending on family- and that was to keep reflection below 20%. Terminations to 2V were the norm, and the 82/130 Thevenin split for 50R was pretty common. That adds up to a lot of current draw.
> 1 inch of trace is a few hundred picoseconds

I was surprised by it too, but that was the Motorola official recommendation.

lørdag den 8. oktober 2022 kl. 19.14.05 UTC+2 skrev John Larkin:
> On Thu, 6 Oct 2022 14:31:36 -0400, Phil Hobbs
> <pcdhSpamM...@electrooptical.net> wrote:
>
> >Lasse Langwadt Christensen wrote:
> >> torsdag den 6. oktober 2022 kl. 20.04.09 UTC+2 skrev Phil Hobbs:
> >>> Lasse Langwadt Christensen wrote:
> >>>> torsdag den 6. oktober 2022 kl. 18.51.13 UTC+2 skrev Phil Hobbs:
> >>>>> John Robertson wrote:
> >>>>>> On 2022/10/06 4:41 a.m., Phil Hobbs wrote:
> >>>>>>> John Robertson wrote:
> >>>>>>>> Have a circuit that needs repair. Uses a TIP125 (NPN, Darlington)
> >>>>>>>> emitter tied to Vbb (~20VDC). Collector to load, then to ground. 1K
> >>>>>>>> resistor (R1) pullup on Base to Vbb, and a second 1KR (R2) to the TTL
> >>>>>>>> controller.
> >>>>>>>>
> >>>>>>>> Problem is of course, that R2 puts the ~20VDC to the TTL output gate
> >>>>>>>> on a 74LS138.
> >>>>>>>>
> >>>>>>>> Trying to solve this without a driver transistor. The circuit is for
> >>>>>>>> a 1ms ~20V strobe pulse repeated every ten ms.
> >>>>>>>>
> >>>>>>>> I thought of putting a 10ufd cap in series with R2, but don't like
> >>>>>>>> electrolytics as they fail after a few thousand hours.
> >>>>>>>>
> >>>>>>>> Possible to use a 15V or so Zener Diode, but the Vbb is not regulated
> >>>>>>>> so that won't work reliably.
> >>>>>>>>
> >>>>>>>> Anyone have a single component in mind that will essentially emulate
> >>>>>>>> (isolate) an Open-Collector output for the 138?
> >>>>>>>>
> >>>>>>>> Thanks!
> >>>>>>>>
> >>>>>>>> John :-#)#
> >>>>>>>>
> >>>>>>> Switch it to a 139 and use a 2N7002?
> >>>>>>>
> >>>>>>> Cheers
> >>>>>>>
> >>>>>>> Phil Hobbs
> >>>>>>>
> >>>>>>
> >>>>>> Well, this is to fix 5 x PCBs we are stuck with at the moment, next run
> >>>>>> will fix the drives - either 7445s or 138 with P-Channel MOSFETs and
> >>>>>> drivers.
> >>>>>>
> >>>>>> Circuit I am trying to fix with fewest components - one x two legged
> >>>>>> device preferred per 138 output:
> >>>>>>
> >>>>>> https://www.flippers.com/images/delete/74LS138_Lamp_Driver.png
> >>>>>>
> >>>>>> VLAMP is roughly 20VDC.
> >>>>>>
> >>>>>> Thanks,
> >>>>>>
> >>>>>> John :-#)#
> >>>>> The MOSFET cascode thing is pretty good actually, if you put a diode to
> >>>>> the supply or want to live dangerously and rely on the ESD protection to
> >>>>> discharge the gate. If it's a matter of using the boards or tossing
> >>>>> them, there's not much to lose by using barefoot FETs.
> >>>>>
> >>>>
> >>>> '138 is push-pull, though very wimpy high side
> >>>>
> >>> Sure, but anything above +4ish reverse-biases the upper output transistor.
> >>> Cheers
> >>
> >> with the upper transistor on does it ever get there?
> >>
> >>
> >
> >Sure, it's an NPN emitter. If it were a NFET, it would be fine.
> >
> >Cheers
> >
> >Phil Hobbs
>
> LS has a darlington with 110 ohms in the drain and probably no ESD
> diode to +5.
>
> It's shocking how poorly specified all those old TTL parts were.
> Modern logic isn't much better. We have to measure stuff like Zout and
> rise/fall times. Sometimes the results are startling.

it should be in the IBIS file

On Saturday, October 8, 2022 at 1:22:23 PM UTC-4, lang...@fonz.dk wrote:
> lørdag den 8. oktober 2022 kl. 19.12.59 UTC+2 skrev Fred Bloggs:
> > On Saturday, October 8, 2022 at 12:43:34 PM UTC-4, Ricky wrote:
> > > On Saturday, October 8, 2022 at 11:27:51 AM UTC-4, Fred Bloggs wrote:
> > > > On Friday, October 7, 2022 at 9:52:12 PM UTC-4, Ricky wrote:
> > > > > On Friday, October 7, 2022 at 7:10:22 PM UTC-4, Fred Bloggs wrote:
> > > > > > On Friday, October 7, 2022 at 4:41:24 PM UTC-4, John Walliker wrote:
> > > > > > > On Friday, 7 October 2022 at 18:25:51 UTC+1, Fred Bloggs wrote:
> > > > > > > > On Thursday, October 6, 2022 at 10:50:15 AM UTC-4, John Larkin wrote:
> > > > > > > >
> > > > > > > > <snip gibberish>
> > > > > > > > > That's not clear. Got a schematic?
> > > > > > > > > >
> > > > > > > > He's wasting his time, there's nothing wrong with the original circuit.
> > > > > > > >
> > > > > > > > He's just one of those people who, when they can't understand something, think something is wrong.
> > > > > > > > LS doesn't have ESD clamp diodes on its outputs, and, in fact, nothing is being avalanched by applying a very current limited 20V to its outputs. Maybe an insignificant elevated leakage is all that happens. The original circuit is well-designed and should be left as is.
> > > > > > > I can see that the original circuit might work fine, but it does depend on parameters that
> > > > > > > are not specified in the data sheet like the breakdown voltage of the output pull-down
> > > > > > > transistor, so I wouldn't be comfortable calling it "well designed".
> > > > > > Well I would and here's why. The ultra-fast (for its day) rise/fall times of the logic family brought transmission line effects into standard logic design. If the typical LS output gate transitioned a typical high impedance interconnecting trace to 5V, and that 5V pulse meets a high impedance input of another LS gate as its only load. The signal will be reflected 100% positively for 5V traveling back down the trace to the driver. Since the driver pulled high is high impedance, the returning pulse again is reflected positively 100% making the voltage at the driver output 10V. The new +5V transition sends a 10V edge traveling down the line to the LS input and gets clamped at 5V which is a full negative reflection to return back to the driver and reduce the 10V at the output node ideally to 5V etc. So we know for a *fact* the process has to be designed to withstand a repetitive 10V applied to the output. And that's not just withstand to survive, that's withstand with no internal circuit disruption. Typical margins are factor of 2x or more, making a withstanding voltage of 20V a done deal, and that can be verified for the part. That's why I'm saying it's a good design.
> > > > > I thought I was following this ok, until I got to the point of the second wave being clamped at the LS input to the 5V rail. Is that were the case, how could the first reflection be above 5V?
> > > > >
> > > > > That aside, your whole description is pretty off track. The LS output driving the "high impedance" trace, does not pull up to 5V in the first place. The "high impedance" trace is not high enough to be ignored. The reality is the driver output will only drive hard to maybe 3.5V. Combine that with the trace impedance loading of around 110 ohms, and you get something like a 2V initial edge on the trace. This will be doubled at the far end reflection at the LS input, to about 4V. So there's no need to worry about over voltage from reflections.
> > > > Not going to get into those details. Theoretically your 4V return pulse would get doubled to 8V at the LS OUT pin, but it doesn't, and here's why. When the LS totem pole gets pushed into back bias, its current is immediately cut off, inducing the superposition of a 2.0V negative going pulse on the line. So the 4V incoming combined with that gets you back to your original 2V, and then the load sees a negative 2V step one line length delay later.
> > > Except this is not what is seen. If the line at the receiver spent any time at 2V, we would see all manner of misbehavior in the circuit. Imagine this being a clock line or an edge sensitive chip enable.
> > > > Stuff like shows why you're okay using unterminated lines most of the time for combinatorial inputs- it's the clocked inputs that are the weak link, unterminated line reflections cause the infamous glitchy double clocking problems. TTL drive levels are too weak for a DC termination but they're good enough for an AC termination. The AC termination is a series R+C shunting the line to signal COM at the load. The R is the interconnecting trace/wire characteristic impedance, and C is selected for an RC time constant equal to signal transition time. That one works pretty well. It's only needed in extreme situations where the line has to be run over 18" or so for some reason.
> > > Funny, I've worked on tons of TTL circuits that were not terminated and had no problems with glitchy clocks. Well, maybe not tons, but at least many pounds.
> > What's funny is that you're so knowledgeable on the basis of such limited experience. Try using signal coming in over a cable LPT port for clocks. There an AC termination into a Schmitt is advisable.
> > >
> > > It was always the ECL that required termination. But talk about power dissipation! Whew! We had machines that could overheat a high bay factory just from running the machines! The air conditioners were not designed to run in the winter, so we had to open doors.
> > The design rules were to use termination on distances greater than 0.8-1.4 inch depending on family- and that was to keep reflection below 20%. Terminations to 2V were the norm, and the 82/130 Thevenin split for 50R was pretty common. That adds up to a lot of current draw.
> 1 inch of trace is a few hundred picoseconds

Guess I should add that recommendation was for the DIP packaging for which lead inductance was significant. It may not apply to the surface mount package.

On Saturday, October 8, 2022 at 1:14:05 PM UTC-4, John Larkin wrote:
> On Thu, 6 Oct 2022 14:31:36 -0400, Phil Hobbs
> <pcdhSpamM...@electrooptical.net> wrote:
>
> >Lasse Langwadt Christensen wrote:
> >> torsdag den 6. oktober 2022 kl. 20.04.09 UTC+2 skrev Phil Hobbs:
> >>> Lasse Langwadt Christensen wrote:
> >>>> torsdag den 6. oktober 2022 kl. 18.51.13 UTC+2 skrev Phil Hobbs:
> >>>>> John Robertson wrote:
> >>>>>> On 2022/10/06 4:41 a.m., Phil Hobbs wrote:
> >>>>>>> John Robertson wrote:
> >>>>>>>> Have a circuit that needs repair. Uses a TIP125 (NPN, Darlington)
> >>>>>>>> emitter tied to Vbb (~20VDC). Collector to load, then to ground. 1K
> >>>>>>>> resistor (R1) pullup on Base to Vbb, and a second 1KR (R2) to the TTL
> >>>>>>>> controller.
> >>>>>>>>
> >>>>>>>> Problem is of course, that R2 puts the ~20VDC to the TTL output gate
> >>>>>>>> on a 74LS138.
> >>>>>>>>
> >>>>>>>> Trying to solve this without a driver transistor. The circuit is for
> >>>>>>>> a 1ms ~20V strobe pulse repeated every ten ms.
> >>>>>>>>
> >>>>>>>> I thought of putting a 10ufd cap in series with R2, but don't like
> >>>>>>>> electrolytics as they fail after a few thousand hours.
> >>>>>>>>
> >>>>>>>> Possible to use a 15V or so Zener Diode, but the Vbb is not regulated
> >>>>>>>> so that won't work reliably.
> >>>>>>>>
> >>>>>>>> Anyone have a single component in mind that will essentially emulate
> >>>>>>>> (isolate) an Open-Collector output for the 138?
> >>>>>>>>
> >>>>>>>> Thanks!
> >>>>>>>>
> >>>>>>>> John :-#)#
> >>>>>>>>
> >>>>>>> Switch it to a 139 and use a 2N7002?
> >>>>>>>
> >>>>>>> Cheers
> >>>>>>>
> >>>>>>> Phil Hobbs
> >>>>>>>
> >>>>>>
> >>>>>> Well, this is to fix 5 x PCBs we are stuck with at the moment, next run
> >>>>>> will fix the drives - either 7445s or 138 with P-Channel MOSFETs and
> >>>>>> drivers.
> >>>>>>
> >>>>>> Circuit I am trying to fix with fewest components - one x two legged
> >>>>>> device preferred per 138 output:
> >>>>>>
> >>>>>> https://www.flippers.com/images/delete/74LS138_Lamp_Driver.png
> >>>>>>
> >>>>>> VLAMP is roughly 20VDC.
> >>>>>>
> >>>>>> Thanks,
> >>>>>>
> >>>>>> John :-#)#
> >>>>> The MOSFET cascode thing is pretty good actually, if you put a diode to
> >>>>> the supply or want to live dangerously and rely on the ESD protection to
> >>>>> discharge the gate. If it's a matter of using the boards or tossing
> >>>>> them, there's not much to lose by using barefoot FETs.
> >>>>>
> >>>>
> >>>> '138 is push-pull, though very wimpy high side
> >>>>
> >>> Sure, but anything above +4ish reverse-biases the upper output transistor.
> >>> Cheers
> >>
> >> with the upper transistor on does it ever get there?
> >>
> >>
> >
> >Sure, it's an NPN emitter. If it were a NFET, it would be fine.
> >
> >Cheers
> >
> >Phil Hobbs
>
> LS has a darlington with 110 ohms in the drain and probably no ESD
> diode to +5.

It's much more than that. It's the so-called totem-pole optimized for switching which mainly meant low impedance circuit paths for quick base saturation discharge and preventing shoot- through spiking.

>
> It's shocking how poorly specified all those old TTL parts were.
> Modern logic isn't much better. We have to measure stuff like Zout and
> rise/fall times. Sometimes the results are startling.
>
> We just yesterday decided that an efinix FPGA output was a pretty good
> 50 ohm source termination, so made the traces 50 ohms and deleted some
> r-packs.

On Saturday, October 8, 2022 at 1:12:59 PM UTC-4, Fred Bloggs wrote:
> On Saturday, October 8, 2022 at 12:43:34 PM UTC-4, Ricky wrote:
> > On Saturday, October 8, 2022 at 11:27:51 AM UTC-4, Fred Bloggs wrote:
> > > On Friday, October 7, 2022 at 9:52:12 PM UTC-4, Ricky wrote:
> > > > On Friday, October 7, 2022 at 7:10:22 PM UTC-4, Fred Bloggs wrote:
> > > > > On Friday, October 7, 2022 at 4:41:24 PM UTC-4, John Walliker wrote:
> > > > > > On Friday, 7 October 2022 at 18:25:51 UTC+1, Fred Bloggs wrote:
> > > > > > > On Thursday, October 6, 2022 at 10:50:15 AM UTC-4, John Larkin wrote:
> > > > > > >
> > > > > > > <snip gibberish>
> > > > > > > > That's not clear. Got a schematic?
> > > > > > > > >
> > > > > > > He's wasting his time, there's nothing wrong with the original circuit.
> > > > > > >
> > > > > > > He's just one of those people who, when they can't understand something, think something is wrong.
> > > > > > > LS doesn't have ESD clamp diodes on its outputs, and, in fact, nothing is being avalanched by applying a very current limited 20V to its outputs. Maybe an insignificant elevated leakage is all that happens. The original circuit is well-designed and should be left as is.
> > > > > > I can see that the original circuit might work fine, but it does depend on parameters that
> > > > > > are not specified in the data sheet like the breakdown voltage of the output pull-down
> > > > > > transistor, so I wouldn't be comfortable calling it "well designed".
> > > > > Well I would and here's why. The ultra-fast (for its day) rise/fall times of the logic family brought transmission line effects into standard logic design. If the typical LS output gate transitioned a typical high impedance interconnecting trace to 5V, and that 5V pulse meets a high impedance input of another LS gate as its only load. The signal will be reflected 100% positively for 5V traveling back down the trace to the driver. Since the driver pulled high is high impedance, the returning pulse again is reflected positively 100% making the voltage at the driver output 10V. The new +5V transition sends a 10V edge traveling down the line to the LS input and gets clamped at 5V which is a full negative reflection to return back to the driver and reduce the 10V at the output node ideally to 5V etc. So we know for a *fact* the process has to be designed to withstand a repetitive 10V applied to the output. And that's not just withstand to survive, that's withstand with no internal circuit disruption. Typical margins are factor of 2x or more, making a withstanding voltage of 20V a done deal, and that can be verified for the part. That's why I'm saying it's a good design.
> > > > I thought I was following this ok, until I got to the point of the second wave being clamped at the LS input to the 5V rail. Is that were the case, how could the first reflection be above 5V?
> > > >
> > > > That aside, your whole description is pretty off track. The LS output driving the "high impedance" trace, does not pull up to 5V in the first place. The "high impedance" trace is not high enough to be ignored. The reality is the driver output will only drive hard to maybe 3.5V. Combine that with the trace impedance loading of around 110 ohms, and you get something like a 2V initial edge on the trace. This will be doubled at the far end reflection at the LS input, to about 4V. So there's no need to worry about over voltage from reflections.
> > > Not going to get into those details. Theoretically your 4V return pulse would get doubled to 8V at the LS OUT pin, but it doesn't, and here's why. When the LS totem pole gets pushed into back bias, its current is immediately cut off, inducing the superposition of a 2.0V negative going pulse on the line. So the 4V incoming combined with that gets you back to your original 2V, and then the load sees a negative 2V step one line length delay later.
> > Except this is not what is seen. If the line at the receiver spent any time at 2V, we would see all manner of misbehavior in the circuit. Imagine this being a clock line or an edge sensitive chip enable.
> > > Stuff like shows why you're okay using unterminated lines most of the time for combinatorial inputs- it's the clocked inputs that are the weak link, unterminated line reflections cause the infamous glitchy double clocking problems. TTL drive levels are too weak for a DC termination but they're good enough for an AC termination. The AC termination is a series R+C shunting the line to signal COM at the load. The R is the interconnecting trace/wire characteristic impedance, and C is selected for an RC time constant equal to signal transition time. That one works pretty well. It's only needed in extreme situations where the line has to be run over 18" or so for some reason.
> > Funny, I've worked on tons of TTL circuits that were not terminated and had no problems with glitchy clocks. Well, maybe not tons, but at least many pounds.
> What's funny is that you're so knowledgeable on the basis of such limited experience. Try using signal coming in over a cable LPT port for clocks. There an AC termination into a Schmitt is advisable.

LOL, I see why Bill gives you such a hard time. You deserve it. Sure, you can construct any of a dozen scenarios where termination might be needed. Your prior posts didn't talk about those. You blame it all on the inherent structure of the LSTTL output stage. So this one is BUSTED!

--

Rick C.

+-- Get 1,000 miles of free Supercharging
+-- Tesla referral code - https://ts.la/richard11209

On Saturday, October 8, 2022 at 2:04:43 PM UTC-4, Ricky wrote:
> On Saturday, October 8, 2022 at 1:12:59 PM UTC-4, Fred Bloggs wrote:
> > On Saturday, October 8, 2022 at 12:43:34 PM UTC-4, Ricky wrote:
> > > On Saturday, October 8, 2022 at 11:27:51 AM UTC-4, Fred Bloggs wrote:
> > > > On Friday, October 7, 2022 at 9:52:12 PM UTC-4, Ricky wrote:
> > > > > On Friday, October 7, 2022 at 7:10:22 PM UTC-4, Fred Bloggs wrote:
> > > > > > On Friday, October 7, 2022 at 4:41:24 PM UTC-4, John Walliker wrote:
> > > > > > > On Friday, 7 October 2022 at 18:25:51 UTC+1, Fred Bloggs wrote:
> > > > > > > > On Thursday, October 6, 2022 at 10:50:15 AM UTC-4, John Larkin wrote:
> > > > > > > >
> > > > > > > > <snip gibberish>
> > > > > > > > > That's not clear. Got a schematic?
> > > > > > > > > >
> > > > > > > > He's wasting his time, there's nothing wrong with the original circuit.
> > > > > > > >
> > > > > > > > He's just one of those people who, when they can't understand something, think something is wrong.
> > > > > > > > LS doesn't have ESD clamp diodes on its outputs, and, in fact, nothing is being avalanched by applying a very current limited 20V to its outputs. Maybe an insignificant elevated leakage is all that happens. The original circuit is well-designed and should be left as is.
> > > > > > > I can see that the original circuit might work fine, but it does depend on parameters that
> > > > > > > are not specified in the data sheet like the breakdown voltage of the output pull-down
> > > > > > > transistor, so I wouldn't be comfortable calling it "well designed".
> > > > > > Well I would and here's why. The ultra-fast (for its day) rise/fall times of the logic family brought transmission line effects into standard logic design. If the typical LS output gate transitioned a typical high impedance interconnecting trace to 5V, and that 5V pulse meets a high impedance input of another LS gate as its only load. The signal will be reflected 100% positively for 5V traveling back down the trace to the driver. Since the driver pulled high is high impedance, the returning pulse again is reflected positively 100% making the voltage at the driver output 10V. The new +5V transition sends a 10V edge traveling down the line to the LS input and gets clamped at 5V which is a full negative reflection to return back to the driver and reduce the 10V at the output node ideally to 5V etc. So we know for a *fact* the process has to be designed to withstand a repetitive 10V applied to the output. And that's not just withstand to survive, that's withstand with no internal circuit disruption. Typical margins are factor of 2x or more, making a withstanding voltage of 20V a done deal, and that can be verified for the part. That's why I'm saying it's a good design.
> > > > > I thought I was following this ok, until I got to the point of the second wave being clamped at the LS input to the 5V rail. Is that were the case, how could the first reflection be above 5V?
> > > > >
> > > > > That aside, your whole description is pretty off track. The LS output driving the "high impedance" trace, does not pull up to 5V in the first place. The "high impedance" trace is not high enough to be ignored. The reality is the driver output will only drive hard to maybe 3.5V. Combine that with the trace impedance loading of around 110 ohms, and you get something like a 2V initial edge on the trace. This will be doubled at the far end reflection at the LS input, to about 4V. So there's no need to worry about over voltage from reflections.
> > > > Not going to get into those details. Theoretically your 4V return pulse would get doubled to 8V at the LS OUT pin, but it doesn't, and here's why. When the LS totem pole gets pushed into back bias, its current is immediately cut off, inducing the superposition of a 2.0V negative going pulse on the line. So the 4V incoming combined with that gets you back to your original 2V, and then the load sees a negative 2V step one line length delay later.
> > > Except this is not what is seen. If the line at the receiver spent any time at 2V, we would see all manner of misbehavior in the circuit. Imagine this being a clock line or an edge sensitive chip enable.
> > > > Stuff like shows why you're okay using unterminated lines most of the time for combinatorial inputs- it's the clocked inputs that are the weak link, unterminated line reflections cause the infamous glitchy double clocking problems. TTL drive levels are too weak for a DC termination but they're good enough for an AC termination. The AC termination is a series R+C shunting the line to signal COM at the load. The R is the interconnecting trace/wire characteristic impedance, and C is selected for an RC time constant equal to signal transition time. That one works pretty well. It's only needed in extreme situations where the line has to be run over 18" or so for some reason.
> > > Funny, I've worked on tons of TTL circuits that were not terminated and had no problems with glitchy clocks. Well, maybe not tons, but at least many pounds.
> > What's funny is that you're so knowledgeable on the basis of such limited experience. Try using signal coming in over a cable LPT port for clocks. There an AC termination into a Schmitt is advisable.
> LOL, I see why Bill gives you such a hard time. You deserve it. Sure, you can construct any of a dozen scenarios where termination might be needed. Your prior posts didn't talk about those. You blame it all on the inherent structure of the LSTTL output stage. So this one is BUSTED!

Have it your way, Einstein.

>
> --
>
> Rick C.
>
> +-- Get 1,000 miles of free Supercharging
> +-- Tesla referral code - https://ts.la/richard11209

On Saturday, October 8, 2022 at 5:54:38 AM UTC-4, John Walliker wrote:
> On Saturday, 8 October 2022 at 05:07:50 UTC+1, whit3rd wrote:
> > On Friday, October 7, 2022 at 4:10:22 PM UTC-7, Fred Bloggs wrote:
> > > On Friday, October 7, 2022 at 4:41:24 PM UTC-4, John Walliker wrote:
> > > > On Friday, 7 October 2022 at 18:25:51 UTC+1, Fred Bloggs wrote:
> >
> > > > > LS doesn't have ESD clamp diodes on its outputs, and, in fact, nothing is being
> > > > >avalanched by applying a very current limited 20V to its outputs. Maybe an insignificant
> > > > >elevated leakage is all that happens. The original circuit is well-designed and should be left as is.
> >
> > > > I can see that the original circuit might work fine, but it does depend on parameters that
> > > > are not specified in the data sheet like the breakdown voltage of the output pull-down
> > > > transistor, so I wouldn't be comfortable calling it "well designed"..
> >
> > > Well I would and here's why. The ultra-fast (for its day) rise/fall times of the logic family brought
> > > transmission line effects into standard logic design. If the typical LS output gate transitioned
> > >a typical high impedance interconnecting trace to 5V, and that 5V pulse meets a high
> > >impedance input of another LS gate as its only load. The signal will be reflected 100% positively ...
> > >Typical margins are factor of 2x or more, making a withstanding voltage of 20V
> > >a done deal, and that can be verified for the part. That's why I'm saying it's a good design.
> > Actually, would substituting a 74HCT138 or 74ACT138 be a good solution?
> > There's certainly protection diodes built into its outputs (MOS body diode).
> > 74ACT138 can take 50 mA into its output pin.
> >
> > <https://www.ti.com/lit/ds/symlink/cd74act138.pdf>
> The problem with that is that the darlington would never turn off.

One of my original thoughts on the circuit was exactly that. The circuit was implementing a filament warmer to prevent exceeding the TIP-125 pulsed power limits turning on a cold filament at a relatively high voltage. The original post was pretty much devoid of enough information to look at that.

>
> John

On Sat, 8 Oct 2022 10:29:56 -0700 (PDT), Lasse Langwadt Christensen
<langwadt@fonz.dk> wrote:

>lørdag den 8. oktober 2022 kl. 19.14.05 UTC+2 skrev John Larkin:
>> On Thu, 6 Oct 2022 14:31:36 -0400, Phil Hobbs
>> <pcdhSpamM...@electrooptical.net> wrote:
>>
>> >Lasse Langwadt Christensen wrote:
>> >> torsdag den 6. oktober 2022 kl. 20.04.09 UTC+2 skrev Phil Hobbs:
>> >>> Lasse Langwadt Christensen wrote:
>> >>>> torsdag den 6. oktober 2022 kl. 18.51.13 UTC+2 skrev Phil Hobbs:
>> >>>>> John Robertson wrote:
>> >>>>>> On 2022/10/06 4:41 a.m., Phil Hobbs wrote:
>> >>>>>>> John Robertson wrote:
>> >>>>>>>> Have a circuit that needs repair. Uses a TIP125 (NPN, Darlington)
>> >>>>>>>> emitter tied to Vbb (~20VDC). Collector to load, then to ground. 1K
>> >>>>>>>> resistor (R1) pullup on Base to Vbb, and a second 1KR (R2) to the TTL
>> >>>>>>>> controller.
>> >>>>>>>>
>> >>>>>>>> Problem is of course, that R2 puts the ~20VDC to the TTL output gate
>> >>>>>>>> on a 74LS138.
>> >>>>>>>>
>> >>>>>>>> Trying to solve this without a driver transistor. The circuit is for
>> >>>>>>>> a 1ms ~20V strobe pulse repeated every ten ms.
>> >>>>>>>>
>> >>>>>>>> I thought of putting a 10ufd cap in series with R2, but don't like
>> >>>>>>>> electrolytics as they fail after a few thousand hours.
>> >>>>>>>>
>> >>>>>>>> Possible to use a 15V or so Zener Diode, but the Vbb is not regulated
>> >>>>>>>> so that won't work reliably.
>> >>>>>>>>
>> >>>>>>>> Anyone have a single component in mind that will essentially emulate
>> >>>>>>>> (isolate) an Open-Collector output for the 138?
>> >>>>>>>>
>> >>>>>>>> Thanks!
>> >>>>>>>>
>> >>>>>>>> John :-#)#
>> >>>>>>>>
>> >>>>>>> Switch it to a 139 and use a 2N7002?
>> >>>>>>>
>> >>>>>>> Cheers
>> >>>>>>>
>> >>>>>>> Phil Hobbs
>> >>>>>>>
>> >>>>>>
>> >>>>>> Well, this is to fix 5 x PCBs we are stuck with at the moment, next run
>> >>>>>> will fix the drives - either 7445s or 138 with P-Channel MOSFETs and
>> >>>>>> drivers.
>> >>>>>>
>> >>>>>> Circuit I am trying to fix with fewest components - one x two legged
>> >>>>>> device preferred per 138 output:
>> >>>>>>
>> >>>>>> https://www.flippers.com/images/delete/74LS138_Lamp_Driver.png
>> >>>>>>
>> >>>>>> VLAMP is roughly 20VDC.
>> >>>>>>
>> >>>>>> Thanks,
>> >>>>>>
>> >>>>>> John :-#)#
>> >>>>> The MOSFET cascode thing is pretty good actually, if you put a diode to
>> >>>>> the supply or want to live dangerously and rely on the ESD protection to
>> >>>>> discharge the gate. If it's a matter of using the boards or tossing
>> >>>>> them, there's not much to lose by using barefoot FETs.
>> >>>>>
>> >>>>
>> >>>> '138 is push-pull, though very wimpy high side
>> >>>>
>> >>> Sure, but anything above +4ish reverse-biases the upper output transistor.
>> >>> Cheers
>> >>
>> >> with the upper transistor on does it ever get there?
>> >>
>> >>
>> >
>> >Sure, it's an NPN emitter. If it were a NFET, it would be fine.
>> >
>> >Cheers
>> >
>> >Phil Hobbs
>>
>> LS has a darlington with 110 ohms in the drain and probably no ESD
>> diode to +5.
>>
>> It's shocking how poorly specified all those old TTL parts were.
>> Modern logic isn't much better. We have to measure stuff like Zout and
>> rise/fall times. Sometimes the results are startling.
>
>it should be in the IBIS file

It's quicker and funner to measure. More believable too.

https://www.dropbox.com/sh/mjrpofcgwgkhyc4/AABdMuqHdBNRcUOMZzCE-CT2a?dl=0

https://www.dropbox.com/sh/gyn0nz486fmqp1s/AAB5kwDWJ1VR8EXMjGRHs4iEa?dl=0

That NC7SV74 rise time was really unexpected. There must be a use for
that.

The actual data setup time is not specified.

On Saturday, October 8, 2022 at 2:54:38 AM UTC-7, John Walliker wrote:
> On Saturday, 8 October 2022 at 05:07:50 UTC+1, whit3rd wrote:
> > On Friday, October 7, 2022 at 4:10:22 PM UTC-7, Fred Bloggs wrote:
> > > On Friday, October 7, 2022 at 4:41:24 PM UTC-4, John Walliker wrote:
> > > > On Friday, 7 October 2022 at 18:25:51 UTC+1, Fred Bloggs wrote:
> >
> > > > > LS doesn't have ESD clamp diodes on its outputs, and, in fact, nothing is being
> > > > >avalanched by applying a very current limited 20V to its outputs. Maybe an insignificant
> > > > >elevated leakage is all that happens. The original circuit is well-designed and should be left as is.
> >
> > > > I can see that the original circuit might work fine, but it does depend on parameters that
> > > > are not specified in the data sheet like the breakdown voltage of the output pull-down
> > > > transistor, so I wouldn't be comfortable calling it "well designed".
....
> > >Typical margins are factor of 2x or more, making a withstanding voltage of 20V
> > >a done deal, and that can be verified for the part. That's why I'm saying it's a good design.
> > Actually, would substituting a 74HCT138 or 74ACT138 be a good solution?
> > There's certainly protection diodes built into its outputs (MOS body diode).
> > 74ACT138 can take 50 mA into its output pin.
> >
> > <https://www.ti.com/lit/ds/symlink/cd74act138.pdf>

> The problem with that is that the darlington would never turn off.

Yeah, you still need to do the cascode thing. It does solve the maybe-feedthrough-happens
concerns Phil was raising.

On Saturday, October 8, 2022 at 3:08:22 PM UTC-4, John Larkin wrote:
> On Sat, 8 Oct 2022 10:29:56 -0700 (PDT), Lasse Langwadt Christensen
> <lang...@fonz.dk> wrote:
>
> >lørdag den 8. oktober 2022 kl. 19.14.05 UTC+2 skrev John Larkin:
> >> On Thu, 6 Oct 2022 14:31:36 -0400, Phil Hobbs
> >> <pcdhSpamM...@electrooptical.net> wrote:
> >>
> >> >Lasse Langwadt Christensen wrote:
> >> >> torsdag den 6. oktober 2022 kl. 20.04.09 UTC+2 skrev Phil Hobbs:
> >> >>> Lasse Langwadt Christensen wrote:
> >> >>>> torsdag den 6. oktober 2022 kl. 18.51.13 UTC+2 skrev Phil Hobbs:
> >> >>>>> John Robertson wrote:
> >> >>>>>> On 2022/10/06 4:41 a.m., Phil Hobbs wrote:
> >> >>>>>>> John Robertson wrote:
> >> >>>>>>>> Have a circuit that needs repair. Uses a TIP125 (NPN, Darlington)
> >> >>>>>>>> emitter tied to Vbb (~20VDC). Collector to load, then to ground. 1K
> >> >>>>>>>> resistor (R1) pullup on Base to Vbb, and a second 1KR (R2) to the TTL
> >> >>>>>>>> controller.
> >> >>>>>>>>
> >> >>>>>>>> Problem is of course, that R2 puts the ~20VDC to the TTL output gate
> >> >>>>>>>> on a 74LS138.
> >> >>>>>>>>
> >> >>>>>>>> Trying to solve this without a driver transistor. The circuit is for
> >> >>>>>>>> a 1ms ~20V strobe pulse repeated every ten ms.
> >> >>>>>>>>
> >> >>>>>>>> I thought of putting a 10ufd cap in series with R2, but don't like
> >> >>>>>>>> electrolytics as they fail after a few thousand hours.
> >> >>>>>>>>
> >> >>>>>>>> Possible to use a 15V or so Zener Diode, but the Vbb is not regulated
> >> >>>>>>>> so that won't work reliably.
> >> >>>>>>>>
> >> >>>>>>>> Anyone have a single component in mind that will essentially emulate
> >> >>>>>>>> (isolate) an Open-Collector output for the 138?
> >> >>>>>>>>
> >> >>>>>>>> Thanks!
> >> >>>>>>>>
> >> >>>>>>>> John :-#)#
> >> >>>>>>>>
> >> >>>>>>> Switch it to a 139 and use a 2N7002?
> >> >>>>>>>
> >> >>>>>>> Cheers
> >> >>>>>>>
> >> >>>>>>> Phil Hobbs
> >> >>>>>>>
> >> >>>>>>
> >> >>>>>> Well, this is to fix 5 x PCBs we are stuck with at the moment, next run
> >> >>>>>> will fix the drives - either 7445s or 138 with P-Channel MOSFETs and
> >> >>>>>> drivers.
> >> >>>>>>
> >> >>>>>> Circuit I am trying to fix with fewest components - one x two legged
> >> >>>>>> device preferred per 138 output:
> >> >>>>>>
> >> >>>>>> https://www.flippers.com/images/delete/74LS138_Lamp_Driver.png
> >> >>>>>>
> >> >>>>>> VLAMP is roughly 20VDC.
> >> >>>>>>
> >> >>>>>> Thanks,
> >> >>>>>>
> >> >>>>>> John :-#)#
> >> >>>>> The MOSFET cascode thing is pretty good actually, if you put a diode to
> >> >>>>> the supply or want to live dangerously and rely on the ESD protection to
> >> >>>>> discharge the gate. If it's a matter of using the boards or tossing
> >> >>>>> them, there's not much to lose by using barefoot FETs.
> >> >>>>>
> >> >>>>
> >> >>>> '138 is push-pull, though very wimpy high side
> >> >>>>
> >> >>> Sure, but anything above +4ish reverse-biases the upper output transistor.
> >> >>> Cheers
> >> >>
> >> >> with the upper transistor on does it ever get there?
> >> >>
> >> >>
> >> >
> >> >Sure, it's an NPN emitter. If it were a NFET, it would be fine.
> >> >
> >> >Cheers
> >> >
> >> >Phil Hobbs
> >>
> >> LS has a darlington with 110 ohms in the drain and probably no ESD
> >> diode to +5.
> >>
> >> It's shocking how poorly specified all those old TTL parts were.
> >> Modern logic isn't much better. We have to measure stuff like Zout and
> >> rise/fall times. Sometimes the results are startling.
> >
> >it should be in the IBIS file
> It's quicker and funner to measure. More believable too.
>
> https://www.dropbox.com/sh/mjrpofcgwgkhyc4/AABdMuqHdBNRcUOMZzCE-CT2a?dl=0
>
> https://www.dropbox.com/sh/gyn0nz486fmqp1s/AAB5kwDWJ1VR8EXMjGRHs4iEa?dl=0
>
> That NC7SV74 rise time was really unexpected. There must be a use for
> that.

Well you have much more attenuation, and probably overcompensation, than in the 10EP setup. If the scope Cin is 3pF then anything more than 50/300x or 0.5pF across the series 300R is an overcompensation ( and ringing). You say it's a "CC type"- meaning a carbon composition I presume.

For the 10EP08 differential, it would be interesting to see your common mode transient measurement setup for that output. It's so brief nothing will respond to it anyway.

>
> The actual data setup time is not specified.

On 2022/10/07 10:25 a.m., Fred Bloggs wrote:
> On Thursday, October 6, 2022 at 10:50:15 AM UTC-4, John Larkin wrote:
>
> <snip gibberish>
>
>> That's not clear. Got a schematic?
>>>
>
> He's wasting his time, there's nothing wrong with the original circuit.
>
> He's just one of those people who, when they can't understand something, think something is wrong.
> LS doesn't have ESD clamp diodes on its outputs, and, in fact, nothing is being avalanched by applying a very current limited 20V to its outputs. Maybe an insignificant elevated leakage is all that happens. The original circuit is well-designed and should be left as is.

The 'original circuit' doesn't work. It was a modification of the actual
original design (which used a 7445) from the 70s.

The designer forgot that the 48s were open collector and figured a 138
would work fine. It doesn't as the outputs won't go over Vcc (5V) and
the TIPs require higher voltage to switch in this circuit. We are going
back to the 7445 as a working solution as it is the simplest answer and
the number of boards to be made is likely under 100 for the lifetime
production. Looked at other solutions and that was the easiest in terms
of real estate and cost.

If the board sells more than 50 or so, chances are it will be totally
redone and MOSFETs, GALs, etc will be added to bring it more up to date
and simplify it further.

John :-#)#
--
(Please post followups or tech inquiries to the USENET newsgroup)
John's Jukes Ltd.
MOVED to #7 - 3979 Marine Way, Burnaby, BC, Canada V5J 5E3
(604)872-5757 (Pinballs, Jukes, Video Games)
www.flippers.com
"Old pinballers never die, they just flip out."

On 2022-10-07, whit3rd <whit3rd@gmail.com> wrote:
> On Thursday, October 6, 2022 at 9:30:55 PM UTC-7, Jasen Betts wrote:
>> On 2022-10-06, John Robertson <j...@flippers.com> wrote:
>> > Have a circuit that needs repair. Uses a TIP125 (NPN, Darlington)
>> > emitter tied to Vbb (~20VDC).
>
> (actually, PNP Darlington)
>
>> > Anyone have a single component in mind that will essentially emulate
>> > (isolate) an Open-Collector output for the 138?
>
>> Use a "digital" PNP transitor, base to VCC emitter to 138 output,
>> collector to the base resistor of the darlington
>>
>> UNR221900L or similar.
>
> Um... the 138 going active low, you want that emitter to be of an NPN transistor,
> not PNP.

Yes, NPN is needed. oops.

> For example, ROHM DTC124XE3 HZG
> Although, with eight outputs to handle, a dual package might
> be good, too.

The single part can be soldered acroass a cut track with a short fly-lead
from base to a common bus wire connected to VCC, and some cyanoacrylate gel
or epoxy to stabilise it mechanically.

--
Jasen.

John Larkin wrote:
> On Sat, 8 Oct 2022 10:29:56 -0700 (PDT), Lasse Langwadt Christensen
> <langwadt@fonz.dk> wrote:
>
>> lørdag den 8. oktober 2022 kl. 19.14.05 UTC+2 skrev John Larkin:
>>> On Thu, 6 Oct 2022 14:31:36 -0400, Phil Hobbs
>>> <pcdhSpamM...@electrooptical.net> wrote:
>>>
>>>> Lasse Langwadt Christensen wrote:
>>>>> torsdag den 6. oktober 2022 kl. 20.04.09 UTC+2 skrev Phil Hobbs:
>>>>>> Lasse Langwadt Christensen wrote:
>>>>>>> torsdag den 6. oktober 2022 kl. 18.51.13 UTC+2 skrev Phil Hobbs:
>>>>>>>> John Robertson wrote:
>>>>>>>>> On 2022/10/06 4:41 a.m., Phil Hobbs wrote:
>>>>>>>>>> John Robertson wrote:
>>>>>>>>>>> Have a circuit that needs repair. Uses a TIP125 (NPN, Darlington)
>>>>>>>>>>> emitter tied to Vbb (~20VDC). Collector to load, then to ground. 1K
>>>>>>>>>>> resistor (R1) pullup on Base to Vbb, and a second 1KR (R2) to the TTL
>>>>>>>>>>> controller.
>>>>>>>>>>>
>>>>>>>>>>> Problem is of course, that R2 puts the ~20VDC to the TTL output gate
>>>>>>>>>>> on a 74LS138.
>>>>>>>>>>>
>>>>>>>>>>> Trying to solve this without a driver transistor. The circuit is for
>>>>>>>>>>> a 1ms ~20V strobe pulse repeated every ten ms.
>>>>>>>>>>>
>>>>>>>>>>> I thought of putting a 10ufd cap in series with R2, but don't like
>>>>>>>>>>> electrolytics as they fail after a few thousand hours.
>>>>>>>>>>>
>>>>>>>>>>> Possible to use a 15V or so Zener Diode, but the Vbb is not regulated
>>>>>>>>>>> so that won't work reliably.
>>>>>>>>>>>
>>>>>>>>>>> Anyone have a single component in mind that will essentially emulate
>>>>>>>>>>> (isolate) an Open-Collector output for the 138?
>>>>>>>>>>>
>>>>>>>>>>> Thanks!
>>>>>>>>>>>
>>>>>>>>>>> John :-#)#
>>>>>>>>>>>
>>>>>>>>>> Switch it to a 139 and use a 2N7002?
>>>>>>>>>>
>>>>>>>>>> Cheers
>>>>>>>>>>
>>>>>>>>>> Phil Hobbs
>>>>>>>>>>
>>>>>>>>>
>>>>>>>>> Well, this is to fix 5 x PCBs we are stuck with at the moment, next run
>>>>>>>>> will fix the drives - either 7445s or 138 with P-Channel MOSFETs and
>>>>>>>>> drivers.
>>>>>>>>>
>>>>>>>>> Circuit I am trying to fix with fewest components - one x two legged
>>>>>>>>> device preferred per 138 output:
>>>>>>>>>
>>>>>>>>> https://www.flippers.com/images/delete/74LS138_Lamp_Driver.png
>>>>>>>>>
>>>>>>>>> VLAMP is roughly 20VDC.
>>>>>>>>>
>>>>>>>>> Thanks,
>>>>>>>>>
>>>>>>>>> John :-#)#
>>>>>>>> The MOSFET cascode thing is pretty good actually, if you put a diode to
>>>>>>>> the supply or want to live dangerously and rely on the ESD protection to
>>>>>>>> discharge the gate. If it's a matter of using the boards or tossing
>>>>>>>> them, there's not much to lose by using barefoot FETs.
>>>>>>>>
>>>>>>>
>>>>>>> '138 is push-pull, though very wimpy high side
>>>>>>>
>>>>>> Sure, but anything above +4ish reverse-biases the upper output transistor.
>>>>>> Cheers
>>>>>
>>>>> with the upper transistor on does it ever get there?
>>>>>
>>>>>
>>>>
>>>> Sure, it's an NPN emitter. If it were a NFET, it would be fine.
>>>
>>> LS has a darlington with 110 ohms in the drain and probably no ESD
>>> diode to +5.
>>>
>>> It's shocking how poorly specified all those old TTL parts were.
>>> Modern logic isn't much better. We have to measure stuff like Zout and
>>> rise/fall times. Sometimes the results are startling.
>>
>> it should be in the IBIS file
>
> It's quicker and funner to measure. More believable too.
>
> https://www.dropbox.com/sh/mjrpofcgwgkhyc4/AABdMuqHdBNRcUOMZzCE-CT2a?dl=0
>
> https://www.dropbox.com/sh/gyn0nz486fmqp1s/AAB5kwDWJ1VR8EXMjGRHs4iEa?dl=0
>
> That NC7SV74 rise time was really unexpected. There must be a use for
> that.
>
> The actual data setup time is not specified.

Sure thing--driving a sampler, for instance (assuming the jitter is good).

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510

http://electrooptical.net
http://hobbs-eo.com

On Mon, 10 Oct 2022 18:26:24 -0400, Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:

>John Larkin wrote:
>> On Sat, 8 Oct 2022 10:29:56 -0700 (PDT), Lasse Langwadt Christensen
>> <langwadt@fonz.dk> wrote:
>>
>>> lørdag den 8. oktober 2022 kl. 19.14.05 UTC+2 skrev John Larkin:
>>>> On Thu, 6 Oct 2022 14:31:36 -0400, Phil Hobbs
>>>> <pcdhSpamM...@electrooptical.net> wrote:
>>>>
>>>>> Lasse Langwadt Christensen wrote:
>>>>>> torsdag den 6. oktober 2022 kl. 20.04.09 UTC+2 skrev Phil Hobbs:
>>>>>>> Lasse Langwadt Christensen wrote:
>>>>>>>> torsdag den 6. oktober 2022 kl. 18.51.13 UTC+2 skrev Phil Hobbs:
>>>>>>>>> John Robertson wrote:
>>>>>>>>>> On 2022/10/06 4:41 a.m., Phil Hobbs wrote:
>>>>>>>>>>> John Robertson wrote:
>>>>>>>>>>>> Have a circuit that needs repair. Uses a TIP125 (NPN, Darlington)
>>>>>>>>>>>> emitter tied to Vbb (~20VDC). Collector to load, then to ground. 1K
>>>>>>>>>>>> resistor (R1) pullup on Base to Vbb, and a second 1KR (R2) to the TTL
>>>>>>>>>>>> controller.
>>>>>>>>>>>>
>>>>>>>>>>>> Problem is of course, that R2 puts the ~20VDC to the TTL output gate
>>>>>>>>>>>> on a 74LS138.
>>>>>>>>>>>>
>>>>>>>>>>>> Trying to solve this without a driver transistor. The circuit is for
>>>>>>>>>>>> a 1ms ~20V strobe pulse repeated every ten ms.
>>>>>>>>>>>>
>>>>>>>>>>>> I thought of putting a 10ufd cap in series with R2, but don't like
>>>>>>>>>>>> electrolytics as they fail after a few thousand hours.
>>>>>>>>>>>>
>>>>>>>>>>>> Possible to use a 15V or so Zener Diode, but the Vbb is not regulated
>>>>>>>>>>>> so that won't work reliably.
>>>>>>>>>>>>
>>>>>>>>>>>> Anyone have a single component in mind that will essentially emulate
>>>>>>>>>>>> (isolate) an Open-Collector output for the 138?
>>>>>>>>>>>>
>>>>>>>>>>>> Thanks!
>>>>>>>>>>>>
>>>>>>>>>>>> John :-#)#
>>>>>>>>>>>>
>>>>>>>>>>> Switch it to a 139 and use a 2N7002?
>>>>>>>>>>>
>>>>>>>>>>> Cheers
>>>>>>>>>>>
>>>>>>>>>>> Phil Hobbs
>>>>>>>>>>>
>>>>>>>>>>
>>>>>>>>>> Well, this is to fix 5 x PCBs we are stuck with at the moment, next run
>>>>>>>>>> will fix the drives - either 7445s or 138 with P-Channel MOSFETs and
>>>>>>>>>> drivers.
>>>>>>>>>>
>>>>>>>>>> Circuit I am trying to fix with fewest components - one x two legged
>>>>>>>>>> device preferred per 138 output:
>>>>>>>>>>
>>>>>>>>>> https://www.flippers.com/images/delete/74LS138_Lamp_Driver.png
>>>>>>>>>>
>>>>>>>>>> VLAMP is roughly 20VDC.
>>>>>>>>>>
>>>>>>>>>> Thanks,
>>>>>>>>>>
>>>>>>>>>> John :-#)#
>>>>>>>>> The MOSFET cascode thing is pretty good actually, if you put a diode to
>>>>>>>>> the supply or want to live dangerously and rely on the ESD protection to
>>>>>>>>> discharge the gate. If it's a matter of using the boards or tossing
>>>>>>>>> them, there's not much to lose by using barefoot FETs.
>>>>>>>>>
>>>>>>>>
>>>>>>>> '138 is push-pull, though very wimpy high side
>>>>>>>>
>>>>>>> Sure, but anything above +4ish reverse-biases the upper output transistor.
>>>>>>> Cheers
>>>>>>
>>>>>> with the upper transistor on does it ever get there?
>>>>>>
>>>>>>
>>>>>
>>>>> Sure, it's an NPN emitter. If it were a NFET, it would be fine.
>>>>
>>>> LS has a darlington with 110 ohms in the drain and probably no ESD
>>>> diode to +5.
>>>>
>>>> It's shocking how poorly specified all those old TTL parts were.
>>>> Modern logic isn't much better. We have to measure stuff like Zout and
>>>> rise/fall times. Sometimes the results are startling.
>>>
>>> it should be in the IBIS file
>>
>> It's quicker and funner to measure. More believable too.
>>
>> https://www.dropbox.com/sh/mjrpofcgwgkhyc4/AABdMuqHdBNRcUOMZzCE-CT2a?dl=0
>>
>> https://www.dropbox.com/sh/gyn0nz486fmqp1s/AAB5kwDWJ1VR8EXMjGRHs4iEa?dl=0
>>
>> That NC7SV74 rise time was really unexpected. There must be a use for
>> that.
>>
>> The actual data setup time is not specified.
>
>
>Sure thing--driving a sampler, for instance (assuming the jitter is good).
>
>Cheers
>
>Phil Hobbs

Pretty good edge for 13 cents.

John Larkin wrote:
> On Mon, 10 Oct 2022 18:26:24 -0400, Phil Hobbs
> <pcdhSpamMeSenseless@electrooptical.net> wrote:
>
>> John Larkin wrote:
>>> On Sat, 8 Oct 2022 10:29:56 -0700 (PDT), Lasse Langwadt Christensen
>>> <langwadt@fonz.dk> wrote:
>>>
>>>> lørdag den 8. oktober 2022 kl. 19.14.05 UTC+2 skrev John Larkin:
>>>>> On Thu, 6 Oct 2022 14:31:36 -0400, Phil Hobbs
>>>>> <pcdhSpamM...@electrooptical.net> wrote:
>>>>>
>>>>>> Lasse Langwadt Christensen wrote:
>>>>>>> torsdag den 6. oktober 2022 kl. 20.04.09 UTC+2 skrev Phil Hobbs:
>>>>>>>> Lasse Langwadt Christensen wrote:
>>>>>>>>> torsdag den 6. oktober 2022 kl. 18.51.13 UTC+2 skrev Phil Hobbs:
>>>>>>>>>> John Robertson wrote:
>>>>>>>>>>> On 2022/10/06 4:41 a.m., Phil Hobbs wrote:
>>>>>>>>>>>> John Robertson wrote:
>>>>>>>>>>>>> Have a circuit that needs repair. Uses a TIP125 (NPN, Darlington)
>>>>>>>>>>>>> emitter tied to Vbb (~20VDC). Collector to load, then to ground. 1K
>>>>>>>>>>>>> resistor (R1) pullup on Base to Vbb, and a second 1KR (R2) to the TTL
>>>>>>>>>>>>> controller.
>>>>>>>>>>>>>
>>>>>>>>>>>>> Problem is of course, that R2 puts the ~20VDC to the TTL output gate
>>>>>>>>>>>>> on a 74LS138.
>>>>>>>>>>>>>
>>>>>>>>>>>>> Trying to solve this without a driver transistor. The circuit is for
>>>>>>>>>>>>> a 1ms ~20V strobe pulse repeated every ten ms.
>>>>>>>>>>>>>
>>>>>>>>>>>>> I thought of putting a 10ufd cap in series with R2, but don't like
>>>>>>>>>>>>> electrolytics as they fail after a few thousand hours.
>>>>>>>>>>>>>
>>>>>>>>>>>>> Possible to use a 15V or so Zener Diode, but the Vbb is not regulated
>>>>>>>>>>>>> so that won't work reliably.
>>>>>>>>>>>>>
>>>>>>>>>>>>> Anyone have a single component in mind that will essentially emulate
>>>>>>>>>>>>> (isolate) an Open-Collector output for the 138?
>>>>>>>>>>>>>
>>>>>>>>>>>>> Thanks!
>>>>>>>>>>>>>
>>>>>>>>>>>>> John :-#)#
>>>>>>>>>>>>>
>>>>>>>>>>>> Switch it to a 139 and use a 2N7002?
>>>>>>>>>>>>
>>>>>>>>>>>> Cheers
>>>>>>>>>>>>
>>>>>>>>>>>> Phil Hobbs
>>>>>>>>>>>>
>>>>>>>>>>>
>>>>>>>>>>> Well, this is to fix 5 x PCBs we are stuck with at the moment, next run
>>>>>>>>>>> will fix the drives - either 7445s or 138 with P-Channel MOSFETs and
>>>>>>>>>>> drivers.
>>>>>>>>>>>
>>>>>>>>>>> Circuit I am trying to fix with fewest components - one x two legged
>>>>>>>>>>> device preferred per 138 output:
>>>>>>>>>>>
>>>>>>>>>>> https://www.flippers.com/images/delete/74LS138_Lamp_Driver.png
>>>>>>>>>>>
>>>>>>>>>>> VLAMP is roughly 20VDC.
>>>>>>>>>>>
>>>>>>>>>>> Thanks,
>>>>>>>>>>>
>>>>>>>>>>> John :-#)#
>>>>>>>>>> The MOSFET cascode thing is pretty good actually, if you put a diode to
>>>>>>>>>> the supply or want to live dangerously and rely on the ESD protection to
>>>>>>>>>> discharge the gate. If it's a matter of using the boards or tossing
>>>>>>>>>> them, there's not much to lose by using barefoot FETs.
>>>>>>>>>>
>>>>>>>>>
>>>>>>>>> '138 is push-pull, though very wimpy high side
>>>>>>>>>
>>>>>>>> Sure, but anything above +4ish reverse-biases the upper output transistor.
>>>>>>>> Cheers
>>>>>>>
>>>>>>> with the upper transistor on does it ever get there?
>>>>>>>
>>>>>>>
>>>>>>
>>>>>> Sure, it's an NPN emitter. If it were a NFET, it would be fine.
>>>>>
>>>>> LS has a darlington with 110 ohms in the drain and probably no ESD
>>>>> diode to +5.
>>>>>
>>>>> It's shocking how poorly specified all those old TTL parts were.
>>>>> Modern logic isn't much better. We have to measure stuff like Zout and
>>>>> rise/fall times. Sometimes the results are startling.
>>>>
>>>> it should be in the IBIS file
>>>
>>> It's quicker and funner to measure. More believable too.
>>>
>>> https://www.dropbox.com/sh/mjrpofcgwgkhyc4/AABdMuqHdBNRcUOMZzCE-CT2a?dl=0
>>>
>>> https://www.dropbox.com/sh/gyn0nz486fmqp1s/AAB5kwDWJ1VR8EXMjGRHs4iEa?dl=0
>>>
>>> That NC7SV74 rise time was really unexpected. There must be a use for
>>> that.
>>>
>>> The actual data setup time is not specified.
>>
>>
>> Sure thing--driving a sampler, for instance (assuming the jitter is good).

>
> Pretty good edge for 13 cents.
>

Yup. Of course the abs max VDD is 4.6V or thereabouts, so it might be a
good time not a long time. That old Fairchild part has probably been
fabbed on more than one process in its day, so who knows what the real
sitch is anyway.

Something like that, driving a fast part with decent gain (e.g. a pHEMT)
is great for one- or two-diode samplers.

Cheers

Phil Hobbs

--
Dr Philip C D Hobbs
Principal Consultant
ElectroOptical Innovations LLC / Hobbs ElectroOptics
Optics, Electro-optics, Photonics, Analog Electronics
Briarcliff Manor NY 10510

http://electrooptical.net
http://hobbs-eo.com

On Mon, 10 Oct 2022 20:32:36 -0400, Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:

>John Larkin wrote:
>> On Mon, 10 Oct 2022 18:26:24 -0400, Phil Hobbs
>> <pcdhSpamMeSenseless@electrooptical.net> wrote:
>>
>>> John Larkin wrote:
>>>> On Sat, 8 Oct 2022 10:29:56 -0700 (PDT), Lasse Langwadt Christensen
>>>> <langwadt@fonz.dk> wrote:
>>>>
>>>>> lørdag den 8. oktober 2022 kl. 19.14.05 UTC+2 skrev John Larkin:
>>>>>> On Thu, 6 Oct 2022 14:31:36 -0400, Phil Hobbs
>>>>>> <pcdhSpamM...@electrooptical.net> wrote:
>>>>>>
>>>>>>> Lasse Langwadt Christensen wrote:
>>>>>>>> torsdag den 6. oktober 2022 kl. 20.04.09 UTC+2 skrev Phil Hobbs:
>>>>>>>>> Lasse Langwadt Christensen wrote:
>>>>>>>>>> torsdag den 6. oktober 2022 kl. 18.51.13 UTC+2 skrev Phil Hobbs:
>>>>>>>>>>> John Robertson wrote:
>>>>>>>>>>>> On 2022/10/06 4:41 a.m., Phil Hobbs wrote:
>>>>>>>>>>>>> John Robertson wrote:
>>>>>>>>>>>>>> Have a circuit that needs repair. Uses a TIP125 (NPN, Darlington)
>>>>>>>>>>>>>> emitter tied to Vbb (~20VDC). Collector to load, then to ground. 1K
>>>>>>>>>>>>>> resistor (R1) pullup on Base to Vbb, and a second 1KR (R2) to the TTL
>>>>>>>>>>>>>> controller.
>>>>>>>>>>>>>>
>>>>>>>>>>>>>> Problem is of course, that R2 puts the ~20VDC to the TTL output gate
>>>>>>>>>>>>>> on a 74LS138.
>>>>>>>>>>>>>>
>>>>>>>>>>>>>> Trying to solve this without a driver transistor. The circuit is for
>>>>>>>>>>>>>> a 1ms ~20V strobe pulse repeated every ten ms.
>>>>>>>>>>>>>>
>>>>>>>>>>>>>> I thought of putting a 10ufd cap in series with R2, but don't like
>>>>>>>>>>>>>> electrolytics as they fail after a few thousand hours.
>>>>>>>>>>>>>>
>>>>>>>>>>>>>> Possible to use a 15V or so Zener Diode, but the Vbb is not regulated
>>>>>>>>>>>>>> so that won't work reliably.
>>>>>>>>>>>>>>
>>>>>>>>>>>>>> Anyone have a single component in mind that will essentially emulate
>>>>>>>>>>>>>> (isolate) an Open-Collector output for the 138?
>>>>>>>>>>>>>>
>>>>>>>>>>>>>> Thanks!
>>>>>>>>>>>>>>
>>>>>>>>>>>>>> John :-#)#
>>>>>>>>>>>>>>
>>>>>>>>>>>>> Switch it to a 139 and use a 2N7002?
>>>>>>>>>>>>>
>>>>>>>>>>>>> Cheers
>>>>>>>>>>>>>
>>>>>>>>>>>>> Phil Hobbs
>>>>>>>>>>>>>
>>>>>>>>>>>>
>>>>>>>>>>>> Well, this is to fix 5 x PCBs we are stuck with at the moment, next run
>>>>>>>>>>>> will fix the drives - either 7445s or 138 with P-Channel MOSFETs and
>>>>>>>>>>>> drivers.
>>>>>>>>>>>>
>>>>>>>>>>>> Circuit I am trying to fix with fewest components - one x two legged
>>>>>>>>>>>> device preferred per 138 output:
>>>>>>>>>>>>
>>>>>>>>>>>> https://www.flippers.com/images/delete/74LS138_Lamp_Driver.png
>>>>>>>>>>>>
>>>>>>>>>>>> VLAMP is roughly 20VDC.
>>>>>>>>>>>>
>>>>>>>>>>>> Thanks,
>>>>>>>>>>>>
>>>>>>>>>>>> John :-#)#
>>>>>>>>>>> The MOSFET cascode thing is pretty good actually, if you put a diode to
>>>>>>>>>>> the supply or want to live dangerously and rely on the ESD protection to
>>>>>>>>>>> discharge the gate. If it's a matter of using the boards or tossing
>>>>>>>>>>> them, there's not much to lose by using barefoot FETs.
>>>>>>>>>>>
>>>>>>>>>>
>>>>>>>>>> '138 is push-pull, though very wimpy high side
>>>>>>>>>>
>>>>>>>>> Sure, but anything above +4ish reverse-biases the upper output transistor.
>>>>>>>>> Cheers
>>>>>>>>
>>>>>>>> with the upper transistor on does it ever get there?
>>>>>>>>
>>>>>>>>
>>>>>>>
>>>>>>> Sure, it's an NPN emitter. If it were a NFET, it would be fine.
>>>>>>
>>>>>> LS has a darlington with 110 ohms in the drain and probably no ESD
>>>>>> diode to +5.
>>>>>>
>>>>>> It's shocking how poorly specified all those old TTL parts were.
>>>>>> Modern logic isn't much better. We have to measure stuff like Zout and
>>>>>> rise/fall times. Sometimes the results are startling.
>>>>>
>>>>> it should be in the IBIS file
>>>>
>>>> It's quicker and funner to measure. More believable too.
>>>>
>>>> https://www.dropbox.com/sh/mjrpofcgwgkhyc4/AABdMuqHdBNRcUOMZzCE-CT2a?dl=0
>>>>
>>>> https://www.dropbox.com/sh/gyn0nz486fmqp1s/AAB5kwDWJ1VR8EXMjGRHs4iEa?dl=0
>>>>
>>>> That NC7SV74 rise time was really unexpected. There must be a use for
>>>> that.
>>>>
>>>> The actual data setup time is not specified.
>>>
>>>
>>> Sure thing--driving a sampler, for instance (assuming the jitter is good).
>
>>
>> Pretty good edge for 13 cents.
>>
>
>Yup. Of course the abs max VDD is 4.6V or thereabouts, so it might be a
>good time not a long time. That old Fairchild part has probably been
>fabbed on more than one process in its day, so who knows what the real
>sitch is anyway.
>
>Something like that, driving a fast part with decent gain (e.g. a pHEMT)
>is great for one- or two-diode samplers.

The rise/fall asymmetry is unfortunate.

>
>Cheers
>
>Phil Hobbs

I tend to push abs-max limits when there is a big payoff. Parts
usually have pretty good margins. Test to destruction, of course, and
back off some.

RF parts are usually good for at least 2x the datasheet voltages,
because of the way RF people usually design: inductor or tank to
specified Vcc and twice that peak sinewave swing in real life.

Spice model? As if!

On 6.10.22 9.24, John Robertson wrote:
> Have a circuit that needs repair. Uses a TIP125 (NPN, Darlington)
> emitter tied to Vbb (~20VDC). Collector to load, then to ground. 1K
> resistor (R1) pullup on Base to Vbb, and a second 1KR (R2) to the TTL
> controller.
>
> Problem is of course, that R2 puts the ~20VDC to the TTL output gate on
> a 74LS138.
>
> Trying to solve this without a driver transistor. The circuit is for a
> 1ms ~20V strobe pulse repeated every ten ms.
>
> I thought of putting a 10ufd cap in series with R2, but don't like
> electrolytics as they fail after a few thousand hours.
>
> Possible to use a 15V or so Zener Diode, but the Vbb is not regulated so
> that won't work reliably.
>
> Anyone have a single component in mind that will essentially emulate
> (isolate) an Open-Collector output for the 138?
>
> Thanks!
>
> John :-#)#
>

If you can handle LTspice, here's a solution.

The original circuit overloads the LS138 with both voltage and current.
The abs max voltage on LSTTL pin is 7V and maximum current for LS138
output is 8mA. The circuit gives 20V and 20mA.

There is no information on the lamp load, but the Darlingtons cannot
handle more then 5A, which can be reached with 5mA on base.

I made a LTspice model with a guessed 240mA lamp load. The value is
not critical.

---- clip clip ----

Version 4
SHEET 1 2200 680
WIRE 2128 -416 1824 -416
WIRE 2128 -304 2128 -416
WIRE 0 -256 -384 -256
WIRE 176 -256 0 -256
WIRE 464 -256 176 -256
WIRE 592 -256 464 -256
WIRE 912 -256 592 -256
WIRE 1520 -240 1472 -240
WIRE 1648 -240 1600 -240
WIRE 1696 -240 1648 -240
WIRE 1824 -240 1824 -416
WIRE 1824 -240 1776 -240
WIRE 176 -176 176 -256
WIRE 464 -176 464 -256
WIRE 2128 -176 2128 -224
WIRE 1824 -160 1824 -240
WIRE -384 -144 -384 -256
WIRE 912 -128 912 -256
WIRE 1648 -112 1648 -240
WIRE 1760 -112 1648 -112
WIRE 592 -96 592 -256
WIRE 0 -80 0 -256
WIRE 1648 -64 1648 -112
WIRE 464 -48 464 -96
WIRE 464 -48 336 -48
WIRE 336 -16 336 -48
WIRE 1280 -16 1104 -16
WIRE 1472 -16 1472 -240
WIRE 1472 -16 1360 -16
WIRE 1584 -16 1472 -16
WIRE -384 32 -384 -64
WIRE 176 32 176 -96
WIRE 272 32 176 32
WIRE 1104 32 1104 -16
WIRE 464 48 464 -48
WIRE 1648 64 1648 32
WIRE 1824 64 1824 -64
WIRE 1824 64 1648 64
WIRE 912 80 912 -48
WIRE 1040 80 912 80
WIRE 176 96 176 32
WIRE 336 96 336 80
WIRE 400 96 336 96
WIRE -144 144 -384 144
WIRE 0 144 0 0
WIRE 0 144 -80 144
WIRE 112 144 0 144
WIRE 464 160 464 144
WIRE 592 160 592 -32
WIRE 592 160 464 160
WIRE 1104 160 1104 128
WIRE 1104 160 592 160
WIRE 464 192 464 160
WIRE 1824 208 1824 64
WIRE 176 240 176 192
WIRE 400 240 176 240
WIRE 592 256 592 160
WIRE -384 272 -384 144
WIRE 912 272 912 80
WIRE 176 288 176 240
WIRE -384 432 -384 352
WIRE 464 432 464 288
WIRE 592 432 592 320
WIRE 912 432 912 352
WIRE 176 448 176 368
WIRE 1824 448 1824 288
FLAG 176 448 0
FLAG -384 432 0
FLAG -384 32 0
FLAG 464 432 0
FLAG 1824 448 0
FLAG 2128 -176 0
FLAG 592 432 0
FLAG 912 432 0
SYMBOL npn 112 96 R0
SYMATTR InstName Q1
SYMBOL res 160 -192 R0
SYMATTR InstName R1
SYMATTR Value 8k
SYMBOL voltage -384 -160 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value 5
SYMBOL voltage -384 256 R0
WINDOW 3 -21 256 Left 2
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR Value PULSE(0 2.5 0 100n 100n 500u 1m)
SYMATTR InstName V2
SYMBOL res 160 272 R0
SYMATTR InstName R3
SYMATTR Value 3k
SYMBOL npn 400 192 R0
SYMATTR InstName Q2
SYMBOL npn 400 48 R0
SYMATTR InstName Q3
SYMBOL res 448 -192 R0
SYMATTR InstName R4
SYMATTR Value 120
SYMBOL npn 272 -16 R0
SYMATTR InstName Q4
SYMBOL res -16 -96 R0
SYMATTR InstName R5
SYMATTR Value 20k
SYMBOL schottky -80 128 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName D1
SYMBOL pnp 1584 32 M180
SYMATTR InstName Q5
SYMATTR Value 2N3906
SYMBOL pnp 1760 -64 M180
SYMATTR InstName Q6
SYMATTR Value 2N2907
SYMBOL res 1616 -256 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R2
SYMATTR Value 8k
SYMBOL res 1792 -224 M270
WINDOW 0 32 56 VTop 2
WINDOW 3 0 56 VBottom 2
SYMATTR InstName R6
SYMATTR Value 120
SYMBOL res 1376 -32 R90
WINDOW 0 0 56 VBottom 2
WINDOW 3 32 56 VTop 2
SYMATTR InstName R8
SYMATTR Value 4.7k
SYMBOL res 1808 192 R0
SYMATTR InstName R9
SYMATTR Value 80
SYMBOL voltage 2128 -320 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value 20
SYMBOL npn 1040 32 R0
SYMATTR InstName Q7
SYMATTR Value 2N3904
SYMBOL res 896 -144 R0
SYMATTR InstName R10
SYMATTR Value 2k
SYMBOL schottky 608 320 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D2
SYMBOL schottky 608 -32 R180
WINDOW 0 24 64 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName D3
SYMBOL res 896 256 R0
SYMATTR InstName R7
SYMATTR Value 2k
TEXT 1320 448 Left 2 !.tran 5m
TEXT 1488 80 Left 2 ;TIP125 model
TEXT 1400 136 Left 2 ;Lamp driver with resistor changes
TEXT 1640 328 Left 2 ;240 mA lamp
TEXT 992 456 Left 2 ;Voltage translator
TEXT -56 440 Left 2 ;LSTTL model
TEXT 1840 -288 Left 2 ;E
TEXT 1840 96 Left 2 ;C
TEXT 1432 -32 Left 2 ;B
RECTANGLE Normal 704 496 -208 -304 2
RECTANGLE Normal 1424 112 1952 -304 2
RECTANGLE Normal 1264 -336 1984 160 2
RECTANGLE Normal 1216 -304 816 496 2
CIRCLE Normal 1904 320 1760 192 2

---- clip clip ----

This should work - at least in simulation.

--

-TV