I want to build a cheap-ish 8-channel DC power supply.

Each channel can be a half-bridge, which is easy.

If I filter with an inductor and a low-ESR cap, I get good ripple but
if I take feedback from the output the loop dynamics, the phase
margin, sucks.

So why not take the voltage feedback from the switch node? No phase
lag! If we know the load current and the circuit losses, we can tweak
the output regulation pretty well.

https://www.dropbox.com/scl/fi/sflylfz5z60wqi0p23276/P943_Sketch_1.jpg?dl=0&rlkey=3rv7i740a900a4vw6tjycmjhl

The ADCs can even be synchronized to the PWM drive, so we can do FPGA
tricks to synchronously filter the maybe-ripply voltage feedback, or
just apply an arbitrarily complex lowpass filter ahead of the
closed-loop math.

Digitizing the current allows even fancier loop dynamics.

On Friday, June 30, 2023 at 1:40:11 PM UTC-4, John Larkin wrote:
> I want to build a cheap-ish 8-channel DC power supply.
>
> Each channel can be a half-bridge, which is easy.
>
> If I filter with an inductor and a low-ESR cap, I get good ripple but
> if I take feedback from the output the loop dynamics, the phase
> margin, sucks.

Your loop gain should zero cross well before the cut-in of L/C. How else can you handle 180o/decade roll-off?

>
> So why not take the voltage feedback from the switch node? No phase
> lag! If we know the load current and the circuit losses, we can tweak
> the output regulation pretty well.
>
> https://www.dropbox.com/scl/fi/sflylfz5z60wqi0p23276/P943_Sketch_1.jpg?dl=0&rlkey=3rv7i740a900a4vw6tjycmjhl
>
> The ADCs can even be synchronized to the PWM drive, so we can do FPGA
> tricks to synchronously filter the maybe-ripply voltage feedback, or
> just apply an arbitrarily complex lowpass filter ahead of the
> closed-loop math.
>
> Digitizing the current allows even fancier loop dynamics.

On Fri, 30 Jun 2023 11:46:18 -0700 (PDT), Fred Bloggs
<bloggs.fredbloggs.fred@gmail.com> wrote:

>On Friday, June 30, 2023 at 1:40:11?PM UTC-4, John Larkin wrote:
>> I want to build a cheap-ish 8-channel DC power supply.
>>
>> Each channel can be a half-bridge, which is easy.
>>
>> If I filter with an inductor and a low-ESR cap, I get good ripple but
>> if I take feedback from the output the loop dynamics, the phase
>> margin, sucks.
>
>Your loop gain should zero cross well before the cut-in of L/C. How else can you handle 180o/decade roll-off?

That's what I'd have to do if I take the feedback from the output,
like power supplies usually do. The loop would be crazy slow.

One nice fat low ESR polymer output cap would be great in a power
supply, but the loop dynamics would be terrible with the fb from the
output.

On 6/30/2023 1:39 PM, John Larkin wrote:
>
> I want to build a cheap-ish 8-channel DC power supply.
>
> Each channel can be a half-bridge, which is easy.
>
> If I filter with an inductor and a low-ESR cap, I get good ripple but
> if I take feedback from the output the loop dynamics, the phase
> margin, sucks.
>
> So why not take the voltage feedback from the switch node? No phase
> lag! If we know the load current and the circuit losses, we can tweak
> the output regulation pretty well.
>
> https://www.dropbox.com/scl/fi/sflylfz5z60wqi0p23276/P943_Sketch_1.jpg?dl=0&rlkey=3rv7i740a900a4vw6tjycmjhl
>
> The ADCs can even be synchronized to the PWM drive, so we can do FPGA
> tricks to synchronously filter the maybe-ripply voltage feedback, or
> just apply an arbitrarily complex lowpass filter ahead of the
> closed-loop math.
>
> Digitizing the current allows even fancier loop dynamics.
>

Post-filter feedback controllers that have good performance don't need a
PhD:

<https://www.diyaudio.com/community/attachments/rad50bb0-pdf.705722/>

On 6/30/2023 1:39 PM, John Larkin wrote:
>
> I want to build a cheap-ish 8-channel DC power supply.
>
> Each channel can be a half-bridge, which is easy.
>
> If I filter with an inductor and a low-ESR cap, I get good ripple but
> if I take feedback from the output the loop dynamics, the phase
> margin, sucks.
>
> So why not take the voltage feedback from the switch node? No phase
> lag! If we know the load current and the circuit losses, we can tweak
> the output regulation pretty well.
>
> https://www.dropbox.com/scl/fi/sflylfz5z60wqi0p23276/P943_Sketch_1.jpg?dl=0&rlkey=3rv7i740a900a4vw6tjycmjhl
>
> The ADCs can even be synchronized to the PWM drive, so we can do FPGA
> tricks to synchronously filter the maybe-ripply voltage feedback, or
> just apply an arbitrarily complex lowpass filter ahead of the
> closed-loop math.
>
> Digitizing the current allows even fancier loop dynamics.
>

Since you're using a FPGA anyway do you even need to low-pass the switch
node voltage in analog and send it to an ADC first?

Since you're pre-filter anyway I think you could just level-shift and
send the bit streams on the gates of Q1 and Q2 to pins on the FPGA, as
your "1 bit ADCs" if you will

On Fri, 30 Jun 2023 15:57:12 -0400, bitrex <user@example.net> wrote:

>On 6/30/2023 1:39 PM, John Larkin wrote:
>>
>> I want to build a cheap-ish 8-channel DC power supply.
>>
>> Each channel can be a half-bridge, which is easy.
>>
>> If I filter with an inductor and a low-ESR cap, I get good ripple but
>> if I take feedback from the output the loop dynamics, the phase
>> margin, sucks.
>>
>> So why not take the voltage feedback from the switch node? No phase
>> lag! If we know the load current and the circuit losses, we can tweak
>> the output regulation pretty well.
>>
>> https://www.dropbox.com/scl/fi/sflylfz5z60wqi0p23276/P943_Sketch_1.jpg?dl=0&rlkey=3rv7i740a900a4vw6tjycmjhl
>>
>> The ADCs can even be synchronized to the PWM drive, so we can do FPGA
>> tricks to synchronously filter the maybe-ripply voltage feedback, or
>> just apply an arbitrarily complex lowpass filter ahead of the
>> closed-loop math.
>>
>> Digitizing the current allows even fancier loop dynamics.
>>
>
>Post-filter feedback controllers that have good performance don't need a
>PhD:
>
><https://www.diyaudio.com/community/attachments/rad50bb0-pdf.705722/>

The other issue is that we don't know what the customer load might be.
It could be capacitive, or inductive, which would change our loop
dynamics.

I suppose I'll have to Spice this. Whatever analog loop I come up
with, it can be done in the FPGA.

On Fri, 30 Jun 2023 16:09:11 -0400, bitrex <user@example.net> wrote:

>On 6/30/2023 1:39 PM, John Larkin wrote:
>>
>> I want to build a cheap-ish 8-channel DC power supply.
>>
>> Each channel can be a half-bridge, which is easy.
>>
>> If I filter with an inductor and a low-ESR cap, I get good ripple but
>> if I take feedback from the output the loop dynamics, the phase
>> margin, sucks.
>>
>> So why not take the voltage feedback from the switch node? No phase
>> lag! If we know the load current and the circuit losses, we can tweak
>> the output regulation pretty well.
>>
>> https://www.dropbox.com/scl/fi/sflylfz5z60wqi0p23276/P943_Sketch_1.jpg?dl=0&rlkey=3rv7i740a900a4vw6tjycmjhl
>>
>> The ADCs can even be synchronized to the PWM drive, so we can do FPGA
>> tricks to synchronously filter the maybe-ripply voltage feedback, or
>> just apply an arbitrarily complex lowpass filter ahead of the
>> closed-loop math.
>>
>> Digitizing the current allows even fancier loop dynamics.
>>
>
>Since you're using a FPGA anyway do you even need to low-pass the switch
>node voltage in analog and send it to an ADC first?

Just to take out any really fast spikes.

>
>Since you're pre-filter anyway I think you could just level-shift and
>send the bit streams on the gates of Q1 and Q2 to pins on the FPGA, as
>your "1 bit ADCs" if you will

The FPGA is driving the fets, so we know their state. The +48 could
wander a bit, and it doesn't know that.

On Fri, 30 Jun 2023 10:39:31 -0700, John Larkin
<jlarkin@highlandSNIPMEtechnology.com> wrote:

>
>I want to build a cheap-ish 8-channel DC power supply.
>
>Each channel can be a half-bridge, which is easy.
>
>If I filter with an inductor and a low-ESR cap, I get good ripple but
>if I take feedback from the output the loop dynamics, the phase
>margin, sucks.
>
>So why not take the voltage feedback from the switch node? No phase
>lag! If we know the load current and the circuit losses, we can tweak
>the output regulation pretty well.
>
>https://www.dropbox.com/scl/fi/sflylfz5z60wqi0p23276/P943_Sketch_1.jpg?dl=0&rlkey=3rv7i740a900a4vw6tjycmjhl
>
>The ADCs can even be synchronized to the PWM drive, so we can do FPGA
>tricks to synchronously filter the maybe-ripply voltage feedback, or
>just apply an arbitrarily complex lowpass filter ahead of the
>closed-loop math.
>
>Digitizing the current allows even fancier loop dynamics.

Your 'tweak' , even without rcfiltering, is expected to be faster
than simple feed-forward compensation?

That is preposterous.

RL

On 6/30/2023 6:39 PM, John Larkin wrote:
> On Fri, 30 Jun 2023 16:09:11 -0400, bitrex <user@example.net> wrote:
>
>> On 6/30/2023 1:39 PM, John Larkin wrote:
>>>
>>> I want to build a cheap-ish 8-channel DC power supply.
>>>
>>> Each channel can be a half-bridge, which is easy.
>>>
>>> If I filter with an inductor and a low-ESR cap, I get good ripple but
>>> if I take feedback from the output the loop dynamics, the phase
>>> margin, sucks.
>>>
>>> So why not take the voltage feedback from the switch node? No phase
>>> lag! If we know the load current and the circuit losses, we can tweak
>>> the output regulation pretty well.
>>>
>>> https://www.dropbox.com/scl/fi/sflylfz5z60wqi0p23276/P943_Sketch_1.jpg?dl=0&rlkey=3rv7i740a900a4vw6tjycmjhl
>>>
>>> The ADCs can even be synchronized to the PWM drive, so we can do FPGA
>>> tricks to synchronously filter the maybe-ripply voltage feedback, or
>>> just apply an arbitrarily complex lowpass filter ahead of the
>>> closed-loop math.
>>>
>>> Digitizing the current allows even fancier loop dynamics.
>>>
>>
>> Since you're using a FPGA anyway do you even need to low-pass the switch
>> node voltage in analog and send it to an ADC first?
>
> Just to take out any really fast spikes.
>
>
>>
>> Since you're pre-filter anyway I think you could just level-shift and
>> send the bit streams on the gates of Q1 and Q2 to pins on the FPGA, as
>> your "1 bit ADCs" if you will
>
>
> The FPGA is driving the fets, so we know their state. The +48 could
> wander a bit, and it doesn't know that.
>

Ah, gotcha, I see the UC27712 is just a driver. The current shunt
post-filter also makes it easy to detect shorted loads.

I think wandering at the switch node could be detected by a current
sense amp there, too, if there's no net current going in or out of the
cap then I don't think it can be wandering. It might be possible to save
an ADC channel that way

On 6/30/2023 7:24 PM, legg wrote:
> On Fri, 30 Jun 2023 10:39:31 -0700, John Larkin
> <jlarkin@highlandSNIPMEtechnology.com> wrote:
>
>>
>> I want to build a cheap-ish 8-channel DC power supply.
>>
>> Each channel can be a half-bridge, which is easy.
>>
>> If I filter with an inductor and a low-ESR cap, I get good ripple but
>> if I take feedback from the output the loop dynamics, the phase
>> margin, sucks.
>>
>> So why not take the voltage feedback from the switch node? No phase
>> lag! If we know the load current and the circuit losses, we can tweak
>> the output regulation pretty well.
>>
>> https://www.dropbox.com/scl/fi/sflylfz5z60wqi0p23276/P943_Sketch_1.jpg?dl=0&rlkey=3rv7i740a900a4vw6tjycmjhl
>>
>> The ADCs can even be synchronized to the PWM drive, so we can do FPGA
>> tricks to synchronously filter the maybe-ripply voltage feedback, or
>> just apply an arbitrarily complex lowpass filter ahead of the
>> closed-loop math.
>>
>> Digitizing the current allows even fancier loop dynamics.
>
> Your 'tweak' , even without rcfiltering, is expected to be faster
> than simple feed-forward compensation?
>
> That is preposterous.
>
> RL

Average current-mode control has a lot of nice properties:

<https://www.ti.com/lit/an/slua079/slua079.pdf>

On Fri, 30 Jun 2023 19:24:13 -0400, legg <legg@nospam.magma.ca> wrote:

>On Fri, 30 Jun 2023 10:39:31 -0700, John Larkin
><jlarkin@highlandSNIPMEtechnology.com> wrote:
>
>>
>>I want to build a cheap-ish 8-channel DC power supply.
>>
>>Each channel can be a half-bridge, which is easy.
>>
>>If I filter with an inductor and a low-ESR cap, I get good ripple but
>>if I take feedback from the output the loop dynamics, the phase
>>margin, sucks.
>>
>>So why not take the voltage feedback from the switch node? No phase
>>lag! If we know the load current and the circuit losses, we can tweak
>>the output regulation pretty well.
>>
>>https://www.dropbox.com/scl/fi/sflylfz5z60wqi0p23276/P943_Sketch_1.jpg?dl=0&rlkey=3rv7i740a900a4vw6tjycmjhl
>>
>>The ADCs can even be synchronized to the PWM drive, so we can do FPGA
>>tricks to synchronously filter the maybe-ripply voltage feedback, or
>>just apply an arbitrarily complex lowpass filter ahead of the
>>closed-loop math.
>>
>>Digitizing the current allows even fancier loop dynamics.
>
>Your 'tweak' , even without rcfiltering, is expected to be faster
>than simple feed-forward compensation?
>
>That is preposterous.
>
>RL

It's not a preposterous idea to take the feedback from the switch node
and math out the droop at the output.

With the inductors I can get, I might lose half a volt at full load.
I'll know the current so I could cancel, say, 90% of the droop.

Compound fb wouldn't be too hard. Get the AC feedback from the switch
node, DC fb from the output. That might take two more parts.

On Friday, June 30, 2023 at 9:02:39 PM UTC-7, John Larkin wrote:
> On Fri, 30 Jun 2023 19:24:13 -0400, legg <le...@nospam.magma.ca> wrote:
>
> >On Fri, 30 Jun 2023 10:39:31 -0700, John Larkin
> ><jla...@highlandSNIPMEtechnology.com> wrote:

> >>I want to build a cheap-ish 8-channel DC power supply.

> >>The ADCs can even be synchronized to the PWM drive, so we can do FPGA
> >>tricks to synchronously filter the maybe-ripply voltage feedback, or
> >>just apply an arbitrarily complex lowpass filter ahead of the
> >>closed-loop math.
> >>
> >>Digitizing the current allows even fancier loop dynamics.
> >
> >Your 'tweak' , even without rcfiltering, is expected to be faster
> >than simple feed-forward compensation?

> It's not a preposterous idea to take the feedback from the switch node
> and math out the droop at the output.

But, typically a power supply is a voltage source, with some droop allowed
at the highest currents (and certainly in the presence of transient current draw).

So, do you intend hard shutdown (foldback) on overcurrent, or
lessened regulation when past a threshold, or
just blow a fuse? You can't kill all eight power supplies
trying to get more power into the one that's reached its limit.

As for fancy regulation tricks... keep it simple, just use a voltage reference
instead of a power supply, when the last 1% ripple in voltage matters.

On Fri, 30 Jun 2023 23:44:32 -0700 (PDT), whit3rd <whit3rd@gmail.com>
wrote:

>On Friday, June 30, 2023 at 9:02:39?PM UTC-7, John Larkin wrote:
>> On Fri, 30 Jun 2023 19:24:13 -0400, legg <le...@nospam.magma.ca> wrote:
>>
>> >On Fri, 30 Jun 2023 10:39:31 -0700, John Larkin
>> ><jla...@highlandSNIPMEtechnology.com> wrote:
>
>> >>I want to build a cheap-ish 8-channel DC power supply.
>
>> >>The ADCs can even be synchronized to the PWM drive, so we can do FPGA
>> >>tricks to synchronously filter the maybe-ripply voltage feedback, or
>> >>just apply an arbitrarily complex lowpass filter ahead of the
>> >>closed-loop math.
>> >>
>> >>Digitizing the current allows even fancier loop dynamics.
>> >
>> >Your 'tweak' , even without rcfiltering, is expected to be faster
>> >than simple feed-forward compensation?
>
>> It's not a preposterous idea to take the feedback from the switch node
>> and math out the droop at the output.
>
>But, typically a power supply is a voltage source, with some droop allowed
>at the highest currents (and certainly in the presence of transient current draw).

Sure, but I'll be measuring current and can cancel most of the droop
for free, asuming that VHDL code bunnies are cheap.

>
>So, do you intend hard shutdown (foldback) on overcurrent, or
>lessened regulation when past a threshold, or
>just blow a fuse? You can't kill all eight power supplies
>trying to get more power into the one that's reached its limit.

Each one will current limit, or maybe some combination of current and
power limit. If each supply can output, say 40 volts max at 0.5 amp,
we could allow them to make 5 volts at 1 or 2 amps. The limit there
would be the D-sub connector pins, which are variously/randomly rated
at 1 to 2 amps.

>
>As for fancy regulation tricks... keep it simple, just use a voltage reference
>instead of a power supply, when the last 1% ripple in voltage matters.

My customers buy power supplies. Being in the aerospace business, they
are used to their DC supplies being really ratty, with long cable
harnesses, so this supply doesn't need to be lab quality or have
remote sense.

One feature they want is simulated timed open-circuit, which is easily
done by turning off both fets in the helf bridge. They don't care
about isolation!

lørdag den 1. juli 2023 kl. 16.23.12 UTC+2 skrev John Larkin:
> On Fri, 30 Jun 2023 23:44:32 -0700 (PDT), whit3rd <whi...@gmail.com>
> wrote:
> >On Friday, June 30, 2023 at 9:02:39?PM UTC-7, John Larkin wrote:
> >> On Fri, 30 Jun 2023 19:24:13 -0400, legg <le...@nospam.magma.ca> wrote:
> >>
> >> >On Fri, 30 Jun 2023 10:39:31 -0700, John Larkin
> >> ><jla...@highlandSNIPMEtechnology.com> wrote:
> >
> >> >>I want to build a cheap-ish 8-channel DC power supply.
> >
> >> >>The ADCs can even be synchronized to the PWM drive, so we can do FPGA
> >> >>tricks to synchronously filter the maybe-ripply voltage feedback, or
> >> >>just apply an arbitrarily complex lowpass filter ahead of the
> >> >>closed-loop math.
> >> >>
> >> >>Digitizing the current allows even fancier loop dynamics.
> >> >
> >> >Your 'tweak' , even without rcfiltering, is expected to be faster
> >> >than simple feed-forward compensation?
> >
> >> It's not a preposterous idea to take the feedback from the switch node
> >> and math out the droop at the output.
> >
> >But, typically a power supply is a voltage source, with some droop allowed
> >at the highest currents (and certainly in the presence of transient current draw).
> Sure, but I'll be measuring current and can cancel most of the droop
> for free, asuming that VHDL code bunnies are cheap.
> >
> >So, do you intend hard shutdown (foldback) on overcurrent, or
> >lessened regulation when past a threshold, or
> >just blow a fuse? You can't kill all eight power supplies
> >trying to get more power into the one that's reached its limit.
> Each one will current limit, or maybe some combination of current and
> power limit. If each supply can output, say 40 volts max at 0.5 amp,
> we could allow them to make 5 volts at 1 or 2 amps. The limit there
> would be the D-sub connector pins, which are variously/randomly rated
> at 1 to 2 amps.

most datasheets I've seen says 3A or 5A per contact

On a sunny day (Sat, 01 Jul 2023 07:22:57 -0700) it happened John Larkin
<jlarkin@highlandSNIPMEtechnology.com> wrote in
<23d0aih4maetoe9p3t5efnmgj8ej0hce14@4ax.com>:

>On Fri, 30 Jun 2023 23:44:32 -0700 (PDT), whit3rd <whit3rd@gmail.com>
>wrote:
>
>>On Friday, June 30, 2023 at 9:02:39?PM UTC-7, John Larkin wrote:
>>> On Fri, 30 Jun 2023 19:24:13 -0400, legg <le...@nospam.magma.ca> wrote:
>>>
>>> >On Fri, 30 Jun 2023 10:39:31 -0700, John Larkin
>>> ><jla...@highlandSNIPMEtechnology.com> wrote:
>>
>>> >>I want to build a cheap-ish 8-channel DC power supply.
>>
>>> >>The ADCs can even be synchronized to the PWM drive, so we can do FPGA
>>> >>tricks to synchronously filter the maybe-ripply voltage feedback, or
>>> >>just apply an arbitrarily complex lowpass filter ahead of the
>>> >>closed-loop math.
>>> >>
>>> >>Digitizing the current allows even fancier loop dynamics.
>>> >
>>> >Your 'tweak' , even without rcfiltering, is expected to be faster
>>> >than simple feed-forward compensation?
>>
>>> It's not a preposterous idea to take the feedback from the switch node
>>> and math out the droop at the output.
>>
>>But, typically a power supply is a voltage source, with some droop allowed
>>at the highest currents (and certainly in the presence of transient current draw).
>
>Sure, but I'll be measuring current and can cancel most of the droop
>for free, asuming that VHDL code bunnies are cheap.
>
>>
>>So, do you intend hard shutdown (foldback) on overcurrent, or
>>lessened regulation when past a threshold, or
>>just blow a fuse? You can't kill all eight power supplies
>>trying to get more power into the one that's reached its limit.
>
>Each one will current limit, or maybe some combination of current and
>power limit. If each supply can output, say 40 volts max at 0.5 amp,
>we could allow them to make 5 volts at 1 or 2 amps. The limit there
>would be the D-sub connector pins, which are variously/randomly rated
>at 1 to 2 amps.
>
>>
>>As for fancy regulation tricks... keep it simple, just use a voltage reference
>>instead of a power supply, when the last 1% ripple in voltage matters.
>
>My customers buy power supplies. Being in the aerospace business, they
>are used to their DC supplies being really ratty, with long cable
>harnesses, so this supply doesn't need to be lab quality or have
>remote sense.
>
>One feature they want is simulated timed open-circuit, which is easily
>done by turning off both fets in the helf bridge. They don't care
>about isolation!

This has now been my lab supply for 14 years, simple SEPIC
https://panteltje.nl/panteltje/pic/pwr_pic/
https://panteltje.nl/panteltje/pic/pwr_pic/power_box_diagram_img_1817.jpg
On each day...
Use PIC's voltage reference, cycle by cycle current limiting using current transformer in MOSFET drain into
PIC analog comparator that resets PWM.
Use it often to charge batteries...

On Fri, 30 Jun 2023 10:39:31 -0700, John Larkin
<jlarkin@highlandSNIPMEtechnology.com> wrote:

>
>I want to build a cheap-ish 8-channel DC power supply.
>
>Each channel can be a half-bridge, which is easy.
>
>If I filter with an inductor and a low-ESR cap, I get good ripple but
>if I take feedback from the output the loop dynamics, the phase
>margin, sucks.
>
>So why not take the voltage feedback from the switch node? No phase
>lag! If we know the load current and the circuit losses, we can tweak
>the output regulation pretty well.
>
>https://www.dropbox.com/scl/fi/sflylfz5z60wqi0p23276/P943_Sketch_1.jpg?dl=0&rlkey=3rv7i740a900a4vw6tjycmjhl
>
>The ADCs can even be synchronized to the PWM drive, so we can do FPGA
>tricks to synchronously filter the maybe-ripply voltage feedback, or
>just apply an arbitrarily complex lowpass filter ahead of the
>closed-loop math.
>
>Digitizing the current allows even fancier loop dynamics.

https://www.dropbox.com/scl/fi/0os6okravqnc6xcju52ph/P943_basic1.jpg?rlkey=zrbme3mtbk8k6pt6n73u9s2cz&dl=0

First pass at compound feedback. All the parts values are absolutely
first-guess as-drawn, and it's a tad underdamped. I'm impressed that
it worked at all, first run.

The ringing is from the passive L1-C1 thing, not the loop. Some
damping could be added across C1 to kill the Q and beautify things
some. I might do that if there's room on the board.

Next step will be to hack in the real switching half-bridge and tune
things.

On Sat, 01 Jul 2023 09:05:53 -0700, John Larkin
<jlarkin@highlandSNIPMEtechnology.com> wrote:

>On Fri, 30 Jun 2023 10:39:31 -0700, John Larkin
><jlarkin@highlandSNIPMEtechnology.com> wrote:
>
>>
>>I want to build a cheap-ish 8-channel DC power supply.
>>
>>Each channel can be a half-bridge, which is easy.
>>
>>If I filter with an inductor and a low-ESR cap, I get good ripple but
>>if I take feedback from the output the loop dynamics, the phase
>>margin, sucks.
>>
>>So why not take the voltage feedback from the switch node? No phase
>>lag! If we know the load current and the circuit losses, we can tweak
>>the output regulation pretty well.
>>
>>https://www.dropbox.com/scl/fi/sflylfz5z60wqi0p23276/P943_Sketch_1.jpg?dl=0&rlkey=3rv7i740a900a4vw6tjycmjhl
>>
>>The ADCs can even be synchronized to the PWM drive, so we can do FPGA
>>tricks to synchronously filter the maybe-ripply voltage feedback, or
>>just apply an arbitrarily complex lowpass filter ahead of the
>>closed-loop math.
>>
>>Digitizing the current allows even fancier loop dynamics.
>
>
>https://www.dropbox.com/scl/fi/0os6okravqnc6xcju52ph/P943_basic1.jpg?rlkey=zrbme3mtbk8k6pt6n73u9s2cz&dl=0
>
>First pass at compound feedback. All the parts values are absolutely
>first-guess as-drawn, and it's a tad underdamped. I'm impressed that
>it worked at all, first run.
>
>The ringing is from the passive L1-C1 thing, not the loop. Some
>damping could be added across C1 to kill the Q and beautify things
>some. I might do that if there's room on the board.
>
>Next step will be to hack in the real switching half-bridge and tune
>things.
>

This is cool. The error amp is a simple integrator, which shouldn't
challenge my VHDL code bunnies to implement. Taking the AC part of the
feedback from the switch node is beautiful for dynamics.

https://www.dropbox.com/scl/fi/fd8f7npyssfz7ukrrhxme/P943_basic2.jpg?rlkey=fp33qcq1hcxqfwia6is0xm8y0&dl=0

The q-killer R9 C7 looks worth doing too. R9 is almost the cap's ESR!

Now it needs a current limiter and the actual switching bit.

Does this link work?

https://www.dropbox.com/scl/fi/fd8f7npyssfz7ukrrhxme/P943_basic2.jpg?rlkey=fp33qcq1hcxqfwia6is0xm8y0&raw=1

On Sat, 01 Jul 2023 15:18:32 GMT, Jan Panteltje <alien@comet.invalid>
wrote:

>On a sunny day (Sat, 01 Jul 2023 07:22:57 -0700) it happened John Larkin
><jlarkin@highlandSNIPMEtechnology.com> wrote in
><23d0aih4maetoe9p3t5efnmgj8ej0hce14@4ax.com>:
>
>>On Fri, 30 Jun 2023 23:44:32 -0700 (PDT), whit3rd <whit3rd@gmail.com>
>>wrote:
>>
>>>On Friday, June 30, 2023 at 9:02:39?PM UTC-7, John Larkin wrote:
>>>> On Fri, 30 Jun 2023 19:24:13 -0400, legg <le...@nospam.magma.ca> wrote:
>>>>
>>>> >On Fri, 30 Jun 2023 10:39:31 -0700, John Larkin
>>>> ><jla...@highlandSNIPMEtechnology.com> wrote:
>>>
>>>> >>I want to build a cheap-ish 8-channel DC power supply.
>>>
>>>> >>The ADCs can even be synchronized to the PWM drive, so we can do FPGA
>>>> >>tricks to synchronously filter the maybe-ripply voltage feedback, or
>>>> >>just apply an arbitrarily complex lowpass filter ahead of the
>>>> >>closed-loop math.
>>>> >>
>>>> >>Digitizing the current allows even fancier loop dynamics.
>>>> >
>>>> >Your 'tweak' , even without rcfiltering, is expected to be faster
>>>> >than simple feed-forward compensation?
>>>
>>>> It's not a preposterous idea to take the feedback from the switch node
>>>> and math out the droop at the output.
>>>
>>>But, typically a power supply is a voltage source, with some droop allowed
>>>at the highest currents (and certainly in the presence of transient current draw).
>>
>>Sure, but I'll be measuring current and can cancel most of the droop
>>for free, asuming that VHDL code bunnies are cheap.
>>
>>>
>>>So, do you intend hard shutdown (foldback) on overcurrent, or
>>>lessened regulation when past a threshold, or
>>>just blow a fuse? You can't kill all eight power supplies
>>>trying to get more power into the one that's reached its limit.
>>
>>Each one will current limit, or maybe some combination of current and
>>power limit. If each supply can output, say 40 volts max at 0.5 amp,
>>we could allow them to make 5 volts at 1 or 2 amps. The limit there
>>would be the D-sub connector pins, which are variously/randomly rated
>>at 1 to 2 amps.
>>
>>>
>>>As for fancy regulation tricks... keep it simple, just use a voltage reference
>>>instead of a power supply, when the last 1% ripple in voltage matters.
>>
>>My customers buy power supplies. Being in the aerospace business, they
>>are used to their DC supplies being really ratty, with long cable
>>harnesses, so this supply doesn't need to be lab quality or have
>>remote sense.
>>
>>One feature they want is simulated timed open-circuit, which is easily
>>done by turning off both fets in the helf bridge. They don't care
>>about isolation!
>
>This has now been my lab supply for 14 years, simple SEPIC
> https://panteltje.nl/panteltje/pic/pwr_pic/
> https://panteltje.nl/panteltje/pic/pwr_pic/power_box_diagram_img_1817.jpg
>On each day...
>Use PIC's voltage reference, cycle by cycle current limiting using current transformer in MOSFET drain into
>PIC analog comparator that resets PWM.
>Use it often to charge batteries...
>

When was the last time you saw a battery charger
spec'd for dynamic response?

RL

On a sunny day (Sun, 02 Jul 2023 10:53:51 -0400) it happened legg
<legg@nospam.magma.ca> wrote in <fq33ailjfpse1rts16eaojb1j8q3d12h28@4ax.com>:

>On Sat, 01 Jul 2023 15:18:32 GMT, Jan Panteltje <alien@comet.invalid>
>wrote:
>
>>On a sunny day (Sat, 01 Jul 2023 07:22:57 -0700) it happened John Larkin
>><jlarkin@highlandSNIPMEtechnology.com> wrote in
>><23d0aih4maetoe9p3t5efnmgj8ej0hce14@4ax.com>:
>>
>>>On Fri, 30 Jun 2023 23:44:32 -0700 (PDT), whit3rd <whit3rd@gmail.com>
>>>wrote:
>>>
>>>>On Friday, June 30, 2023 at 9:02:39?PM UTC-7, John Larkin wrote:
>>>>> On Fri, 30 Jun 2023 19:24:13 -0400, legg <le...@nospam.magma.ca> wrote:
>>>>>
>>>>> >On Fri, 30 Jun 2023 10:39:31 -0700, John Larkin
>>>>> ><jla...@highlandSNIPMEtechnology.com> wrote:
>>>>
>>>>> >>I want to build a cheap-ish 8-channel DC power supply.
>>>>
>>>>> >>The ADCs can even be synchronized to the PWM drive, so we can do FPGA
>>>>> >>tricks to synchronously filter the maybe-ripply voltage feedback, or
>>>>> >>just apply an arbitrarily complex lowpass filter ahead of the
>>>>> >>closed-loop math.
>>>>> >>
>>>>> >>Digitizing the current allows even fancier loop dynamics.
>>>>> >
>>>>> >Your 'tweak' , even without rcfiltering, is expected to be faster
>>>>> >than simple feed-forward compensation?
>>>>
>>>>> It's not a preposterous idea to take the feedback from the switch node
>>>>> and math out the droop at the output.
>>>>
>>>>But, typically a power supply is a voltage source, with some droop allowed
>>>>at the highest currents (and certainly in the presence of transient current draw).
>>>
>>>Sure, but I'll be measuring current and can cancel most of the droop
>>>for free, asuming that VHDL code bunnies are cheap.
>>>
>>>>
>>>>So, do you intend hard shutdown (foldback) on overcurrent, or
>>>>lessened regulation when past a threshold, or
>>>>just blow a fuse? You can't kill all eight power supplies
>>>>trying to get more power into the one that's reached its limit.
>>>
>>>Each one will current limit, or maybe some combination of current and
>>>power limit. If each supply can output, say 40 volts max at 0.5 amp,
>>>we could allow them to make 5 volts at 1 or 2 amps. The limit there
>>>would be the D-sub connector pins, which are variously/randomly rated
>>>at 1 to 2 amps.
>>>
>>>>
>>>>As for fancy regulation tricks... keep it simple, just use a voltage reference
>>>>instead of a power supply, when the last 1% ripple in voltage matters.
>>>
>>>My customers buy power supplies. Being in the aerospace business, they
>>>are used to their DC supplies being really ratty, with long cable
>>>harnesses, so this supply doesn't need to be lab quality or have
>>>remote sense.
>>>
>>>One feature they want is simulated timed open-circuit, which is easily
>>>done by turning off both fets in the helf bridge. They don't care
>>>about isolation!
>>
>>This has now been my lab supply for 14 years, simple SEPIC
>> https://panteltje.nl/panteltje/pic/pwr_pic/
>> https://panteltje.nl/panteltje/pic/pwr_pic/power_box_diagram_img_1817.jpg
>>On each day...
>>Use PIC's voltage reference, cycle by cycle current limiting using current transformer in MOSFET drain into
>>PIC analog comparator that resets PWM.
>>Use it often to charge batteries...
>>
>
>When was the last time you saw a battery charger
>spec'd for dynamic response?
>
>RL

Not sure what you mean, the output voltage of this lab supply is very stable
also with pulse response (load on-off etc).
No special filter needed in feedback.
Fast impulse load variations are cought by the output filter capacitor.
It does have a slow start PWM mode with programmable max PWM via the serial port.
Programmable current limit is cycle by cycle on PWM via a comparator.
John Larkin's application does not seem a big thing needding complex loop filters to me.
Neither does mine.

On 7/2/2023 7:20 AM, John Larkin wrote:
> On Sat, 01 Jul 2023 09:05:53 -0700, John Larkin
> <jlarkin@highlandSNIPMEtechnology.com> wrote:
>
>> On Fri, 30 Jun 2023 10:39:31 -0700, John Larkin
>> <jlarkin@highlandSNIPMEtechnology.com> wrote:
>>
>>>
>>> I want to build a cheap-ish 8-channel DC power supply.
>>>
>>> Each channel can be a half-bridge, which is easy.
>>>
>>> If I filter with an inductor and a low-ESR cap, I get good ripple but
>>> if I take feedback from the output the loop dynamics, the phase
>>> margin, sucks.
>>>
>>> So why not take the voltage feedback from the switch node? No phase
>>> lag! If we know the load current and the circuit losses, we can tweak
>>> the output regulation pretty well.
>>>
>>> https://www.dropbox.com/scl/fi/sflylfz5z60wqi0p23276/P943_Sketch_1.jpg?dl=0&rlkey=3rv7i740a900a4vw6tjycmjhl
>>>
>>> The ADCs can even be synchronized to the PWM drive, so we can do FPGA
>>> tricks to synchronously filter the maybe-ripply voltage feedback, or
>>> just apply an arbitrarily complex lowpass filter ahead of the
>>> closed-loop math.
>>>
>>> Digitizing the current allows even fancier loop dynamics.
>>
>>
>> https://www.dropbox.com/scl/fi/0os6okravqnc6xcju52ph/P943_basic1.jpg?rlkey=zrbme3mtbk8k6pt6n73u9s2cz&dl=0
>>
>> First pass at compound feedback. All the parts values are absolutely
>> first-guess as-drawn, and it's a tad underdamped. I'm impressed that
>> it worked at all, first run.
>>
>> The ringing is from the passive L1-C1 thing, not the loop. Some
>> damping could be added across C1 to kill the Q and beautify things
>> some. I might do that if there's room on the board.
>>
>> Next step will be to hack in the real switching half-bridge and tune
>> things.
>>
>
> This is cool. The error amp is a simple integrator, which shouldn't
> challenge my VHDL code bunnies to implement. Taking the AC part of the
> feedback from the switch node is beautiful for dynamics.
>
> https://www.dropbox.com/scl/fi/fd8f7npyssfz7ukrrhxme/P943_basic2.jpg?rlkey=fp33qcq1hcxqfwia6is0xm8y0&dl=0
>
> The q-killer R9 C7 looks worth doing too. R9 is almost the cap's ESR!
>
> Now it needs a current limiter and the actual switching bit.
>
>
> Does this link work?
>
> https://www.dropbox.com/scl/fi/fd8f7npyssfz7ukrrhxme/P943_basic2.jpg?rlkey=fp33qcq1hcxqfwia6is0xm8y0&raw=1
>
>

Yes.
Ed

On 01/07/2023 17:05, John Larkin wrote:
> On Fri, 30 Jun 2023 10:39:31 -0700, John Larkin
> <jlarkin@highlandSNIPMEtechnology.com> wrote:
>
>>
>> I want to build a cheap-ish 8-channel DC power supply.
>>
>> Each channel can be a half-bridge, which is easy.
>>
>> If I filter with an inductor and a low-ESR cap, I get good ripple but
>> if I take feedback from the output the loop dynamics, the phase
>> margin, sucks.
>>
>> So why not take the voltage feedback from the switch node? No phase
>> lag! If we know the load current and the circuit losses, we can tweak
>> the output regulation pretty well.
>>
>> https://www.dropbox.com/scl/fi/sflylfz5z60wqi0p23276/P943_Sketch_1.jpg?dl=0&rlkey=3rv7i740a900a4vw6tjycmjhl
>>
>> The ADCs can even be synchronized to the PWM drive, so we can do FPGA
>> tricks to synchronously filter the maybe-ripply voltage feedback, or
>> just apply an arbitrarily complex lowpass filter ahead of the
>> closed-loop math.
>>
>> Digitizing the current allows even fancier loop dynamics.
>
>
> https://www.dropbox.com/scl/fi/0os6okravqnc6xcju52ph/P943_basic1.jpg?rlkey=zrbme3mtbk8k6pt6n73u9s2cz&dl=0
>
> First pass at compound feedback. All the parts values are absolutely
> first-guess as-drawn, and it's a tad underdamped. I'm impressed that
> it worked at all, first run.
>
> The ringing is from the passive L1-C1 thing, not the loop. Some
> damping could be added across C1 to kill the Q and beautify things
> some. I might do that if there's room on the board.
>
> Next step will be to hack in the real switching half-bridge and tune
> things.
>
>

Sampling the switch node is giving you information about the supply
voltage and MOSFET Rdson. Voltage drop due to Rdson is probably going to
be much lower than inductor loss and inferable from current measurement.
For DC accuracy you most likely will still need to sample the post LC
output. For your AC dynamics you might as well just sample the raw
supply voltage?

piglet

On Mon, 3 Jul 2023 20:12:57 +0100, piglet <erichpwagner@hotmail.com>
wrote:

>On 01/07/2023 17:05, John Larkin wrote:
>> On Fri, 30 Jun 2023 10:39:31 -0700, John Larkin
>> <jlarkin@highlandSNIPMEtechnology.com> wrote:
>>
>>>
>>> I want to build a cheap-ish 8-channel DC power supply.
>>>
>>> Each channel can be a half-bridge, which is easy.
>>>
>>> If I filter with an inductor and a low-ESR cap, I get good ripple but
>>> if I take feedback from the output the loop dynamics, the phase
>>> margin, sucks.
>>>
>>> So why not take the voltage feedback from the switch node? No phase
>>> lag! If we know the load current and the circuit losses, we can tweak
>>> the output regulation pretty well.
>>>
>>> https://www.dropbox.com/scl/fi/sflylfz5z60wqi0p23276/P943_Sketch_1.jpg?dl=0&rlkey=3rv7i740a900a4vw6tjycmjhl
>>>
>>> The ADCs can even be synchronized to the PWM drive, so we can do FPGA
>>> tricks to synchronously filter the maybe-ripply voltage feedback, or
>>> just apply an arbitrarily complex lowpass filter ahead of the
>>> closed-loop math.
>>>
>>> Digitizing the current allows even fancier loop dynamics.
>>
>>
>> https://www.dropbox.com/scl/fi/0os6okravqnc6xcju52ph/P943_basic1.jpg?rlkey=zrbme3mtbk8k6pt6n73u9s2cz&dl=0
>>
>> First pass at compound feedback. All the parts values are absolutely
>> first-guess as-drawn, and it's a tad underdamped. I'm impressed that
>> it worked at all, first run.
>>
>> The ringing is from the passive L1-C1 thing, not the loop. Some
>> damping could be added across C1 to kill the Q and beautify things
>> some. I might do that if there's room on the board.
>>
>> Next step will be to hack in the real switching half-bridge and tune
>> things.
>>
>>
>
>Sampling the switch node is giving you information about the supply
>voltage and MOSFET Rdson. Voltage drop due to Rdson is probably going to
>be much lower than inductor loss and inferable from current measurement.
>For DC accuracy you most likely will still need to sample the post LC
>output. For your AC dynamics you might as well just sample the raw
>supply voltage?
>
>piglet
>

Here is is:

https://www.dropbox.com/scl/fi/pgw70e2ls16i66pj0hl5b/P943_Loop_1.jpg?rlkey=hc1ske5u41ylhfnazuj4t27k5&raw=1

The loop feedback is a mixture of the raw switching from the
half-bridge, and the actual DC output. Dynamics look great. The two
bumps are from a pulsed load.

One nice thing, in a power supply, is that it behaves pretty well no
matter what crazy things the customer may connect it to.

Many power supplies try to solve that problem by having huge output
caps, which make giant sparks when the supply is shorted, no matter
what the current limit is set to. I won't have room for giant caps
anyhow.

That LTC driver is supposed to have shoot-thru protection, but the top
fet was frying in simulation. We'll actually use the TI driver, and
our FPGA can add shoot-thru timing if we need it. The actual control
loop will be all digital.

One sim run like in the pic takes maybe 20 minutes. I had lunch and
hosed out the garage during runs. Maybe I need a new PC.

It's hard to tune a control loop with 20 minute feedback.

On Monday, 3 July 2023 at 22:02:53 UTC+1, John Larkin wrote:
> On Mon, 3 Jul 2023 20:12:57 +0100, piglet <erichp...@hotmail.com>
> wrote:
> >On 01/07/2023 17:05, John Larkin wrote:
> >> On Fri, 30 Jun 2023 10:39:31 -0700, John Larkin
> >> <jla...@highlandSNIPMEtechnology.com> wrote:
> >>
> >>>
> >>> I want to build a cheap-ish 8-channel DC power supply.
> >>>
> >>> Each channel can be a half-bridge, which is easy.
> >>>
> >>> If I filter with an inductor and a low-ESR cap, I get good ripple but
> >>> if I take feedback from the output the loop dynamics, the phase
> >>> margin, sucks.
> >>>
> >>> So why not take the voltage feedback from the switch node? No phase
> >>> lag! If we know the load current and the circuit losses, we can tweak
> >>> the output regulation pretty well.
> >>>
> >>> https://www.dropbox.com/scl/fi/sflylfz5z60wqi0p23276/P943_Sketch_1.jpg?dl=0&rlkey=3rv7i740a900a4vw6tjycmjhl
> >>>
> >>> The ADCs can even be synchronized to the PWM drive, so we can do FPGA
> >>> tricks to synchronously filter the maybe-ripply voltage feedback, or
> >>> just apply an arbitrarily complex lowpass filter ahead of the
> >>> closed-loop math.
> >>>
> >>> Digitizing the current allows even fancier loop dynamics.
> >>
> >>
> >> https://www.dropbox.com/scl/fi/0os6okravqnc6xcju52ph/P943_basic1.jpg?rlkey=zrbme3mtbk8k6pt6n73u9s2cz&dl=0
> >>
> >> First pass at compound feedback. All the parts values are absolutely
> >> first-guess as-drawn, and it's a tad underdamped. I'm impressed that
> >> it worked at all, first run.
> >>
> >> The ringing is from the passive L1-C1 thing, not the loop. Some
> >> damping could be added across C1 to kill the Q and beautify things
> >> some. I might do that if there's room on the board.
> >>
> >> Next step will be to hack in the real switching half-bridge and tune
> >> things.
> >>
> >>
> >
> >Sampling the switch node is giving you information about the supply
> >voltage and MOSFET Rdson. Voltage drop due to Rdson is probably going to
> >be much lower than inductor loss and inferable from current measurement.
> >For DC accuracy you most likely will still need to sample the post LC
> >output. For your AC dynamics you might as well just sample the raw
> >supply voltage?
> >
> >piglet
> >
> Here is is:
>
> https://www.dropbox.com/scl/fi/pgw70e2ls16i66pj0hl5b/P943_Loop_1.jpg?rlkey=hc1ske5u41ylhfnazuj4t27k5&raw=1
>
> The loop feedback is a mixture of the raw switching from the
> half-bridge, and the actual DC output. Dynamics look great. The two
> bumps are from a pulsed load.
>
> One nice thing, in a power supply, is that it behaves pretty well no
> matter what crazy things the customer may connect it to.
>
> Many power supplies try to solve that problem by having huge output
> caps, which make giant sparks when the supply is shorted, no matter
> what the current limit is set to. I won't have room for giant caps
> anyhow.
>
> That LTC driver is supposed to have shoot-thru protection, but the top
> fet was frying in simulation. We'll actually use the TI driver, and
> our FPGA can add shoot-thru timing if we need it. The actual control
> loop will be all digital.
>
> One sim run like in the pic takes maybe 20 minutes. I had lunch and
> hosed out the garage during runs. Maybe I need a new PC.
>
> It's hard to tune a control loop with 20 minute feedback.

What is the 48v supply impedance, can’t see the series resistance of v6?
piglet

On Tue, 4 Jul 2023 04:17:47 -0700 (PDT), Erich Wagner
<erichpwagner@hotmail.com> wrote:

>On Monday, 3 July 2023 at 22:02:53 UTC+1, John Larkin wrote:
>> On Mon, 3 Jul 2023 20:12:57 +0100, piglet <erichp...@hotmail.com>
>> wrote:
>> >On 01/07/2023 17:05, John Larkin wrote:
>> >> On Fri, 30 Jun 2023 10:39:31 -0700, John Larkin
>> >> <jla...@highlandSNIPMEtechnology.com> wrote:
>> >>
>> >>>
>> >>> I want to build a cheap-ish 8-channel DC power supply.
>> >>>
>> >>> Each channel can be a half-bridge, which is easy.
>> >>>
>> >>> If I filter with an inductor and a low-ESR cap, I get good ripple but
>> >>> if I take feedback from the output the loop dynamics, the phase
>> >>> margin, sucks.
>> >>>
>> >>> So why not take the voltage feedback from the switch node? No phase
>> >>> lag! If we know the load current and the circuit losses, we can tweak
>> >>> the output regulation pretty well.
>> >>>
>> >>> https://www.dropbox.com/scl/fi/sflylfz5z60wqi0p23276/P943_Sketch_1.jpg?dl=0&rlkey=3rv7i740a900a4vw6tjycmjhl
>> >>>
>> >>> The ADCs can even be synchronized to the PWM drive, so we can do FPGA
>> >>> tricks to synchronously filter the maybe-ripply voltage feedback, or
>> >>> just apply an arbitrarily complex lowpass filter ahead of the
>> >>> closed-loop math.
>> >>>
>> >>> Digitizing the current allows even fancier loop dynamics.
>> >>
>> >>
>> >> https://www.dropbox.com/scl/fi/0os6okravqnc6xcju52ph/P943_basic1.jpg?rlkey=zrbme3mtbk8k6pt6n73u9s2cz&dl=0
>> >>
>> >> First pass at compound feedback. All the parts values are absolutely
>> >> first-guess as-drawn, and it's a tad underdamped. I'm impressed that
>> >> it worked at all, first run.
>> >>
>> >> The ringing is from the passive L1-C1 thing, not the loop. Some
>> >> damping could be added across C1 to kill the Q and beautify things
>> >> some. I might do that if there's room on the board.
>> >>
>> >> Next step will be to hack in the real switching half-bridge and tune
>> >> things.
>> >>
>> >>
>> >
>> >Sampling the switch node is giving you information about the supply
>> >voltage and MOSFET Rdson. Voltage drop due to Rdson is probably going to
>> >be much lower than inductor loss and inferable from current measurement.
>> >For DC accuracy you most likely will still need to sample the post LC
>> >output. For your AC dynamics you might as well just sample the raw
>> >supply voltage?
>> >
>> >piglet
>> >
>> Here is is:
>>
>> https://www.dropbox.com/scl/fi/pgw70e2ls16i66pj0hl5b/P943_Loop_1.jpg?rlkey=hc1ske5u41ylhfnazuj4t27k5&raw=1
>>
>> The loop feedback is a mixture of the raw switching from the
>> half-bridge, and the actual DC output. Dynamics look great. The two
>> bumps are from a pulsed load.
>>
>> One nice thing, in a power supply, is that it behaves pretty well no
>> matter what crazy things the customer may connect it to.
>>
>> Many power supplies try to solve that problem by having huge output
>> caps, which make giant sparks when the supply is shorted, no matter
>> what the current limit is set to. I won't have room for giant caps
>> anyhow.
>>
>> That LTC driver is supposed to have shoot-thru protection, but the top
>> fet was frying in simulation. We'll actually use the TI driver, and
>> our FPGA can add shoot-thru timing if we need it. The actual control
>> loop will be all digital.
>>
>> One sim run like in the pic takes maybe 20 minutes. I had lunch and
>> hosed out the garage during runs. Maybe I need a new PC.
>>
>> It's hard to tune a control loop with 20 minute feedback.
>
>What is the 48v supply impedance, can’t see the series resistance of v6?
>piglet

The 48 supply is a kilowatt MeanWell switcher, and I'm assuming it's a
perfect voltage source. These will be relatively tiny supplies,
ballpark 20 watts each maybe, so they shouldn't affect the 48v buss
much.

And, as I tell people, it's just a power supply.

I actually see people putting bypass caps across voltage sources in
Spice! It's sometimes hard to remember that we're simulating, that
dissipating 20 watts in a pullup resistor doesn't matter, or that 50
ohm resistors are actually 49.9.

Well, sometimes we add stuff that's not sensible in simulation, as
reminders about real life later. Like the gate resistors.

On 6/30/23 22:39, John Larkin wrote:
> On Fri, 30 Jun 2023 16:09:11 -0400, bitrex <user@example.net> wrote:
>
>> On 6/30/2023 1:39 PM, John Larkin wrote:
>>>
>>> I want to build a cheap-ish 8-channel DC power supply.
>>>
>>> Each channel can be a half-bridge, which is easy.
>>>
>>> If I filter with an inductor and a low-ESR cap, I get good ripple but
>>> if I take feedback from the output the loop dynamics, the phase
>>> margin, sucks.
>>>
>>> So why not take the voltage feedback from the switch node? No phase
>>> lag! If we know the load current and the circuit losses, we can tweak
>>> the output regulation pretty well.
>>>
>>> https://www.dropbox.com/scl/fi/sflylfz5z60wqi0p23276/P943_Sketch_1.jpg?dl=0&rlkey=3rv7i740a900a4vw6tjycmjhl
>>>
>>> The ADCs can even be synchronized to the PWM drive, so we can do FPGA
>>> tricks to synchronously filter the maybe-ripply voltage feedback, or
>>> just apply an arbitrarily complex lowpass filter ahead of the
>>> closed-loop math.
>>>
>>> Digitizing the current allows even fancier loop dynamics.
>>>

Why not Sense the output voltage with a separate diode and smaller cap
just to sense the voltage alone ?. Depends on what regulation you need.
but why add complexity and cost with an fpga. Overthinking ?

Chris

>>
>> Since you're using a FPGA anyway do you even need to low-pass the switch
>> node voltage in analog and send it to an ADC first?
>
> Just to take out any really fast spikes.
>
>
>>
>> Since you're pre-filter anyway I think you could just level-shift and
>> send the bit streams on the gates of Q1 and Q2 to pins on the FPGA, as
>> your "1 bit ADCs" if you will
>
>
> The FPGA is driving the fets, so we know their state. The +48 could
> wander a bit, and it doesn't know that.
>