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tech / sci.electronics.design / Re: power supply dynamics

SubjectAuthor
* power supply dynamicsJohn Larkin
+* Re: power supply dynamicsFred Bloggs
|`- Re: power supply dynamicsJohn Larkin
+* Re: power supply dynamicsbitrex
|`- Re: power supply dynamicsJohn Larkin
+* Re: power supply dynamicsbitrex
|`* Re: power supply dynamicsJohn Larkin
| +- Re: power supply dynamicsbitrex
| `* Re: power supply dynamicstridac
|  `- Re: power supply dynamicsJohn Larkin
+* Re: power supply dynamicslegg
|+- Re: power supply dynamicsbitrex
|`* Re: power supply dynamicsJohn Larkin
| `* Re: power supply dynamicswhit3rd
|  `* Re: power supply dynamicsJohn Larkin
|   +- Re: power supply dynamicsLasse Langwadt Christensen
|   `* Re: power supply dynamicsJan Panteltje
|    `* Re: power supply dynamicslegg
|     `- Re: power supply dynamicsJan Panteltje
`* Re: power supply dynamicsJohn Larkin
 +* Re: power supply dynamicsJohn Larkin
 |`- Re: power supply dynamicsehsjr
 `* Re: power supply dynamicspiglet
  `* Re: power supply dynamicsJohn Larkin
   `* Re: power supply dynamicsErich Wagner
    `- Re: power supply dynamicsJohn Larkin

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Re: power supply dynamics

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From: jlar...@highlandSNIPMEtechnology.com (John Larkin)
Newsgroups: sci.electronics.design
Subject: Re: power supply dynamics
Date: Tue, 04 Jul 2023 19:34:12 -0700
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 by: John Larkin - Wed, 5 Jul 2023 02:34 UTC

On Tue, 4 Jul 2023 23:34:28 +0000, tridac <syseng@gfsys.co.uk> wrote:

>On 6/30/23 22:39, John Larkin wrote:
>> On Fri, 30 Jun 2023 16:09:11 -0400, bitrex <user@example.net> wrote:
>>
>>> On 6/30/2023 1:39 PM, John Larkin wrote:
>>>>
>>>> I want to build a cheap-ish 8-channel DC power supply.
>>>>
>>>> Each channel can be a half-bridge, which is easy.
>>>>
>>>> If I filter with an inductor and a low-ESR cap, I get good ripple but
>>>> if I take feedback from the output the loop dynamics, the phase
>>>> margin, sucks.
>>>>
>>>> So why not take the voltage feedback from the switch node? No phase
>>>> lag! If we know the load current and the circuit losses, we can tweak
>>>> the output regulation pretty well.
>>>>
>>>> https://www.dropbox.com/scl/fi/sflylfz5z60wqi0p23276/P943_Sketch_1.jpg?dl=0&rlkey=3rv7i740a900a4vw6tjycmjhl
>>>>
>>>> The ADCs can even be synchronized to the PWM drive, so we can do FPGA
>>>> tricks to synchronously filter the maybe-ripply voltage feedback, or
>>>> just apply an arbitrarily complex lowpass filter ahead of the
>>>> closed-loop math.
>>>>
>>>> Digitizing the current allows even fancier loop dynamics.
>>>>
>
>Why not Sense the output voltage with a separate diode and smaller cap
>just to sense the voltage alone ?. Depends on what regulation you need.
>but why add complexity and cost with an fpga. Overthinking ?
>
>Chris
>

I posted the almost-final circuit below, repeated here

https://www.dropbox.com/scl/fi/pgw70e2ls16i66pj0hl5b/P943_Loop_1.jpg?rlkey=hc1ske5u41ylhfnazuj4t27k5&raw=1

It does combine fast feedback from the switch node and slow feedback
from the final output. That gives good dynamics and good regulation.

The board plugs into a mainframe and needs the FPGA to handshake with
the main controller, a MicroZed board. The FPGA allows a lot of
features too, like programmable slew rate, cc/cv/cr modes, data
logging, things like that. The Efinix part is just $10.

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