There are wire and pcb trace fusing calculators online, and in the
Saturn software and such. They use the Onderdonk or Preece’s
equations.

Onderdonk assumes no heat loss, so in theory 1 mA will melt #10 wire
if you wait long enough. Preece’s equation (from 1884!) assumes heat
loss from a round wire, presumably not insulated.

A PCB trace is wide and thin and loses heat to air and adjacent planes
(microstrip) or to two planes (stripline). Does anyone know of a
calculator for real-life PCB traces?

On Thu, 27 Jul 2023 07:19:08 -0700, John Larkin
<jlarkin@highlandSNIPMEtechnology.com> wrote:

>There are wire and pcb trace fusing calculators online, and in the
>Saturn software and such. They use the Onderdonk or Preece’s
>equations.
>
>Onderdonk assumes no heat loss, so in theory 1 mA will melt #10 wire
>if you wait long enough. Preece’s equation (from 1884!) assumes heat
>loss from a round wire, presumably not insulated.
>
>A PCB trace is wide and thin and loses heat to air and adjacent planes
>(microstrip) or to two planes (stripline). Does anyone know of a
>calculator for real-life PCB traces?

This one says that for a 10 amp trace, the inner-layer width needs to
be 740 mils... 3/4 of an inch!

https://www.4pcb.com/trace-width-calculator.html

That's crazy. And they show inner layers needing to be wider than
microstrips. Doesn't epoxy-glass conduct heat better than air?

They don't account for heat conduction to inner-layer planes either.

On Thursday, July 27, 2023 at 10:48:06 AM UTC-4, John Larkin wrote:
> On Thu, 27 Jul 2023 07:19:08 -0700, John Larkin
> <jla...@highlandSNIPMEtechnology.com> wrote:
>
> >There are wire and pcb trace fusing calculators online, and in the
> >Saturn software and such. They use the Onderdonk or Preece’s
> >equations.
> >
> >Onderdonk assumes no heat loss, so in theory 1 mA will melt #10 wire
> >if you wait long enough. Preece’s equation (from 1884!) assumes heat
> >loss from a round wire, presumably not insulated.
> >
> >A PCB trace is wide and thin and loses heat to air and adjacent planes
> >(microstrip) or to two planes (stripline). Does anyone know of a
> >calculator for real-life PCB traces?
> This one says that for a 10 amp trace, the inner-layer width needs to
> be 740 mils... 3/4 of an inch!
>
> https://www.4pcb.com/trace-width-calculator.html
>
> That's crazy. And they show inner layers needing to be wider than
> microstrips. Doesn't epoxy-glass conduct heat better than air?
>
> They don't account for heat conduction to inner-layer planes either.

Did you check out this more fundamental and comprehensive write-up:

https://www.researchgate.net/publication/286096911_Fusing_of_wires_by_electrical_current

torsdag den 27. juli 2023 kl. 16.48.06 UTC+2 skrev John Larkin:
> On Thu, 27 Jul 2023 07:19:08 -0700, John Larkin
> <jla...@highlandSNIPMEtechnology.com> wrote:
>
> >There are wire and pcb trace fusing calculators online, and in the
> >Saturn software and such. They use the Onderdonk or Preece’s
> >equations.
> >
> >Onderdonk assumes no heat loss, so in theory 1 mA will melt #10 wire
> >if you wait long enough. Preece’s equation (from 1884!) assumes heat
> >loss from a round wire, presumably not insulated.
> >
> >A PCB trace is wide and thin and loses heat to air and adjacent planes
> >(microstrip) or to two planes (stripline). Does anyone know of a
> >calculator for real-life PCB traces?
> This one says that for a 10 amp trace, the inner-layer width needs to
> be 740 mils... 3/4 of an inch!
>
> https://www.4pcb.com/trace-width-calculator.html
>
> That's crazy. And they show inner layers needing to be wider than
> microstrips. Doesn't epoxy-glass conduct heat better than air?
>
> They don't account for heat conduction to inner-layer planes either.

https://www.smps.us/pcb-calculator.html

On Thu, 27 Jul 2023 08:20:46 -0700 (PDT), Lasse Langwadt Christensen
<langwadt@fonz.dk> wrote:

>torsdag den 27. juli 2023 kl. 16.48.06 UTC+2 skrev John Larkin:
>> On Thu, 27 Jul 2023 07:19:08 -0700, John Larkin
>> <jla...@highlandSNIPMEtechnology.com> wrote:
>>
>> >There are wire and pcb trace fusing calculators online, and in the
>> >Saturn software and such. They use the Onderdonk or Preece’s
>> >equations.
>> >
>> >Onderdonk assumes no heat loss, so in theory 1 mA will melt #10 wire
>> >if you wait long enough. Preece’s equation (from 1884!) assumes heat
>> >loss from a round wire, presumably not insulated.
>> >
>> >A PCB trace is wide and thin and loses heat to air and adjacent planes
>> >(microstrip) or to two planes (stripline). Does anyone know of a
>> >calculator for real-life PCB traces?
>> This one says that for a 10 amp trace, the inner-layer width needs to
>> be 740 mils... 3/4 of an inch!
>>
>> https://www.4pcb.com/trace-width-calculator.html
>>
>> That's crazy. And they show inner layers needing to be wider than
>> microstrips. Doesn't epoxy-glass conduct heat better than air?
>>
>> They don't account for heat conduction to inner-layer planes either.
>
>https://www.smps.us/pcb-calculator.html

Entering

1 oz copper
5c rise
10 amps
62 mil pcb thickness
8 mils to a big plane
external trace

It claims that I need a trace 1580, or 560, or maybe 440 mils wide.

My private calculation, and experience, says that 100 mils wide would
be about right for the 5c temp rise, given that plane 8 mils below.
Imagine a trace that's an inch and a half wide for 10 amps!

It also says that internal traces have to be 3x as wide as surface
traces.

This is pitiful. The PCB thermal calculators seem to use random number
generators.

torsdag den 27. juli 2023 kl. 17.48.00 UTC+2 skrev John Larkin:
> On Thu, 27 Jul 2023 08:20:46 -0700 (PDT), Lasse Langwadt Christensen
> <lang...@fonz.dk> wrote:
>
> >torsdag den 27. juli 2023 kl. 16.48.06 UTC+2 skrev John Larkin:
> >> On Thu, 27 Jul 2023 07:19:08 -0700, John Larkin
> >> <jla...@highlandSNIPMEtechnology.com> wrote:
> >>
> >> >There are wire and pcb trace fusing calculators online, and in the
> >> >Saturn software and such. They use the Onderdonk or Preece’s
> >> >equations.
> >> >
> >> >Onderdonk assumes no heat loss, so in theory 1 mA will melt #10 wire
> >> >if you wait long enough. Preece’s equation (from 1884!) assumes heat
> >> >loss from a round wire, presumably not insulated.
> >> >
> >> >A PCB trace is wide and thin and loses heat to air and adjacent planes
> >> >(microstrip) or to two planes (stripline). Does anyone know of a
> >> >calculator for real-life PCB traces?
> >> This one says that for a 10 amp trace, the inner-layer width needs to
> >> be 740 mils... 3/4 of an inch!
> >>
> >> https://www.4pcb.com/trace-width-calculator.html
> >>
> >> That's crazy. And they show inner layers needing to be wider than
> >> microstrips. Doesn't epoxy-glass conduct heat better than air?
> >>
> >> They don't account for heat conduction to inner-layer planes either.
> >
> >https://www.smps.us/pcb-calculator.html
> Entering
>
> 1 oz copper
> 5c rise
> 10 amps
> 62 mil pcb thickness
> 8 mils to a big plane
> external trace
>
> It claims that I need a trace 1580, or 560, or maybe 440 mils wide.
>
> My private calculation, and experience, says that 100 mils wide would
> be about right for the 5c temp rise, given that plane 8 mils below.
> Imagine a trace that's an inch and a half wide for 10 amps!
>
> It also says that internal traces have to be 3x as wide as surface
> traces.
>
> This is pitiful. The PCB thermal calculators seem to use random number
> generators.

copper's resistance + ~0.4% per C so it should be easy enough get
some actually numbers with a test pcb and a powersupply

On Thu, 27 Jul 2023 09:24:02 -0700 (PDT), Lasse Langwadt Christensen
<langwadt@fonz.dk> wrote:

>torsdag den 27. juli 2023 kl. 17.48.00 UTC+2 skrev John Larkin:
>> On Thu, 27 Jul 2023 08:20:46 -0700 (PDT), Lasse Langwadt Christensen
>> <lang...@fonz.dk> wrote:
>>
>> >torsdag den 27. juli 2023 kl. 16.48.06 UTC+2 skrev John Larkin:
>> >> On Thu, 27 Jul 2023 07:19:08 -0700, John Larkin
>> >> <jla...@highlandSNIPMEtechnology.com> wrote:
>> >>
>> >> >There are wire and pcb trace fusing calculators online, and in the
>> >> >Saturn software and such. They use the Onderdonk or Preece’s
>> >> >equations.
>> >> >
>> >> >Onderdonk assumes no heat loss, so in theory 1 mA will melt #10 wire
>> >> >if you wait long enough. Preece’s equation (from 1884!) assumes heat
>> >> >loss from a round wire, presumably not insulated.
>> >> >
>> >> >A PCB trace is wide and thin and loses heat to air and adjacent planes
>> >> >(microstrip) or to two planes (stripline). Does anyone know of a
>> >> >calculator for real-life PCB traces?
>> >> This one says that for a 10 amp trace, the inner-layer width needs to
>> >> be 740 mils... 3/4 of an inch!
>> >>
>> >> https://www.4pcb.com/trace-width-calculator.html
>> >>
>> >> That's crazy. And they show inner layers needing to be wider than
>> >> microstrips. Doesn't epoxy-glass conduct heat better than air?
>> >>
>> >> They don't account for heat conduction to inner-layer planes either.
>> >
>> >https://www.smps.us/pcb-calculator.html
>> Entering
>>
>> 1 oz copper
>> 5c rise
>> 10 amps
>> 62 mil pcb thickness
>> 8 mils to a big plane
>> external trace
>>
>> It claims that I need a trace 1580, or 560, or maybe 440 mils wide.
>>
>> My private calculation, and experience, says that 100 mils wide would
>> be about right for the 5c temp rise, given that plane 8 mils below.
>> Imagine a trace that's an inch and a half wide for 10 amps!
>>
>> It also says that internal traces have to be 3x as wide as surface
>> traces.
>>
>> This is pitiful. The PCB thermal calculators seem to use random number
>> generators.
>
>copper's resistance + ~0.4% per C so it should be easy enough get
>some actually numbers with a test pcb and a powersupply

Yes, copper resistance can measure actual trace temps.

I probably have enough old multilayer boards around to do some
maybe-destructive testing. Baking a new proto board is a possibility,
and I could include some other circuits. I want to test the AP66300
switcher and eval boards can't be had now for some reason.

In article <8c05ci9uqpvr4cebltae4drf33d5iq3fd6@4ax.com>,
John Larkin <xx@yy.com> wrote:

>This one says that for a 10 amp trace, the inner-layer width needs to
>be 740 mils... 3/4 of an inch!
>
>https://www.4pcb.com/trace-width-calculator.html
>
>That's crazy. And they show inner layers needing to be wider than
>microstrips. Doesn't epoxy-glass conduct heat better than air?

Yes, it does (air's thermal conductivity is lousy) but that's not the
right question. Relatively little heat leaves the board by conduction
to air. Most of it leaves via convection (or forced-air).

Equally importantly: the higher thermal conductivity of the epoxy-
glass isn't magic. It still adds thermal resistance between the
heat source and the outside of the board, in addition to the
"surface to ambient" thermal resistance which both internal traces
and microstrips have to deal with.

>They don't account for heat conduction to inner-layer planes either.

If we neglect the presence of inner-plane flooded layers, then of
course the inner traces would need to be wider than the outer, for a
given amount of heat dissipation and acceptable temperature rise. The
thermal resistance to ambient for an inner layer is going to be higher
than that of the outer layers.

Every layer the heat has to go through on its way to ambient is going
to add thermal resistance. The thermal resistance to the two sides of
the board will combine in the usual parallel-resistance formula. For
a trace on the surface, the resulting resistance will be dominated by
the direct-to-air resistance on that side, and so it'll be lower than
a trace right in the middle.

Now, to add in the "inner layer" effect accurately, you'd have to give
an accurate model for the heatsinking ability of those inner planes.
What is _their_ thermal resistance to ambient, on a given board? Is
there a direct and efficient heat-path from the power and ground
planes out to ambient (e.g. big fat power-supply connectors and heavy
copper wire to some cold place) or are the power and ground planes
thermally "trapped inside" the board and mostly just moving heat
around inside the board?

You also would need to consider whether you're trying to get a valid
number for a board with just a few traces high-current traces, or for
"they're all going to be like this". If it's just one or two traces
(hotted up at any given time) you can probably treat your internal
planes as something like near-infinite heat-sinks to ambient, and get
away with a thinner trace. If you're designing a board which is going
to be full of these hot traces operating simultaneously, then you
can't make this assumption - the ability of the inner planes to
conduct all of that heat out to ambient is likely to be limited and
you'll have to limit your heat-generated-per-trace or the board as a
whole will cook itself.

I'd guess that the calculators are designed based on some conservative
(near to worst-case) simplifying assumptions. "So, you want to fill
your whole board with traces like this, and you can't count on your
internal planes sinking a lot of heat out to ambient? Do it this way,
keep your generated heat down to a minimum, and you can be reasonably
confident that the board probably won't cook itself to death before
the warranty expires."

If you want a more accurate set of numbers for your own specific
board design, you'll probably need to do some finite-element
thermal modeling based on your actual board layout, and tune
things manually based on your actual trace usage. If you've
got 2-3 energized relays on the board at a time, you'll probably
like the answers a lot better than if you're expecting to have
dozens of relays pulling current most of the time.

On a sunny day (Thu, 27 Jul 2023 08:47:50 -0700) it happened John Larkin
<jlarkin@highlandSNIPMEtechnology.com> wrote in
<kk35cip1b14524ebn9bhf5no3878s4fkpi@4ax.com>:

>On Thu, 27 Jul 2023 08:20:46 -0700 (PDT), Lasse Langwadt Christensen
><langwadt@fonz.dk> wrote:
>
>>torsdag den 27. juli 2023 kl. 16.48.06 UTC+2 skrev John Larkin:
>>> On Thu, 27 Jul 2023 07:19:08 -0700, John Larkin
>>> <jla...@highlandSNIPMEtechnology.com> wrote:
>>>
>>> >There are wire and pcb trace fusing calculators online, and in the
>>> >Saturn software and such. They use the Onderdonk or Preece�s
>>> >equations.
>>> >
>>> >Onderdonk assumes no heat loss, so in theory 1 mA will melt #10 wire
>>> >if you wait long enough. Preece�s equation (from 1884!) assumes heat
>>> >loss from a round wire, presumably not insulated.
>>> >
>>> >A PCB trace is wide and thin and loses heat to air and adjacent planes
>>> >(microstrip) or to two planes (stripline). Does anyone know of a
>>> >calculator for real-life PCB traces?
>>> This one says that for a 10 amp trace, the inner-layer width needs to
>>> be 740 mils... 3/4 of an inch!
>>>
>>> https://www.4pcb.com/trace-width-calculator.html
>>>
>>> That's crazy. And they show inner layers needing to be wider than
>>> microstrips. Doesn't epoxy-glass conduct heat better than air?
>>>
>>> They don't account for heat conduction to inner-layer planes either.
>>
>>https://www.smps.us/pcb-calculator.html
>
>Entering
>
>1 oz copper
>5c rise
>10 amps
>62 mil pcb thickness
>8 mils to a big plane
>external trace
>
>It claims that I need a trace 1580, or 560, or maybe 440 mils wide.
>
>My private calculation, and experience, says that 100 mils wide would
>be about right for the 5c temp rise, given that plane 8 mils below.
>Imagine a trace that's an inch and a half wide for 10 amps!
>
>It also says that internal traces have to be 3x as wide as surface
>traces.
>
>This is pitiful. The PCB thermal calculators seem to use random number
>generators.

And there is skin effect, as you work with pick-a-second pulses?

On Thu, 27 Jul 2023 10:34:09 -0700, dplatt@coop.radagast.org (Dave
Platt) wrote:

>In article <8c05ci9uqpvr4cebltae4drf33d5iq3fd6@4ax.com>,
>John Larkin <xx@yy.com> wrote:
>
>>This one says that for a 10 amp trace, the inner-layer width needs to
>>be 740 mils... 3/4 of an inch!
>>
>>https://www.4pcb.com/trace-width-calculator.html
>>
>>That's crazy. And they show inner layers needing to be wider than
>>microstrips. Doesn't epoxy-glass conduct heat better than air?
>
>Yes, it does (air's thermal conductivity is lousy) but that's not the
>right question. Relatively little heat leaves the board by conduction
>to air. Most of it leaves via convection (or forced-air).
>
>Equally importantly: the higher thermal conductivity of the epoxy-
>glass isn't magic. It still adds thermal resistance between the
>heat source and the outside of the board, in addition to the
>"surface to ambient" thermal resistance which both internal traces
>and microstrips have to deal with.

If you thermal image the surfaces of a board that has a hot trace
inside, the hot area of the board will be wider than the trace. For a
narrow trace, much wider. The epoxy spreads the heat and allows the
trace to contact a lot more air on both sides.

>
>>They don't account for heat conduction to inner-layer planes either.
>
>If we neglect the presence of inner-plane flooded layers, then of
>course the inner traces would need to be wider than the outer, for a
>given amount of heat dissipation and acceptable temperature rise. The
>thermal resistance to ambient for an inner layer is going to be higher
>than that of the outer layers.

A full-board ground plane, or better yet a ground plane and a couple
of power planes, will spread the heat over the entire board surface.

An inner layer trace could dump heat through thin FR4 layers to
thermally conductive planes above and below.

>
>Every layer the heat has to go through on its way to ambient is going
>to add thermal resistance.

Unless the spreading effect wins. FR4 conducts heat about 12x better
than air.

> The thermal resistance to the two sides of
>the board will combine in the usual parallel-resistance formula. For
>a trace on the surface, the resulting resistance will be dominated by
>the direct-to-air resistance on that side, and so it'll be lower than
>a trace right in the middle.
>
>Now, to add in the "inner layer" effect accurately, you'd have to give
>an accurate model for the heatsinking ability of those inner planes.
>What is _their_ thermal resistance to ambient, on a given board? Is
>there a direct and efficient heat-path from the power and ground
>planes out to ambient (e.g. big fat power-supply connectors and heavy
>copper wire to some cold place) or are the power and ground planes
>thermally "trapped inside" the board and mostly just moving heat
>around inside the board?
>
>You also would need to consider whether you're trying to get a valid
>number for a board with just a few traces high-current traces, or for
>"they're all going to be like this". If it's just one or two traces
>(hotted up at any given time) you can probably treat your internal
>planes as something like near-infinite heat-sinks to ambient, and get
>away with a thinner trace. If you're designing a board which is going
>to be full of these hot traces operating simultaneously, then you
>can't make this assumption - the ability of the inner planes to
>conduct all of that heat out to ambient is likely to be limited and
>you'll have to limit your heat-generated-per-trace or the board as a
>whole will cook itself.
>
>I'd guess that the calculators are designed based on some conservative
>(near to worst-case) simplifying assumptions. "So, you want to fill
>your whole board with traces like this, and you can't count on your
>internal planes sinking a lot of heat out to ambient? Do it this way,
>keep your generated heat down to a minimum, and you can be reasonably
>confident that the board probably won't cook itself to death before
>the warranty expires."
>
>If you want a more accurate set of numbers for your own specific
>board design, you'll probably need to do some finite-element
>thermal modeling based on your actual board layout, and tune
>things manually based on your actual trace usage. If you've
>got 2-3 energized relays on the board at a time, you'll probably
>like the answers a lot better than if you're expecting to have
>dozens of relays pulling current most of the time.
>
>
>
>
I'll just experimant with a real board. Buying and learning the FEM
software would be 50x as hard.

I am disappointed how little that hard numbers are available. And the
wild range of calculated results.

On Thu, 27 Jul 2023 21:57:29 GMT, Jan Panteltje <alien@comet.invalid>
wrote:

>On a sunny day (Thu, 27 Jul 2023 08:47:50 -0700) it happened John Larkin
><jlarkin@highlandSNIPMEtechnology.com> wrote in
><kk35cip1b14524ebn9bhf5no3878s4fkpi@4ax.com>:
>
>>On Thu, 27 Jul 2023 08:20:46 -0700 (PDT), Lasse Langwadt Christensen
>><langwadt@fonz.dk> wrote:
>>
>>>torsdag den 27. juli 2023 kl. 16.48.06 UTC+2 skrev John Larkin:
>>>> On Thu, 27 Jul 2023 07:19:08 -0700, John Larkin
>>>> <jla...@highlandSNIPMEtechnology.com> wrote:
>>>>
>>>> >There are wire and pcb trace fusing calculators online, and in the
>>>> >Saturn software and such. They use the Onderdonk or Preece’s
>>>> >equations.
>>>> >
>>>> >Onderdonk assumes no heat loss, so in theory 1 mA will melt #10 wire
>>>> >if you wait long enough. Preece’s equation (from 1884!) assumes heat
>>>> >loss from a round wire, presumably not insulated.
>>>> >
>>>> >A PCB trace is wide and thin and loses heat to air and adjacent planes
>>>> >(microstrip) or to two planes (stripline). Does anyone know of a
>>>> >calculator for real-life PCB traces?
>>>> This one says that for a 10 amp trace, the inner-layer width needs to
>>>> be 740 mils... 3/4 of an inch!
>>>>
>>>> https://www.4pcb.com/trace-width-calculator.html
>>>>
>>>> That's crazy. And they show inner layers needing to be wider than
>>>> microstrips. Doesn't epoxy-glass conduct heat better than air?
>>>>
>>>> They don't account for heat conduction to inner-layer planes either.
>>>
>>>https://www.smps.us/pcb-calculator.html
>>
>>Entering
>>
>>1 oz copper
>>5c rise
>>10 amps
>>62 mil pcb thickness
>>8 mils to a big plane
>>external trace
>>
>>It claims that I need a trace 1580, or 560, or maybe 440 mils wide.
>>
>>My private calculation, and experience, says that 100 mils wide would
>>be about right for the 5c temp rise, given that plane 8 mils below.
>>Imagine a trace that's an inch and a half wide for 10 amps!
>>
>>It also says that internal traces have to be 3x as wide as surface
>>traces.
>>
>>This is pitiful. The PCB thermal calculators seem to use random number
>>generators.
>
>And there is skin effect, as you work with pick-a-second pulses?

Not this one. It's basically a cable tester, for slow klunky signals
and power.

On Thursday, July 27, 2023 at 3:17:51 PM UTC-7, John Larkin wrote:
> On Thu, 27 Jul 2023 21:57:29 GMT, Jan Panteltje <al...@comet.invalid>
> wrote:
> >On a sunny day (Thu, 27 Jul 2023 08:47:50 -0700) it happened John Larkin
> ><jla...@highlandSNIPMEtechnology.com> wrote in
> ><kk35cip1b14524ebn...@4ax.com>:
> >
> >>On Thu, 27 Jul 2023 08:20:46 -0700 (PDT), Lasse Langwadt Christensen
> >><lang...@fonz.dk> wrote:
> >>
> >>>torsdag den 27. juli 2023 kl. 16.48.06 UTC+2 skrev John Larkin:
> >>>> On Thu, 27 Jul 2023 07:19:08 -0700, John Larkin
> >>>> <jla...@highlandSNIPMEtechnology.com> wrote:
> >>>>
> >>>> >There are wire and pcb trace fusing calculators online, and in the
> >>>> >Saturn software and such. They use the Onderdonk or Preece’s
> >>>> >equations.
> >>>> >
> >>>> >Onderdonk assumes no heat loss, so in theory 1 mA will melt #10 wire
> >>>> >if you wait long enough. Preece’s equation (from 1884!) assumes heat
> >>>> >loss from a round wire, presumably not insulated.
> >>>> >
> >>>> >A PCB trace is wide and thin and loses heat to air and adjacent planes
> >>>> >(microstrip) or to two planes (stripline). Does anyone know of a
> >>>> >calculator for real-life PCB traces?
> >>>> This one says that for a 10 amp trace, the inner-layer width needs to
> >>>> be 740 mils... 3/4 of an inch!
> >>>>
> >>>> https://www.4pcb.com/trace-width-calculator.html
> >>>>
> >>>> That's crazy. And they show inner layers needing to be wider than
> >>>> microstrips. Doesn't epoxy-glass conduct heat better than air?
> >>>>
> >>>> They don't account for heat conduction to inner-layer planes either.
> >>>
> >>>https://www.smps.us/pcb-calculator.html
> >>
> >>Entering
> >>
> >>1 oz copper
> >>5c rise
> >>10 amps
> >>62 mil pcb thickness
> >>8 mils to a big plane
> >>external trace
> >>
> >>It claims that I need a trace 1580, or 560, or maybe 440 mils wide.
> >>
> >>My private calculation, and experience, says that 100 mils wide would
> >>be about right for the 5c temp rise, given that plane 8 mils below.
> >>Imagine a trace that's an inch and a half wide for 10 amps!
> >>
> >>It also says that internal traces have to be 3x as wide as surface
> >>traces.
> >>
> >>This is pitiful. The PCB thermal calculators seem to use random number
> >>generators.
> >
> >And there is skin effect, as you work with pick-a-second pulses?
> Not this one. It's basically a cable tester, for slow klunky signals
> and power.
Over the years, Doug Brooks has expended much ink (bytes?) over PCB trace currents. I've made mental note of this, in case I needed to explore this (I haven't the need ... yet). FYI here is an article of his from the Signal Integrity Journal (March 10, 2020):

https://www.signalintegrityjournal.com/articles/1596-internal-trace-temperatures-more-complicated-than-we-think

I make no claims made to the validity of his analysis.
-Mark

On Thursday, July 27, 2023 at 6:07:13 PM UTC-4, John Larkin wrote:
> On Thu, 27 Jul 2023 10:34:09 -0700, dpl...@coop.radagast.org (Dave
> Platt) wrote:
>
> >In article <8c05ci9uqpvr4cebl...@4ax.com>,
> >John Larkin <x...@yy.com> wrote:
> >
> >>This one says that for a 10 amp trace, the inner-layer width needs to
> >>be 740 mils... 3/4 of an inch!
> >>
> >>https://www.4pcb.com/trace-width-calculator.html
> >>
> >>That's crazy. And they show inner layers needing to be wider than
> >>microstrips. Doesn't epoxy-glass conduct heat better than air?
> >
> >Yes, it does (air's thermal conductivity is lousy) but that's not the
> >right question. Relatively little heat leaves the board by conduction
> >to air. Most of it leaves via convection (or forced-air).
> >
> >Equally importantly: the higher thermal conductivity of the epoxy-
> >glass isn't magic. It still adds thermal resistance between the
> >heat source and the outside of the board, in addition to the
> >"surface to ambient" thermal resistance which both internal traces
> >and microstrips have to deal with.
> If you thermal image the surfaces of a board that has a hot trace
> inside, the hot area of the board will be wider than the trace. For a
> narrow trace, much wider. The epoxy spreads the heat and allows the
> trace to contact a lot more air on both sides.
> >
> >>They don't account for heat conduction to inner-layer planes either.
> >
> >If we neglect the presence of inner-plane flooded layers, then of
> >course the inner traces would need to be wider than the outer, for a
> >given amount of heat dissipation and acceptable temperature rise. The
> >thermal resistance to ambient for an inner layer is going to be higher
> >than that of the outer layers.
> A full-board ground plane, or better yet a ground plane and a couple
> of power planes, will spread the heat over the entire board surface.
>
> An inner layer trace could dump heat through thin FR4 layers to
> thermally conductive planes above and below.
> >
> >Every layer the heat has to go through on its way to ambient is going
> >to add thermal resistance.
> Unless the spreading effect wins. FR4 conducts heat about 12x better
> than air.
> > The thermal resistance to the two sides of
> >the board will combine in the usual parallel-resistance formula. For
> >a trace on the surface, the resulting resistance will be dominated by
> >the direct-to-air resistance on that side, and so it'll be lower than
> >a trace right in the middle.
> >
> >Now, to add in the "inner layer" effect accurately, you'd have to give
> >an accurate model for the heatsinking ability of those inner planes.
> >What is _their_ thermal resistance to ambient, on a given board? Is
> >there a direct and efficient heat-path from the power and ground
> >planes out to ambient (e.g. big fat power-supply connectors and heavy
> >copper wire to some cold place) or are the power and ground planes
> >thermally "trapped inside" the board and mostly just moving heat
> >around inside the board?
> >
> >You also would need to consider whether you're trying to get a valid
> >number for a board with just a few traces high-current traces, or for
> >"they're all going to be like this". If it's just one or two traces
> >(hotted up at any given time) you can probably treat your internal
> >planes as something like near-infinite heat-sinks to ambient, and get
> >away with a thinner trace. If you're designing a board which is going
> >to be full of these hot traces operating simultaneously, then you
> >can't make this assumption - the ability of the inner planes to
> >conduct all of that heat out to ambient is likely to be limited and
> >you'll have to limit your heat-generated-per-trace or the board as a
> >whole will cook itself.
> >
> >I'd guess that the calculators are designed based on some conservative
> >(near to worst-case) simplifying assumptions. "So, you want to fill
> >your whole board with traces like this, and you can't count on your
> >internal planes sinking a lot of heat out to ambient? Do it this way,
> >keep your generated heat down to a minimum, and you can be reasonably
> >confident that the board probably won't cook itself to death before
> >the warranty expires."
> >
> >If you want a more accurate set of numbers for your own specific
> >board design, you'll probably need to do some finite-element
> >thermal modeling based on your actual board layout, and tune
> >things manually based on your actual trace usage. If you've
> >got 2-3 energized relays on the board at a time, you'll probably
> >like the answers a lot better than if you're expecting to have
> >dozens of relays pulling current most of the time.
> >
> >
> >
> >
> I'll just experimant with a real board. Buying and learning the FEM
> software would be 50x as hard.
>
> I am disappointed how little that hard numbers are available. And the
> wild range of calculated results.

They're probably just pulling numbers out the the nebulous IPC-2221 charts, that no one seems to understand or know of the origins. Apparently temperature is everything and the starting point for a specification, not an aside you throw into a calculator. The reason being the drastic difference in temperature expansion of Cu, at something like 5ppm, and epoxy resin, at something like 350ppm. The epoxy numbers are for T "near" Tg, the glass transition temperature of the material. Based on that bs the IPC publishes a formula I = K * dT^0.44 * (W*H)^0.725 with obvious notation. That particular result gets around anyone having to figure out a safe stress limit on the copper/ substrate bonding induced by expansion. I'm sure in addition to an outright separation there is the issue of cycling the material interface through repeated expansions. If your numbers for trace width are ridiculously big then there are the options of using heavier CU, the W*H part, and using a high Tg material PCB, the allowable dT part. There are plenty of high Tg PCB manufacturers out there and you should be consulting with them. "High TG PCB"

https://www.us-tech.com/RelId/2687527/ISvars/default/Heavy_Copper_Design_Considerations_Part_1_Traces_and_Temperature.htm

On Thursday, July 27, 2023 at 6:07:13 PM UTC-4, John Larkin wrote:
> On Thu, 27 Jul 2023 10:34:09 -0700, dpl...@coop.radagast.org (Dave
> Platt) wrote:
>
> >In article <8c05ci9uqpvr4cebl...@4ax.com>,
> >John Larkin <x...@yy.com> wrote:
> >
> >>This one says that for a 10 amp trace, the inner-layer width needs to
> >>be 740 mils... 3/4 of an inch!
> >>
> >>https://www.4pcb.com/trace-width-calculator.html
> >>
> >>That's crazy. And they show inner layers needing to be wider than
> >>microstrips. Doesn't epoxy-glass conduct heat better than air?
> >
> >Yes, it does (air's thermal conductivity is lousy) but that's not the
> >right question. Relatively little heat leaves the board by conduction
> >to air. Most of it leaves via convection (or forced-air).
> >
> >Equally importantly: the higher thermal conductivity of the epoxy-
> >glass isn't magic. It still adds thermal resistance between the
> >heat source and the outside of the board, in addition to the
> >"surface to ambient" thermal resistance which both internal traces
> >and microstrips have to deal with.
> If you thermal image the surfaces of a board that has a hot trace
> inside, the hot area of the board will be wider than the trace. For a
> narrow trace, much wider. The epoxy spreads the heat and allows the
> trace to contact a lot more air on both sides.
> >
> >>They don't account for heat conduction to inner-layer planes either.
> >
> >If we neglect the presence of inner-plane flooded layers, then of
> >course the inner traces would need to be wider than the outer, for a
> >given amount of heat dissipation and acceptable temperature rise. The
> >thermal resistance to ambient for an inner layer is going to be higher
> >than that of the outer layers.
> A full-board ground plane, or better yet a ground plane and a couple
> of power planes, will spread the heat over the entire board surface.
>
> An inner layer trace could dump heat through thin FR4 layers to
> thermally conductive planes above and below.
> >
> >Every layer the heat has to go through on its way to ambient is going
> >to add thermal resistance.
> Unless the spreading effect wins. FR4 conducts heat about 12x better
> than air.
> > The thermal resistance to the two sides of
> >the board will combine in the usual parallel-resistance formula. For
> >a trace on the surface, the resulting resistance will be dominated by
> >the direct-to-air resistance on that side, and so it'll be lower than
> >a trace right in the middle.
> >
> >Now, to add in the "inner layer" effect accurately, you'd have to give
> >an accurate model for the heatsinking ability of those inner planes.
> >What is _their_ thermal resistance to ambient, on a given board? Is
> >there a direct and efficient heat-path from the power and ground
> >planes out to ambient (e.g. big fat power-supply connectors and heavy
> >copper wire to some cold place) or are the power and ground planes
> >thermally "trapped inside" the board and mostly just moving heat
> >around inside the board?
> >
> >You also would need to consider whether you're trying to get a valid
> >number for a board with just a few traces high-current traces, or for
> >"they're all going to be like this". If it's just one or two traces
> >(hotted up at any given time) you can probably treat your internal
> >planes as something like near-infinite heat-sinks to ambient, and get
> >away with a thinner trace. If you're designing a board which is going
> >to be full of these hot traces operating simultaneously, then you
> >can't make this assumption - the ability of the inner planes to
> >conduct all of that heat out to ambient is likely to be limited and
> >you'll have to limit your heat-generated-per-trace or the board as a
> >whole will cook itself.
> >
> >I'd guess that the calculators are designed based on some conservative
> >(near to worst-case) simplifying assumptions. "So, you want to fill
> >your whole board with traces like this, and you can't count on your
> >internal planes sinking a lot of heat out to ambient? Do it this way,
> >keep your generated heat down to a minimum, and you can be reasonably
> >confident that the board probably won't cook itself to death before
> >the warranty expires."
> >
> >If you want a more accurate set of numbers for your own specific
> >board design, you'll probably need to do some finite-element
> >thermal modeling based on your actual board layout, and tune
> >things manually based on your actual trace usage. If you've
> >got 2-3 energized relays on the board at a time, you'll probably
> >like the answers a lot better than if you're expecting to have
> >dozens of relays pulling current most of the time.
> >
> >
> >
> >
> I'll just experimant with a real board. Buying and learning the FEM
> software would be 50x as hard.
>
> I am disappointed how little that hard numbers are available. And the
> wild range of calculated results.

The approach of trace fusing is ridiculous, your board will be destroyed long before then. You should be focusing on allowable dT, which will be way, way less than the 2,000oF melting temperature of Cu.

On 7/29/23 9:54 AM, Fred Bloggs wrote:
> They're probably just pulling numbers out the the nebulous IPC-2221 charts, that no one seems to understand or know of the origins. Apparently temperature is everything and the starting point for a specification, not an aside you throw into a calculator. The reason being the drastic difference in temperature expansion of Cu, at something like 5ppm, and epoxy resin, at something like 350ppm. The epoxy numbers are for T "near" Tg, the glass transition temperature of the material. Based on that bs the IPC publishes a formula I = K * dT^0.44 * (W*H)^0.725 with obvious notation. That particular result gets around anyone having to figure out a safe stress limit on the copper/ substrate bonding induced by expansion. I'm sure in addition to an outright separation there is the issue of cycling the material interface through repeated expansions. If your numbers for trace width are ridiculously big then there are the options of using heavier CU, the W*H part, and using a high Tg material PCB, the allowable dT part. There are plenty of high Tg PCB manufacturers out there and you should be consulting with them. "High TG PCB"
>
> https://www.us-tech.com/RelId/2687527/ISvars/default/Heavy_Copper_Design_Considerations_Part_1_Traces_and_Temperature.htm
If you are pushing the limits of maximum temperature due to thermal
expansion and/or the number of temperature cycles, I wonder if placing a
number of small round holes in wide traces and planes would help? Not a
hole through the fiberglass, just a hole through the copper much smaller
than the width of a trace. That would allow resin to flow in and fill
the hole during manufacture and should "pin" the trace to resist lateral
movement and delamination. Hopefully the loss of electrical performance
could be kept small for a substantial increase in the mechanical strength.
--
Regards,
Carl

On Saturday, July 29, 2023 at 12:09:07 PM UTC-4, Carl wrote:
> On 7/29/23 9:54 AM, Fred Bloggs wrote:
>
> > They're probably just pulling numbers out the the nebulous IPC-2221 charts, that no one seems to understand or know of the origins. Apparently temperature is everything and the starting point for a specification, not an aside you throw into a calculator. The reason being the drastic difference in temperature expansion of Cu, at something like 5ppm, and epoxy resin, at something like 350ppm. The epoxy numbers are for T "near" Tg, the glass transition temperature of the material. Based on that bs the IPC publishes a formula I = K * dT^0.44 * (W*H)^0.725 with obvious notation. That particular result gets around anyone having to figure out a safe stress limit on the copper/ substrate bonding induced by expansion. I'm sure in addition to an outright separation there is the issue of cycling the material interface through repeated expansions. If your numbers for trace width are ridiculously big then there are the options of using heavier CU, the W*H part, and using a high Tg material PCB, the allowable dT part. There are plenty of high Tg PCB manufacturers out there and you should be consulting with them. "High TG PCB"
> >
> > https://www.us-tech.com/RelId/2687527/ISvars/default/Heavy_Copper_Design_Considerations_Part_1_Traces_and_Temperature.htm
> If you are pushing the limits of maximum temperature due to thermal
> expansion and/or the number of temperature cycles, I wonder if placing a
> number of small round holes in wide traces and planes would help? Not a
> hole through the fiberglass, just a hole through the copper much smaller
> than the width of a trace. That would allow resin to flow in and fill
> the hole during manufacture and should "pin" the trace to resist lateral
> movement and delamination. Hopefully the loss of electrical performance
> could be kept small for a substantial increase in the mechanical strength..

I'm not seeing how that will help. When the epoxy starts growing, the whole side-to-side footprint under the trace starts growing whereas the copper wants to maintain its original width. If it gets out of hand either the copper will split or the bonding lets go or both. As long as that strain stays under what's called the yield limit (temperature dependent), the copper will stay intact and return to its original cold dimensions when the temperature declines. The resin manufacturer will know those details and should be able to recommend a maximum dT to achieve maximum product longevity.

>
> --
> Regards,
> Carl

On Sat, 29 Jul 2023 09:38:40 -0700 (PDT), Fred Bloggs
<bloggs.fredbloggs.fred@gmail.com> wrote:

>On Saturday, July 29, 2023 at 12:09:07?PM UTC-4, Carl wrote:
>> On 7/29/23 9:54 AM, Fred Bloggs wrote:
>>
>> > They're probably just pulling numbers out the the nebulous IPC-2221 charts, that no one seems to understand or know of the origins. Apparently temperature is everything and the starting point for a specification, not an aside you throw into a calculator. The reason being the drastic difference in temperature expansion of Cu, at something like 5ppm, and epoxy resin, at something like 350ppm. The epoxy numbers are for T "near" Tg, the glass transition temperature of the material. Based on that bs the IPC publishes a formula I = K * dT^0.44 * (W*H)^0.725 with obvious notation. That particular result gets around anyone having to figure out a safe stress limit on the copper/ substrate bonding induced by expansion. I'm sure in addition to an outright separation there is the issue of cycling the material interface through repeated expansions. If your numbers for trace width are ridiculously big then there are the options of using heavier CU, the W*H part, and using a high Tg material
>PCB, the allowable dT part. There are plenty of high Tg PCB manufacturers out there and you should be consulting with them. "High TG PCB"
>> >
>> > https://www.us-tech.com/RelId/2687527/ISvars/default/Heavy_Copper_Design_Considerations_Part_1_Traces_and_Temperature.htm
>> If you are pushing the limits of maximum temperature due to thermal
>> expansion and/or the number of temperature cycles, I wonder if placing a
>> number of small round holes in wide traces and planes would help? Not a
>> hole through the fiberglass, just a hole through the copper much smaller
>> than the width of a trace. That would allow resin to flow in and fill
>> the hole during manufacture and should "pin" the trace to resist lateral
>> movement and delamination. Hopefully the loss of electrical performance
>> could be kept small for a substantial increase in the mechanical strength.
>
>I'm not seeing how that will help. When the epoxy starts growing, the whole side-to-side footprint under the trace starts growing whereas the copper wants to maintain its original width. If it gets out of hand either the copper will split or the bonding lets go or both. As long as that strain stays under what's called the yield limit (temperature dependent), the copper will stay intact and return to its original cold dimensions when the temperature declines. The resin manufacturer will know those details and should be able to recommend a maximum dT to achieve maximum product longevity.
>
>>
>> --
>> Regards,
>> Carl

Mechanical stresses won't be an issue. Toasting the epoxy-glass will.

I've never seen a board self-destruct from current-induced thermal
expansion. They make boats and bathtubs and Corvettes from
epoxy-glass.

I have seen a few fused traces.

On 7/29/23 12:38 PM, Fred Bloggs wrote:
> On Saturday, July 29, 2023 at 12:09:07 PM UTC-4, Carl wrote:
>> On 7/29/23 9:54 AM, Fred Bloggs wrote:
>>
>>> They're probably just pulling numbers out the the nebulous IPC-2221 charts, that no one seems to understand or know of the origins. Apparently temperature is everything and the starting point for a specification, not an aside you throw into a calculator. The reason being the drastic difference in temperature expansion of Cu, at something like 5ppm, and epoxy resin, at something like 350ppm. The epoxy numbers are for T "near" Tg, the glass transition temperature of the material. Based on that bs the IPC publishes a formula I = K * dT^0.44 * (W*H)^0.725 with obvious notation. That particular result gets around anyone having to figure out a safe stress limit on the copper/ substrate bonding induced by expansion. I'm sure in addition to an outright separation there is the issue of cycling the material interface through repeated expansions. If your numbers for trace width are ridiculously big then there are the options of using heavier CU, the W*H part, and using a high Tg material PCB, the allowable dT part. There are plenty of high Tg PCB manufacturers out there and you should be consulting with them. "High TG PCB"
>>>
>>> https://www.us-tech.com/RelId/2687527/ISvars/default/Heavy_Copper_Design_Considerations_Part_1_Traces_and_Temperature.htm
>> If you are pushing the limits of maximum temperature due to thermal
>> expansion and/or the number of temperature cycles, I wonder if placing a
>> number of small round holes in wide traces and planes would help? Not a
>> hole through the fiberglass, just a hole through the copper much smaller
>> than the width of a trace. That would allow resin to flow in and fill
>> the hole during manufacture and should "pin" the trace to resist lateral
>> movement and delamination. Hopefully the loss of electrical performance
>> could be kept small for a substantial increase in the mechanical strength.
>
> I'm not seeing how that will help. When the epoxy starts growing, the whole side-to-side footprint under the trace starts growing whereas the copper wants to maintain its original width. If it gets out of hand either the copper will split or the bonding lets go or both. As long as that strain stays under what's called the yield limit (temperature dependent), the copper will stay intact and return to its original cold dimensions when the temperature declines. The resin manufacturer will know those details and should be able to recommend a maximum dT to achieve maximum product longevity.
>
>>
>> --
>> Regards,
>> Carl
I was making the assumption that the yield strength of the copper would
be greater than the bonding strength of the copper to the substrate so
that using the holes to increase the bonding strength of the copper to
the substrate would increase the failure strength of the assembly. If
they stay bound together then localized bending or curling could relieve
some of the stress by spreading it out instead of keeping it localized
to pop the copper off the substrate. May not make enough of a
difference to matter but it seems a simple, cheap modification to at
least try if JL is going to test a few boards to destruction :-).
--
Regards,
Carl

On a sunny day (Sat, 29 Jul 2023 10:15:18 -0700) it happened John Larkin
<jlarkin@highlandSNIPMEtechnology.com> wrote in
<j1iacipp92fe2q7gf945kp6ljp6klve8ko@4ax.com>:

>On Sat, 29 Jul 2023 09:38:40 -0700 (PDT), Fred Bloggs
><bloggs.fredbloggs.fred@gmail.com> wrote:
>
>>On Saturday, July 29, 2023 at 12:09:07?PM UTC-4, Carl wrote:
>>> On 7/29/23 9:54 AM, Fred Bloggs wrote:
>>>
>>> > They're probably just pulling numbers out the the nebulous IPC-2221 charts, that no one seems to understand or know of the
>>> > origins. Apparently temperature is everything and the starting point for a specification, not an aside you throw into a
>>> > calculator. The reason being the drastic difference in temperature expansion of Cu, at something like 5ppm, and epoxy resin, at
>>> > something like 350ppm. The epoxy numbers are for T "near" Tg, the glass transition temperature of the material. Based on that bs the IPC
>>> > publishes a formula I = K * dT^0.44 * (W*H)^0.725 with obvious notation. That particular result gets around anyone having to
>>> > figure out a safe stress limit on the copper/ substrate bonding induced by expansion. I'm sure in addition to an outright
>>> > separation there is the issue of cycling the material interface through repeated expansions. If your numbers for trace width are
>>> > ridiculously big then there are the options of using heavier CU, the W*H part, and using a high Tg material
>>PCB, the allowable dT part. There are plenty of high Tg PCB manufacturers out there and you should be consulting with them.
>>"High TG PCB"
>>> >
>>> > https://www.us-tech.com/RelId/2687527/ISvars/default/Heavy_Copper_Design_Considerations_Part_1_Traces_and_Temperature.htm
>>> If you are pushing the limits of maximum temperature due to thermal
>>> expansion and/or the number of temperature cycles, I wonder if placing a
>>> number of small round holes in wide traces and planes would help? Not a
>>> hole through the fiberglass, just a hole through the copper much smaller
>>> than the width of a trace. That would allow resin to flow in and fill
>>> the hole during manufacture and should "pin" the trace to resist lateral
>>> movement and delamination. Hopefully the loss of electrical performance
>>> could be kept small for a substantial increase in the mechanical strength.
>>
>>I'm not seeing how that will help. When the epoxy starts growing, the whole side-to-side footprint under the trace starts
>>growing whereas the copper wants to maintain its original width. If it gets out of hand either the copper will split or the bonding
>>lets go or both. As long as that strain stays under what's called the yield limit (temperature dependent), the copper will stay
>>intact and return to its original cold dimensions when the temperature declines. The resin manufacturer will know those details
>>and should be able to recommend a maximum dT to achieve maximum product longevity.
>>
>>>
>>> --
>>> Regards,
>>> Carl
>
>Mechanical stresses won't be an issue. Toasting the epoxy-glass will.
>
>I've never seen a board self-destruct from current-induced thermal
>expansion. They make boats and bathtubs and Corvettes from
>epoxy-glass.

Hey, I had some TV sets in for repair that were hit by lightning
Several tracks just had evaporated.
Managed to fix it.. needed some part replacement too.

>I have seen a few fused traces.

Yes

On Saturday, 29 July 2023 at 18:16:44 UTC+1, John Larkin wrote:
> On Sat, 29 Jul 2023 09:38:40 -0700 (PDT), Fred Bloggs
> <bloggs.fred...@gmail.com> wrote:
> >On Saturday, July 29, 2023 at 12:09:07?PM UTC-4, Carl wrote:
> >> On 7/29/23 9:54 AM, Fred Bloggs wrote:
> >>
> >> > They're probably just pulling numbers out the the nebulous IPC-2221 charts, that no one seems to understand or know of the origins. Apparently temperature is everything and the starting point for a specification, not an aside you throw into a calculator. The reason being the drastic difference in temperature expansion of Cu, at something like 5ppm, and epoxy resin, at something like 350ppm. The epoxy numbers are for T "near" Tg, the glass transition temperature of the material. Based on that bs the IPC publishes a formula I = K * dT^0.44 * (W*H)^0.725 with obvious notation. That particular result gets around anyone having to figure out a safe stress limit on the copper/ substrate bonding induced by expansion. I'm sure in addition to an outright separation there is the issue of cycling the material interface through repeated expansions. If your numbers for trace width are ridiculously big then there are the options of using heavier CU, the W*H part, and using a high Tg material
> >PCB, the allowable dT part. There are plenty of high Tg PCB manufacturers out there and you should be consulting with them. "High TG PCB"
> >> >
> >> > https://www.us-tech.com/RelId/2687527/ISvars/default/Heavy_Copper_Design_Considerations_Part_1_Traces_and_Temperature.htm
> >> If you are pushing the limits of maximum temperature due to thermal
> >> expansion and/or the number of temperature cycles, I wonder if placing a
> >> number of small round holes in wide traces and planes would help? Not a
> >> hole through the fiberglass, just a hole through the copper much smaller
> >> than the width of a trace. That would allow resin to flow in and fill
> >> the hole during manufacture and should "pin" the trace to resist lateral
> >> movement and delamination. Hopefully the loss of electrical performance
> >> could be kept small for a substantial increase in the mechanical strength.
> >
> >I'm not seeing how that will help. When the epoxy starts growing, the whole side-to-side footprint under the trace starts growing whereas the copper wants to maintain its original width. If it gets out of hand either the copper will split or the bonding lets go or both. As long as that strain stays under what's called the yield limit (temperature dependent), the copper will stay intact and return to its original cold dimensions when the temperature declines. The resin manufacturer will know those details and should be able to recommend a maximum dT to achieve maximum product longevity.
> >
> >>
> >> --
> >> Regards,
> >> Carl
> Mechanical stresses won't be an issue. Toasting the epoxy-glass will.
>
> I've never seen a board self-destruct from current-induced thermal
> expansion. They make boats and bathtubs and Corvettes from
> epoxy-glass.
>
> I have seen a few fused traces.

I've seen successfully fused traces, typically where the overload was massive. I've seen many more where the result was a pile of conductive arcing carbon & junk. If you must use a trace as a fuse, I'd at least give it lots of clearance. And don't be surprised by a messy arcing shorting result.

On Sat, 29 Jul 2023 13:23:19 -0400, Carl <carl.ijamesxx@yyverizon.net>
wrote:

>On 7/29/23 12:38 PM, Fred Bloggs wrote:
>> On Saturday, July 29, 2023 at 12:09:07?PM UTC-4, Carl wrote:
>>> On 7/29/23 9:54 AM, Fred Bloggs wrote:
>>>
>>>> They're probably just pulling numbers out the the nebulous IPC-2221 charts, that no one seems to understand or know of the origins. Apparently temperature is everything and the starting point for a specification, not an aside you throw into a calculator. The reason being the drastic difference in temperature expansion of Cu, at something like 5ppm, and epoxy resin, at something like 350ppm. The epoxy numbers are for T "near" Tg, the glass transition temperature of the material. Based on that bs the IPC publishes a formula I = K * dT^0.44 * (W*H)^0.725 with obvious notation. That particular result gets around anyone having to figure out a safe stress limit on the copper/ substrate bonding induced by expansion. I'm sure in addition to an outright separation there is the issue of cycling the material interface through repeated expansions. If your numbers for trace width are ridiculously big then there are the options of using heavier CU, the W*H part, and using a high Tg material
>PCB, the allowable dT part. There are plenty of high Tg PCB manufacturers out there and you should be consulting with them. "High TG PCB"
>>>>
>>>> https://www.us-tech.com/RelId/2687527/ISvars/default/Heavy_Copper_Design_Considerations_Part_1_Traces_and_Temperature.htm
>>> If you are pushing the limits of maximum temperature due to thermal
>>> expansion and/or the number of temperature cycles, I wonder if placing a
>>> number of small round holes in wide traces and planes would help? Not a
>>> hole through the fiberglass, just a hole through the copper much smaller
>>> than the width of a trace. That would allow resin to flow in and fill
>>> the hole during manufacture and should "pin" the trace to resist lateral
>>> movement and delamination. Hopefully the loss of electrical performance
>>> could be kept small for a substantial increase in the mechanical strength.
>>
>> I'm not seeing how that will help. When the epoxy starts growing, the whole side-to-side footprint under the trace starts growing whereas the copper wants to maintain its original width. If it gets out of hand either the copper will split or the bonding lets go or both. As long as that strain stays under what's called the yield limit (temperature dependent), the copper will stay intact and return to its original cold dimensions when the temperature declines. The resin manufacturer will know those details and should be able to recommend a maximum dT to achieve maximum product longevity.
>>
>>>
>>> --
>>> Regards,
>>> Carl
>
>I was making the assumption that the yield strength of the copper would
>be greater than the bonding strength of the copper to the substrate so
>that using the holes to increase the bonding strength of the copper to
>the substrate would increase the failure strength of the assembly. If
>they stay bound together then localized bending or curling could relieve
>some of the stress by spreading it out instead of keeping it localized
>to pop the copper off the substrate. May not make enough of a
>difference to matter but it seems a simple, cheap modification to at
>least try if JL is going to test a few boards to destruction :-).

Carl, this is 'cycling', not static stress.

RL

On Sunday, July 30, 2023 at 9:36:28 AM UTC-4, Anthony William Sloman wrote:
> On Sunday, July 30, 2023 at 12:10:26 AM UTC+10, Fred Bloggs wrote:
> > On Thursday, July 27, 2023 at 6:07:13 PM UTC-4, John Larkin wrote:
> > > On Thu, 27 Jul 2023 10:34:09 -0700, dpl...@coop.radagast.org (Dave Platt) wrote:
> > > >In article <8c05ci9uqpvr4cebl...@4ax.com>, John Larkin <x...@yy.com> wrote:
> <snip>
>
> > > I'll just experiment with a real board. Buying and learning the FEM
> > > software would be 50x as hard.
> > >
> > > I am disappointed how little that hard numbers are available. And the
> > > wild range of calculated results.
> >
> > The approach of trace fusing is ridiculous, your board will be destroyed long before then. You should be focusing on allowable dT, which will be way, way less than the 2,000oF melting temperature of Cu.
> The real problem is likely to be the glass transition temperature of the epoxy resin. The one time I had my nose rubbed in it, the mechanical engineers had used an epoxy with a glass transition temperature of 62C (which is pretty common) to position a pair of electrodes which were supposed to measure the conductivity of a a water-based wash liquid that got up to 85C. None of us were pleased when the electrodes started moving around at 62C.
>
> I found an epoxy resin with a glass transition temperature of 125C which saved the day.
>
> A glass-fibre-epoxy printed circuit board that got hotter than the glass transition temperature of its resin would probably start sagging, and stay permanently sagged when it cooled off.
>
> Getting the copper traces hot enough to melt copper isn't going to be what messes up your board.

TG of 175oC is readily available these days. Something like that should allow dT in the 40-50oC range, allowing for thinner traces, maybe 1/4, and amplify that with heavier copper to get even more current capacity.

>
> --
> Bill Sloman, Sydney

On Saturday, July 29, 2023 at 1:23:27 PM UTC-4, Carl wrote:
> On 7/29/23 12:38 PM, Fred Bloggs wrote:
> > On Saturday, July 29, 2023 at 12:09:07 PM UTC-4, Carl wrote:
> >> On 7/29/23 9:54 AM, Fred Bloggs wrote:
> >>
> >>> They're probably just pulling numbers out the the nebulous IPC-2221 charts, that no one seems to understand or know of the origins. Apparently temperature is everything and the starting point for a specification, not an aside you throw into a calculator. The reason being the drastic difference in temperature expansion of Cu, at something like 5ppm, and epoxy resin, at something like 350ppm. The epoxy numbers are for T "near" Tg, the glass transition temperature of the material. Based on that bs the IPC publishes a formula I = K * dT^0.44 * (W*H)^0.725 with obvious notation. That particular result gets around anyone having to figure out a safe stress limit on the copper/ substrate bonding induced by expansion. I'm sure in addition to an outright separation there is the issue of cycling the material interface through repeated expansions. If your numbers for trace width are ridiculously big then there are the options of using heavier CU, the W*H part, and using a high Tg material PCB, the allowable dT part. There are plenty of high Tg PCB manufacturers out there and you should be consulting with them. "High TG PCB"
> >>>
> >>> https://www.us-tech.com/RelId/2687527/ISvars/default/Heavy_Copper_Design_Considerations_Part_1_Traces_and_Temperature.htm
> >> If you are pushing the limits of maximum temperature due to thermal
> >> expansion and/or the number of temperature cycles, I wonder if placing a
> >> number of small round holes in wide traces and planes would help? Not a
> >> hole through the fiberglass, just a hole through the copper much smaller
> >> than the width of a trace. That would allow resin to flow in and fill
> >> the hole during manufacture and should "pin" the trace to resist lateral
> >> movement and delamination. Hopefully the loss of electrical performance
> >> could be kept small for a substantial increase in the mechanical strength.
> >
> > I'm not seeing how that will help. When the epoxy starts growing, the whole side-to-side footprint under the trace starts growing whereas the copper wants to maintain its original width. If it gets out of hand either the copper will split or the bonding lets go or both. As long as that strain stays under what's called the yield limit (temperature dependent), the copper will stay intact and return to its original cold dimensions when the temperature declines. The resin manufacturer will know those details and should be able to recommend a maximum dT to achieve maximum product longevity.
> >
> >>
> >> --
> >> Regards,
> >> Carl
> I was making the assumption that the yield strength of the copper would
> be greater than the bonding strength of the copper to the substrate so
> that using the holes to increase the bonding strength of the copper to
> the substrate would increase the failure strength of the assembly. If
> they stay bound together then localized bending or curling could relieve
> some of the stress by spreading it out instead of keeping it localized
> to pop the copper off the substrate. May not make enough of a
> difference to matter but it seems a simple, cheap modification to at
> least try if JL is going to test a few boards to destruction :-).

I'm not sure because the article didn't spell it out, but those expansion ppm's should be volumetric. So to compute deformation with temperature all they have to do is determine the volume increase and then apply it to their specific geometry, a flat plane usually, and determine how the boundaries swell.

>
> --
> Regards,
> Carl

On Saturday, July 29, 2023 at 6:45:52 PM UTC-4, Tabby wrote:
> On Saturday, 29 July 2023 at 18:16:44 UTC+1, John Larkin wrote:
> > On Sat, 29 Jul 2023 09:38:40 -0700 (PDT), Fred Bloggs
> > <bloggs.fred...@gmail.com> wrote:
> > >On Saturday, July 29, 2023 at 12:09:07?PM UTC-4, Carl wrote:
> > >> On 7/29/23 9:54 AM, Fred Bloggs wrote:
> > >>
> > >> > They're probably just pulling numbers out the the nebulous IPC-2221 charts, that no one seems to understand or know of the origins. Apparently temperature is everything and the starting point for a specification, not an aside you throw into a calculator. The reason being the drastic difference in temperature expansion of Cu, at something like 5ppm, and epoxy resin, at something like 350ppm. The epoxy numbers are for T "near" Tg, the glass transition temperature of the material. Based on that bs the IPC publishes a formula I = K * dT^0.44 * (W*H)^0.725 with obvious notation. That particular result gets around anyone having to figure out a safe stress limit on the copper/ substrate bonding induced by expansion. I'm sure in addition to an outright separation there is the issue of cycling the material interface through repeated expansions. If your numbers for trace width are ridiculously big then there are the options of using heavier CU, the W*H part, and using a high Tg material
> > >PCB, the allowable dT part. There are plenty of high Tg PCB manufacturers out there and you should be consulting with them. "High TG PCB"
> > >> >
> > >> > https://www.us-tech.com/RelId/2687527/ISvars/default/Heavy_Copper_Design_Considerations_Part_1_Traces_and_Temperature.htm
> > >> If you are pushing the limits of maximum temperature due to thermal
> > >> expansion and/or the number of temperature cycles, I wonder if placing a
> > >> number of small round holes in wide traces and planes would help? Not a
> > >> hole through the fiberglass, just a hole through the copper much smaller
> > >> than the width of a trace. That would allow resin to flow in and fill
> > >> the hole during manufacture and should "pin" the trace to resist lateral
> > >> movement and delamination. Hopefully the loss of electrical performance
> > >> could be kept small for a substantial increase in the mechanical strength.
> > >
> > >I'm not seeing how that will help. When the epoxy starts growing, the whole side-to-side footprint under the trace starts growing whereas the copper wants to maintain its original width. If it gets out of hand either the copper will split or the bonding lets go or both. As long as that strain stays under what's called the yield limit (temperature dependent), the copper will stay intact and return to its original cold dimensions when the temperature declines. The resin manufacturer will know those details and should be able to recommend a maximum dT to achieve maximum product longevity.
> > >
> > >>
> > >> --
> > >> Regards,
> > >> Carl
> > Mechanical stresses won't be an issue. Toasting the epoxy-glass will.
> >
> > I've never seen a board self-destruct from current-induced thermal
> > expansion. They make boats and bathtubs and Corvettes from
> > epoxy-glass.
> >
> > I have seen a few fused traces.
> I've seen successfully fused traces, typically where the overload was massive. I've seen many more where the result was a pile of conductive arcing carbon & junk. If you must use a trace as a fuse, I'd at least give it lots of clearance. And don't be surprised by a messy arcing shorting result.

I've seen those, usually as a result of a KAPOW lightning strike induced transient on the line. Trace is a gone with charred footprint on board where it used to be.

On one occasion I saw the aftermath of a line stepdown transformer failure. That would be a utility transformer stepping down from medium voltage to the 120VAC. Lots and lots of failed MOVs in lots of equipment. All that was left of most MOVs were the leads soldered to the board, the component itself was nowhere to be found.

On 7/30/23 8:46 AM, legg wrote:
> On Sat, 29 Jul 2023 13:23:19 -0400, Carl <carl.ijamesxx@yyverizon.net>
> wrote:
>
>> On 7/29/23 12:38 PM, Fred Bloggs wrote:
>>> On Saturday, July 29, 2023 at 12:09:07?PM UTC-4, Carl wrote:
>>>> On 7/29/23 9:54 AM, Fred Bloggs wrote:
>>>>
>>>>> They're probably just pulling numbers out the the nebulous IPC-2221 charts, that no one seems to understand or know of the origins. Apparently temperature is everything and the starting point for a specification, not an aside you throw into a calculator. The reason being the drastic difference in temperature expansion of Cu, at something like 5ppm, and epoxy resin, at something like 350ppm. The epoxy numbers are for T "near" Tg, the glass transition temperature of the material. Based on that bs the IPC publishes a formula I = K * dT^0.44 * (W*H)^0.725 with obvious notation. That particular result gets around anyone having to figure out a safe stress limit on the copper/ substrate bonding induced by expansion. I'm sure in addition to an outright separation there is the issue of cycling the material interface through repeated expansions. If your numbers for trace width are ridiculously big then there are the options of using heavier CU, the W*H part, and using a high Tg material
>> PCB, the allowable dT part. There are plenty of high Tg PCB manufacturers out there and you should be consulting with them. "High TG PCB"
>>>>>
>>>>> https://www.us-tech.com/RelId/2687527/ISvars/default/Heavy_Copper_Design_Considerations_Part_1_Traces_and_Temperature.htm
>>>> If you are pushing the limits of maximum temperature due to thermal
>>>> expansion and/or the number of temperature cycles, I wonder if placing a
>>>> number of small round holes in wide traces and planes would help? Not a
>>>> hole through the fiberglass, just a hole through the copper much smaller
>>>> than the width of a trace. That would allow resin to flow in and fill
>>>> the hole during manufacture and should "pin" the trace to resist lateral
>>>> movement and delamination. Hopefully the loss of electrical performance
>>>> could be kept small for a substantial increase in the mechanical strength.
>>>
>>> I'm not seeing how that will help. When the epoxy starts growing, the whole side-to-side footprint under the trace starts growing whereas the copper wants to maintain its original width. If it gets out of hand either the copper will split or the bonding lets go or both. As long as that strain stays under what's called the yield limit (temperature dependent), the copper will stay intact and return to its original cold dimensions when the temperature declines. The resin manufacturer will know those details and should be able to recommend a maximum dT to achieve maximum product longevity.
>>>
>>>>
>>>> --
>>>> Regards,
>>>> Carl
>>
>> I was making the assumption that the yield strength of the copper would
>> be greater than the bonding strength of the copper to the substrate so
>> that using the holes to increase the bonding strength of the copper to
>> the substrate would increase the failure strength of the assembly. If
>> they stay bound together then localized bending or curling could relieve
>> some of the stress by spreading it out instead of keeping it localized
>> to pop the copper off the substrate. May not make enough of a
>> difference to matter but it seems a simple, cheap modification to at
>> least try if JL is going to test a few boards to destruction :-).
>
> Carl, this is 'cycling', not static stress.
>
> RL
Yes, but a lot of materials fail after lots of cycles of stress that is
well below the ultimate tensile strength. Steel lasts "forever" so long
as you stay below the ultimate tensile, aluminum fails after "some
number" of cycles well below UTS. After some number of cycles the bond
between copper and substrate will begin to lessen, which eventually will
degrade the heat transfer, which will eventually make the trace run
hotter, etc. I was thinking more about the total number of use cycles
of the product since JL's application is a tester where the current will
be cycled frequently, not about prompt failure. I've seen heater
controller pcbs with traces carrying a few amps of 110VAC that ran cool
when new, then over a few years the fiberglass started to turn brown,
and eventually some charred and burnt, all while the current stayed
within spec until the final fire. Just thought this might be a way to
slow that progression.
--
Regards,
Carl