On Sat, 29 Jul 2023 07:10:21 -0700 (PDT), Fred Bloggs
<bloggs.fredbloggs.fred@gmail.com> wrote:

>On Thursday, July 27, 2023 at 6:07:13?PM UTC-4, John Larkin wrote:
>> On Thu, 27 Jul 2023 10:34:09 -0700, dpl...@coop.radagast.org (Dave
>> Platt) wrote:
>>
>> >In article <8c05ci9uqpvr4cebl...@4ax.com>,
>> >John Larkin <x...@yy.com> wrote:
>> >
>> >>This one says that for a 10 amp trace, the inner-layer width needs to
>> >>be 740 mils... 3/4 of an inch!
>> >>
>> >>https://www.4pcb.com/trace-width-calculator.html
>> >>
>> >>That's crazy. And they show inner layers needing to be wider than
>> >>microstrips. Doesn't epoxy-glass conduct heat better than air?
>> >
>> >Yes, it does (air's thermal conductivity is lousy) but that's not the
>> >right question. Relatively little heat leaves the board by conduction
>> >to air. Most of it leaves via convection (or forced-air).
>> >
>> >Equally importantly: the higher thermal conductivity of the epoxy-
>> >glass isn't magic. It still adds thermal resistance between the
>> >heat source and the outside of the board, in addition to the
>> >"surface to ambient" thermal resistance which both internal traces
>> >and microstrips have to deal with.
>> If you thermal image the surfaces of a board that has a hot trace
>> inside, the hot area of the board will be wider than the trace. For a
>> narrow trace, much wider. The epoxy spreads the heat and allows the
>> trace to contact a lot more air on both sides.
>> >
>> >>They don't account for heat conduction to inner-layer planes either.
>> >
>> >If we neglect the presence of inner-plane flooded layers, then of
>> >course the inner traces would need to be wider than the outer, for a
>> >given amount of heat dissipation and acceptable temperature rise. The
>> >thermal resistance to ambient for an inner layer is going to be higher
>> >than that of the outer layers.
>> A full-board ground plane, or better yet a ground plane and a couple
>> of power planes, will spread the heat over the entire board surface.
>>
>> An inner layer trace could dump heat through thin FR4 layers to
>> thermally conductive planes above and below.
>> >
>> >Every layer the heat has to go through on its way to ambient is going
>> >to add thermal resistance.
>> Unless the spreading effect wins. FR4 conducts heat about 12x better
>> than air.
>> > The thermal resistance to the two sides of
>> >the board will combine in the usual parallel-resistance formula. For
>> >a trace on the surface, the resulting resistance will be dominated by
>> >the direct-to-air resistance on that side, and so it'll be lower than
>> >a trace right in the middle.
>> >
>> >Now, to add in the "inner layer" effect accurately, you'd have to give
>> >an accurate model for the heatsinking ability of those inner planes.
>> >What is _their_ thermal resistance to ambient, on a given board? Is
>> >there a direct and efficient heat-path from the power and ground
>> >planes out to ambient (e.g. big fat power-supply connectors and heavy
>> >copper wire to some cold place) or are the power and ground planes
>> >thermally "trapped inside" the board and mostly just moving heat
>> >around inside the board?
>> >
>> >You also would need to consider whether you're trying to get a valid
>> >number for a board with just a few traces high-current traces, or for
>> >"they're all going to be like this". If it's just one or two traces
>> >(hotted up at any given time) you can probably treat your internal
>> >planes as something like near-infinite heat-sinks to ambient, and get
>> >away with a thinner trace. If you're designing a board which is going
>> >to be full of these hot traces operating simultaneously, then you
>> >can't make this assumption - the ability of the inner planes to
>> >conduct all of that heat out to ambient is likely to be limited and
>> >you'll have to limit your heat-generated-per-trace or the board as a
>> >whole will cook itself.
>> >
>> >I'd guess that the calculators are designed based on some conservative
>> >(near to worst-case) simplifying assumptions. "So, you want to fill
>> >your whole board with traces like this, and you can't count on your
>> >internal planes sinking a lot of heat out to ambient? Do it this way,
>> >keep your generated heat down to a minimum, and you can be reasonably
>> >confident that the board probably won't cook itself to death before
>> >the warranty expires."
>> >
>> >If you want a more accurate set of numbers for your own specific
>> >board design, you'll probably need to do some finite-element
>> >thermal modeling based on your actual board layout, and tune
>> >things manually based on your actual trace usage. If you've
>> >got 2-3 energized relays on the board at a time, you'll probably
>> >like the answers a lot better than if you're expecting to have
>> >dozens of relays pulling current most of the time.
>> >
>> >
>> >
>> >
>> I'll just experimant with a real board. Buying and learning the FEM
>> software would be 50x as hard.
>>
>> I am disappointed how little that hard numbers are available. And the
>> wild range of calculated results.
>
>The approach of trace fusing is ridiculous, your board will be destroyed long before then. You should be focusing on allowable dT, which will be way, way less than the 2,000oF melting temperature of Cu.

I have seen PCB traces used as last-resort fuses. It's not an
unreasonable concept, but I was diasppointed to not find any useful
references to the appropriate geometry and dimensions.

But polyfuses would be better, if I can fit 48 of them on my board and
somehow route the hundreds of fat traces.

https://www.dropbox.com/scl/fi/wqhbrcrp5ku2drfnjb3m1/P948_polyfuses_5.jpg?rlkey=7q7oddoj2cdgi7co7dndyjqd4&raw=1

Why solve stupid useless puzzles in the back of the New York Times,
when PCBs are more challenging?