Jay E. Morris <morrisj@epsilon3.comcon> wrote:
> On 11/28/2022 12:47 AM, Thomas Koenig wrote:
>>> There have been Windows implementations for MIPS, ARM, Alpha and PowerPC.
>> Vobis (a German computer discounter at the
>> time) actually offered an Alpha with Windows, the
>> "Highscreen Alpha 5000". You can see their catalog at
>> https://www.schmalenstroer.net/books/Alte%20Kataloge/Vobis%20Denkzettel%201997-07-24.pdf
>> (have to scroll down a bit).
>>
>> With its PALcode, the Alpha was designed with different operating
>> systems in mind.
>>
>
> There were at least a couple dozen Alphas that could run NT or 2000. At
> one orkspace I maintained three DS10s, two VMS and one NT.

Also OSF/1...we were a Unix shop we ran that on ours.

Robert
--
Robert K. Shull Email: rkshull at rosettacon dot com

On Mon, 28 Nov 2022 11:08:29 -0700, Jibini Kula Tumbili Kujisalimisha
<taustinca@gmail.com> wrote:

>Paul S Person <psperson@old.netcom.invalid> wrote in
>news:qfr9oh1ghvqo1husle7uiu7drko9pq2gao@4ax.com:
>
>> On Sun, 27 Nov 2022 18:30:23 GMT, Ninapenda Jibini
>> <taustinca@gmail.com> wrote:
>>
>>>scott@slp53.sl.home (Scott Lurndal) wrote in
>>>news:huNgL.314169$Mlk.253947@fx17.iad:
>>>
>>>> Paul S Person <psperson@old.netcom.invalid> writes:
>>>>>On Sat, 26 Nov 2022 17:26:44 GMT, scott@slp53.sl.home (Scott
>>>>>Lurndal) wrote:
>>>>>
>>>>>>Paul S Person <psperson@old.netcom.invalid> writes:
>>>>>>>On Thu, 24 Nov 2022 15:36:29 -0500, John W Kennedy
>>>>>>><john.w.kennedy@gmail.com> wrote:
>>>>>>>
>>>>>>>
>>>>>>>>>>
>>>>>>>>>> Badly written software - or simply badly /conceived/
>>>>>>>>>> software - can kill any CPU.
>>>>>>>>>
>>>>>>>>> That's /always/ the excuse when the big promises turn out
>>>>>>>>> to be, at best, overly optimistic.
>>>>>>>>>
>>>>>>>>> I seem to recall that the theory was that no such
>>>>>>>>> software could possibly exist with the new OSes.
>>>>>>>>
>>>>>>>>Huh? ARM isn’t an OS; it’s a RISC architecture.
>>>>>>>
>>>>>>>It was claimed that the associated OSes would never lose
>>>>>>>anything. IIRC.
>>>>>>
>>>>>>Claimed by whom?
>>>>>
>>>>>The people making the promises about RISC. IIRC.
>>>>>
>>>>>This was, what, 30 years ago? 25? Details fade.
>>>>
>>>> I've been in the hardware and OS side of the business for
>>>> longer than that, and worked on and OS for the early RISC
>>>> processor from Motrola, the 88100. I've never heard such a
>>>> claim about "OS never loosing anything"[*].
>>>>
>>>>
>>>>>It is the RISC proponents who were making these predictions.
>>>>
>>>> You'll need to find some citations to support your memory.
>>>>
>>>> The claims about RISC have always been around the simplicity
>>>> of the hardware providing a path to easier and less
>>>> expensive implementation.
>>>>
>>>I suspect that, as an industry insider, you've seen technical
>>>claims by technical people, and he's seen marketing claims by
>>>marketing "people".
>>>
>>>And you know how accurate marketing claims are.
>>
>> I think both points are quite possible.
>>
>> Although some of it may have come from articles in BYTE or DDJ.
>> So perhaps "enthusiasts" rather than "marketing".
>
>Entusiasts are simply parroting the marketing spiel.

I'm not sure that was the case. There were, and probably still are, a
/lot/ of people who really really hate segmented architectures and
Windows. The marketing campaign was much, much tamer.

BTW, has anyone else noticed this interesting progression:
1) A claim is reported that RISC processors will take over the world.
2) I point out that this same claim was made 25 (say) years ago, and
it didn't happen.
3) Others claim that modern "segmented" processors are really RISC
processors which mimic segmentation so the software will run.

Which, of course, leads to the question:

If RISC processors have /already/ taken over the world, why was the
new prediction made at all?

I suspect that, as always, we have long-since descended into semantic
mush.
--
"In this connexion, unquestionably the most significant
development was the disintegration, under Christian
influence, of classical conceptions of the family and
of family right."

Paul S Person <psperson@old.netcom.invalid> wrote in
news:80fcohdrjkbg26f4r6m5fsled7hknqka5n@4ax.com:

> On Mon, 28 Nov 2022 11:08:29 -0700, Jibini Kula Tumbili
> Kujisalimisha <taustinca@gmail.com> wrote:
>
>>Paul S Person <psperson@old.netcom.invalid> wrote in
>>news:qfr9oh1ghvqo1husle7uiu7drko9pq2gao@4ax.com:
>>
>>> On Sun, 27 Nov 2022 18:30:23 GMT, Ninapenda Jibini
>>> <taustinca@gmail.com> wrote:
>>>
>>>>scott@slp53.sl.home (Scott Lurndal) wrote in
>>>>news:huNgL.314169$Mlk.253947@fx17.iad:
>>>>
>>>>> Paul S Person <psperson@old.netcom.invalid> writes:
>>>>>>On Sat, 26 Nov 2022 17:26:44 GMT, scott@slp53.sl.home (Scott
>>>>>>Lurndal) wrote:
>>>>>>
>>>>>>>Paul S Person <psperson@old.netcom.invalid> writes:
>>>>>>>>On Thu, 24 Nov 2022 15:36:29 -0500, John W Kennedy
>>>>>>>><john.w.kennedy@gmail.com> wrote:
>>>>>>>>
>>>>>>>>
>>>>>>>>>>>
>>>>>>>>>>> Badly written software - or simply badly /conceived/
>>>>>>>>>>> software - can kill any CPU.
>>>>>>>>>>
>>>>>>>>>> That's /always/ the excuse when the big promises turn
>>>>>>>>>> out to be, at best, overly optimistic.
>>>>>>>>>>
>>>>>>>>>> I seem to recall that the theory was that no such
>>>>>>>>>> software could possibly exist with the new OSes.
>>>>>>>>>
>>>>>>>>>Huh? ARM isn�t an OS; it�s a RISC architecture.
>>>>>>>>
>>>>>>>>It was claimed that the associated OSes would never lose
>>>>>>>>anything. IIRC.
>>>>>>>
>>>>>>>Claimed by whom?
>>>>>>
>>>>>>The people making the promises about RISC. IIRC.
>>>>>>
>>>>>>This was, what, 30 years ago? 25? Details fade.
>>>>>
>>>>> I've been in the hardware and OS side of the business for
>>>>> longer than that, and worked on and OS for the early RISC
>>>>> processor from Motrola, the 88100. I've never heard such a
>>>>> claim about "OS never loosing anything"[*].
>>>>>
>>>>>
>>>>>>It is the RISC proponents who were making these predictions.
>>>>>
>>>>> You'll need to find some citations to support your memory.
>>>>>
>>>>> The claims about RISC have always been around the simplicity
>>>>> of the hardware providing a path to easier and less
>>>>> expensive implementation.
>>>>>
>>>>I suspect that, as an industry insider, you've seen technical
>>>>claims by technical people, and he's seen marketing claims by
>>>>marketing "people".
>>>>
>>>>And you know how accurate marketing claims are.
>>>
>>> I think both points are quite possible.
>>>
>>> Although some of it may have come from articles in BYTE or
>>> DDJ. So perhaps "enthusiasts" rather than "marketing".
>>
>>Entusiasts are simply parroting the marketing spiel.
>
> I'm not sure that was the case. There were, and probably still
> are, a /lot/ of people who really really hate segmented
> architectures and Windows. The marketing campaign was much, much
> tamer.
>
> BTW, has anyone else noticed this interesting progression:
> 1) A claim is reported that RISC processors will take over the
> world. 2) I point out that this same claim was made 25 (say)
> years ago, and it didn't happen.
> 3) Others claim that modern "segmented" processors are really
> RISC processors which mimic segmentation so the software will
> run.
>
> Which, of course, leads to the question:
>
> If RISC processors have /already/ taken over the world, why was
> the new prediction made at all?
>
> I suspect that, as always, we have long-since descended into
> semantic mush.

Semantic mush is the building block of all marketing hype. They're
glued together with more semantic mush as mortar, plastered over
with more semantic much, and deocrated with pieces of art made out
of semantic mush (hung with picture hangers made out of semantic
mush).

It's turtles all the way down.

--
Terry Austin

"Terry Austin: like the polio vaccine, only with more asshole."
-- David Bilek

Jesus forgives sinners, not criminals.

Paul S Person <psperson@old.netcom.invalid> writes:
>On Mon, 28 Nov 2022 11:08:29 -0700, Jibini Kula Tumbili Kujisalimisha
><taustinca@gmail.com> wrote:
>
>
>BTW, has anyone else noticed this interesting progression:
>1) A claim is reported that RISC processors will take over the world.

Reported by whom? An anonymous poster in a Usenet newsgroup?

>2) I point out that this same claim was made 25 (say) years ago, and
>it didn't happen.

Again, cite please. Not a cite to your claim, but a period cite.

>3) Others claim that modern "segmented" processors are really RISC
>processors which mimic segmentation so the software will run.

There have been no "modern segmented" processors since the 286.

There hasn't been any segmented software running, even under windows
since the 286 (except in compatability mode, e.g. v86, which was
not implemented in the 64-bit x86 processors and has been obsolete
for over two decades).

The internal structure of a modern intel or amd processor quite
strikingly resembles the internal structure of a modern RISC
processor. That doesn't make it a RISC processor, it just notes
that the internal implementation (where the macro instructions
are fissioned into micro-operations that are scheduled to the
relevent units - arithmetic, load/store, simd - for execution)
has the same implementation and performance qualities of
RISC architectures.

>
>Which, of course, leads to the question:
>
>If RISC processors have /already/ taken over the world, why was the
>new prediction made at all?

ARM has taken over the world - they've shipped over 200 billion
processors, and there are server-grade ARM processors already
in production in various cloud datacenters from various
vendors.

Intel's share price (and history over the last two decades)
should tell you a great deal about the RISC impact on their
business. Hint, the stock price today is a bit less per
share than it was in 2000.

>
>I suspect that, as always, we have long-since descended into semantic
>mush.

I suspect that you are reaching to make a pointless argument.

scott@slp53.sl.home (Scott Lurndal) wrote in
news:3IrhL.7$Use.0@fx15.iad:

> Paul S Person <psperson@old.netcom.invalid> writes:

>>I suspect that, as always, we have long-since descended into
>>semantic mush.
>
> I suspect that you are reaching to make a pointless argument.
>
Isn't that the whole purpose of Usenet?

--
Terry Austin

"Terry Austin: like the polio vaccine, only with more asshole."
-- David Bilek

Jesus forgives sinners, not criminals.

On Tue, 29 Nov 2022 09:58:11 -0700, Jibini Kula Tumbili Kujisalimisha
<taustinca@gmail.com> wrote:

>scott@slp53.sl.home (Scott Lurndal) wrote in
>news:3IrhL.7$Use.0@fx15.iad:
>
>> Paul S Person <psperson@old.netcom.invalid> writes:
>
>>>I suspect that, as always, we have long-since descended into
>>>semantic mush.
>>
>> I suspect that you are reaching to make a pointless argument.
>>
>Isn't that the whole purpose of Usenet?

I don't know that that is the /whole/ purpose of Usenet -- but it is
certainly a common use and a lot of fun.
\ --
"In this connexion, unquestionably the most significant
development was the disintegration, under Christian
influence, of classical conceptions of the family and
of family right."

Paul S Person <psperson@old.netcom.invalid> wrote in
news:g83foh58frlkkblvvssiv0gtovmiljro81@4ax.com:

> On Tue, 29 Nov 2022 09:58:11 -0700, Jibini Kula Tumbili
> Kujisalimisha <taustinca@gmail.com> wrote:
>
>>scott@slp53.sl.home (Scott Lurndal) wrote in
>>news:3IrhL.7$Use.0@fx15.iad:
>>
>>> Paul S Person <psperson@old.netcom.invalid> writes:
>>
>>>>I suspect that, as always, we have long-since descended into
>>>>semantic mush.
>>>
>>> I suspect that you are reaching to make a pointless argument.
>>>
>>Isn't that the whole purpose of Usenet?
>
> I don't know that that is the /whole/ purpose of Usenet -- but
> it is certainly a common use and a lot of fun.
> \

On the other hand . . .

https://www.youtube.com/watch?v=LTJvdGcb7Fs

(But technically speaking, Usenet is not the internet.)

--
Terry Austin

"Terry Austin: like the polio vaccine, only with more asshole."
-- David Bilek

Jesus forgives sinners, not criminals.

On 11/29/22 12:10 PM, Paul S Person wrote:
> On Mon, 28 Nov 2022 11:08:29 -0700, Jibini Kula Tumbili Kujisalimisha
> <taustinca@gmail.com> wrote:
>
>> Paul S Person <psperson@old.netcom.invalid> wrote in
>> news:qfr9oh1ghvqo1husle7uiu7drko9pq2gao@4ax.com:
>>
>>> On Sun, 27 Nov 2022 18:30:23 GMT, Ninapenda Jibini
>>> <taustinca@gmail.com> wrote:
>>>
>>>> scott@slp53.sl.home (Scott Lurndal) wrote in
>>>> news:huNgL.314169$Mlk.253947@fx17.iad:
>>>>
>>>>> Paul S Person <psperson@old.netcom.invalid> writes:
>>>>>> On Sat, 26 Nov 2022 17:26:44 GMT, scott@slp53.sl.home (Scott
>>>>>> Lurndal) wrote:
>>>>>>
>>>>>>> Paul S Person <psperson@old.netcom.invalid> writes:
>>>>>>>> On Thu, 24 Nov 2022 15:36:29 -0500, John W Kennedy
>>>>>>>> <john.w.kennedy@gmail.com> wrote:
>>>>>>>>
>>>>>>>>
>>>>>>>>>>>
>>>>>>>>>>> Badly written software - or simply badly /conceived/
>>>>>>>>>>> software - can kill any CPU.
>>>>>>>>>>
>>>>>>>>>> That's /always/ the excuse when the big promises turn out
>>>>>>>>>> to be, at best, overly optimistic.
>>>>>>>>>>
>>>>>>>>>> I seem to recall that the theory was that no such
>>>>>>>>>> software could possibly exist with the new OSes.
>>>>>>>>>
>>>>>>>>> Huh? ARM isn’t an OS; it’s a RISC architecture.
>>>>>>>>
>>>>>>>> It was claimed that the associated OSes would never lose
>>>>>>>> anything. IIRC.
>>>>>>>
>>>>>>> Claimed by whom?
>>>>>>
>>>>>> The people making the promises about RISC. IIRC.
>>>>>>
>>>>>> This was, what, 30 years ago? 25? Details fade.
>>>>>
>>>>> I've been in the hardware and OS side of the business for
>>>>> longer than that, and worked on and OS for the early RISC
>>>>> processor from Motrola, the 88100. I've never heard such a
>>>>> claim about "OS never loosing anything"[*].
>>>>>
>>>>>
>>>>>> It is the RISC proponents who were making these predictions.
>>>>>
>>>>> You'll need to find some citations to support your memory.
>>>>>
>>>>> The claims about RISC have always been around the simplicity
>>>>> of the hardware providing a path to easier and less
>>>>> expensive implementation.
>>>>>
>>>> I suspect that, as an industry insider, you've seen technical
>>>> claims by technical people, and he's seen marketing claims by
>>>> marketing "people".
>>>>
>>>> And you know how accurate marketing claims are.
>>>
>>> I think both points are quite possible.
>>>
>>> Although some of it may have come from articles in BYTE or DDJ.
>>> So perhaps "enthusiasts" rather than "marketing".
>>
>> Entusiasts are simply parroting the marketing spiel.
>
> I'm not sure that was the case. There were, and probably still are, a
> /lot/ of people who really really hate segmented architectures and
> Windows. The marketing campaign was much, much tamer.
>
> BTW, has anyone else noticed this interesting progression:
> 1) A claim is reported that RISC processors will take over the world.

Apart from legacy architectures dating back to the 60s or 70s, haven’t
they? And even the current implementations of z/Architecture are
implemented mostly as RISC, with a minority of opcodes invisibly
implemented in software using the hardware opcodes (a paradigm that
actually goes back to the S/360-44).

> 2) I point out that this same claim was made 25 (say) years ago, and
> it didn't happen.
> 3) Others claim that modern "segmented" processors are really RISC
> processors which mimic segmentation so the software will run.
>
> Which, of course, leads to the question:
>
> If RISC processors have /already/ taken over the world, why was the
> new prediction made at all?
>
> I suspect that, as always, we have long-since descended into semantic
> mush.

--
John W. Kennedy
Algernon Burbage, Lord Roderick, Father Martin, Bishop Baldwin,
King Pellinore, Captain Bailey, Merlin -- A Kingdom for a Stage!

John W Kennedy <john.w.kennedy@gmail.com> schrieb:
> On 11/29/22 12:10 PM, Paul S Person wrote:
>> On Mon, 28 Nov 2022 11:08:29 -0700, Jibini Kula Tumbili Kujisalimisha
>> <taustinca@gmail.com> wrote:
>>
>>> Paul S Person <psperson@old.netcom.invalid> wrote in
>>> news:qfr9oh1ghvqo1husle7uiu7drko9pq2gao@4ax.com:
>>>
>>>> On Sun, 27 Nov 2022 18:30:23 GMT, Ninapenda Jibini
>>>> <taustinca@gmail.com> wrote:
>>>>
>>>>> scott@slp53.sl.home (Scott Lurndal) wrote in
>>>>> news:huNgL.314169$Mlk.253947@fx17.iad:
>>>>>
>>>>>> Paul S Person <psperson@old.netcom.invalid> writes:
>>>>>>> On Sat, 26 Nov 2022 17:26:44 GMT, scott@slp53.sl.home (Scott
>>>>>>> Lurndal) wrote:
>>>>>>>
>>>>>>>> Paul S Person <psperson@old.netcom.invalid> writes:
>>>>>>>>> On Thu, 24 Nov 2022 15:36:29 -0500, John W Kennedy
>>>>>>>>> <john.w.kennedy@gmail.com> wrote:
>>>>>>>>>
>>>>>>>>>
>>>>>>>>>>>>
>>>>>>>>>>>> Badly written software - or simply badly /conceived/
>>>>>>>>>>>> software - can kill any CPU.
>>>>>>>>>>>
>>>>>>>>>>> That's /always/ the excuse when the big promises turn out
>>>>>>>>>>> to be, at best, overly optimistic.
>>>>>>>>>>>
>>>>>>>>>>> I seem to recall that the theory was that no such
>>>>>>>>>>> software could possibly exist with the new OSes.
>>>>>>>>>>
>>>>>>>>>> Huh? ARM isn’t an OS; it’s a RISC architecture.
>>>>>>>>>
>>>>>>>>> It was claimed that the associated OSes would never lose
>>>>>>>>> anything. IIRC.
>>>>>>>>
>>>>>>>> Claimed by whom?
>>>>>>>
>>>>>>> The people making the promises about RISC. IIRC.
>>>>>>>
>>>>>>> This was, what, 30 years ago? 25? Details fade.
>>>>>>
>>>>>> I've been in the hardware and OS side of the business for
>>>>>> longer than that, and worked on and OS for the early RISC
>>>>>> processor from Motrola, the 88100. I've never heard such a
>>>>>> claim about "OS never loosing anything"[*].
>>>>>>
>>>>>>
>>>>>>> It is the RISC proponents who were making these predictions.
>>>>>>
>>>>>> You'll need to find some citations to support your memory.
>>>>>>
>>>>>> The claims about RISC have always been around the simplicity
>>>>>> of the hardware providing a path to easier and less
>>>>>> expensive implementation.
>>>>>>
>>>>> I suspect that, as an industry insider, you've seen technical
>>>>> claims by technical people, and he's seen marketing claims by
>>>>> marketing "people".
>>>>>
>>>>> And you know how accurate marketing claims are.
>>>>
>>>> I think both points are quite possible.
>>>>
>>>> Although some of it may have come from articles in BYTE or DDJ.
>>>> So perhaps "enthusiasts" rather than "marketing".
>>>
>>> Entusiasts are simply parroting the marketing spiel.
>>
>> I'm not sure that was the case. There were, and probably still are, a
>> /lot/ of people who really really hate segmented architectures and
>> Windows. The marketing campaign was much, much tamer.
>>
>> BTW, has anyone else noticed this interesting progression:
>> 1) A claim is reported that RISC processors will take over the world.
>
> Apart from legacy architectures dating back to the 60s or 70s, haven’t
> they?

Well, yes and no - it is very much a matter of debate.

Old systems (like almost all versions of the /360, the VAX, the
Motorola 6800 or the DG Eclipse/MV of "The Soul of a New Machine"
fame ) used static microcode, where each instruction was split into
one or several microcode instructions, which were then executed.

The original RISC designs were, in a way, machines which exposed
the microcode directly to the user. At least the 801 was indeed
used as such, to run a /370 (I believe). They also used pipeplining
on their instructions to gain performance. They also (usually) had
one cycle per instruction, later versions had superscalar execution,
out-of-order execution and whatnot.

Today's CISC designs like the different AMD64 versions out there
first translate their CICS instructions into micro-ops (microcode,
if you will), which they then pipeline, schedule out-of-order
and whatnot.

A relatively pure RISC design like the POWER still has many
instructions as a single micro-instructions, others are cracked
into two. I believe RISC-V is designed so that it is a relatively
pure RISC, and each instruction is designed so it more or
less can be implemented directly. Of course, they advertise
for instruction fusion for things they left out.

So... has RISC taken over the world? You could argue as well that
microcode (not static, but instructions that can be scheduled)
rules supreme in x86-world. This is slightly at variance with
the definition of microcode as it is used now (which is static
RAM the same sort of micro-ops that the main engine uses).

> And even the current implementations of z/Architecture are
> implemented mostly as RISC, with a minority of opcodes invisibly
> implemented in software using the hardware opcodes (a paradigm that
> actually goes back to the S/360-44).

That is _really_ hard to define. IIRC, the hardware runs a superset
of a subset of the instructions that the programmer sees, and they
use millicode (executing one machine instructions via several
other machine instructions of the same format, but with some additional
ones available which the programmer cannot use).

Backwards compatibility to the mid-1960s comes at a price...

On 12/1/2022 11:33 AM, Thomas Koenig wrote:
> John W Kennedy <john.w.kennedy@gmail.com> schrieb:
>> On 11/29/22 12:10 PM, Paul S Person wrote:
>>> On Mon, 28 Nov 2022 11:08:29 -0700, Jibini Kula Tumbili Kujisalimisha
>>> <taustinca@gmail.com> wrote:
>>>
>>>> Paul S Person <psperson@old.netcom.invalid> wrote in
>>>> news:qfr9oh1ghvqo1husle7uiu7drko9pq2gao@4ax.com:
>>>>
>>>>> On Sun, 27 Nov 2022 18:30:23 GMT, Ninapenda Jibini
>>>>> <taustinca@gmail.com> wrote:
>>>>>
>>>>>> scott@slp53.sl.home (Scott Lurndal) wrote in
>>>>>> news:huNgL.314169$Mlk.253947@fx17.iad:
>>>>>>
>>>>>>> Paul S Person <psperson@old.netcom.invalid> writes:
>>>>>>>> On Sat, 26 Nov 2022 17:26:44 GMT, scott@slp53.sl.home (Scott
>>>>>>>> Lurndal) wrote:
>>>>>>>>
>>>>>>>>> Paul S Person <psperson@old.netcom.invalid> writes:
>>>>>>>>>> On Thu, 24 Nov 2022 15:36:29 -0500, John W Kennedy
>>>>>>>>>> <john.w.kennedy@gmail.com> wrote:
>>>>>>>>>>
>>>>>>>>>>
>>>>>>>>>>>>>
>>>>>>>>>>>>> Badly written software - or simply badly /conceived/
>>>>>>>>>>>>> software - can kill any CPU.
>>>>>>>>>>>>
>>>>>>>>>>>> That's /always/ the excuse when the big promises turn out
>>>>>>>>>>>> to be, at best, overly optimistic.
>>>>>>>>>>>>
>>>>>>>>>>>> I seem to recall that the theory was that no such
>>>>>>>>>>>> software could possibly exist with the new OSes.
>>>>>>>>>>>
>>>>>>>>>>> Huh? ARM isn’t an OS; it’s a RISC architecture.
>>>>>>>>>>
>>>>>>>>>> It was claimed that the associated OSes would never lose
>>>>>>>>>> anything. IIRC.
>>>>>>>>>
>>>>>>>>> Claimed by whom?
>>>>>>>>
>>>>>>>> The people making the promises about RISC. IIRC.
>>>>>>>>
>>>>>>>> This was, what, 30 years ago? 25? Details fade.
>>>>>>>
>>>>>>> I've been in the hardware and OS side of the business for
>>>>>>> longer than that, and worked on and OS for the early RISC
>>>>>>> processor from Motrola, the 88100. I've never heard such a
>>>>>>> claim about "OS never loosing anything"[*].
>>>>>>>
>>>>>>>
>>>>>>>> It is the RISC proponents who were making these predictions.
>>>>>>>
>>>>>>> You'll need to find some citations to support your memory.
>>>>>>>
>>>>>>> The claims about RISC have always been around the simplicity
>>>>>>> of the hardware providing a path to easier and less
>>>>>>> expensive implementation.
>>>>>>>
>>>>>> I suspect that, as an industry insider, you've seen technical
>>>>>> claims by technical people, and he's seen marketing claims by
>>>>>> marketing "people".
>>>>>>
>>>>>> And you know how accurate marketing claims are.
>>>>>
>>>>> I think both points are quite possible.
>>>>>
>>>>> Although some of it may have come from articles in BYTE or DDJ.
>>>>> So perhaps "enthusiasts" rather than "marketing".
>>>>
>>>> Entusiasts are simply parroting the marketing spiel.
>>>
>>> I'm not sure that was the case. There were, and probably still are, a
>>> /lot/ of people who really really hate segmented architectures and
>>> Windows. The marketing campaign was much, much tamer.
>>>
>>> BTW, has anyone else noticed this interesting progression:
>>> 1) A claim is reported that RISC processors will take over the world.
>>
>> Apart from legacy architectures dating back to the 60s or 70s, haven’t
>> they?
>
> Well, yes and no - it is very much a matter of debate.
>
> Old systems (like almost all versions of the /360, the VAX, the
> Motorola 6800 or the DG Eclipse/MV of "The Soul of a New Machine"
> fame ) used static microcode, where each instruction was split into
> one or several microcode instructions, which were then executed.
>
> The original RISC designs were, in a way, machines which exposed
> the microcode directly to the user. At least the 801 was indeed
> used as such, to run a /370 (I believe). They also used pipeplining
> on their instructions to gain performance. They also (usually) had
> one cycle per instruction, later versions had superscalar execution,
> out-of-order execution and whatnot.
>
> Today's CISC designs like the different AMD64 versions out there
> first translate their CICS instructions into micro-ops (microcode,
> if you will), which they then pipeline, schedule out-of-order
> and whatnot.
>
> A relatively pure RISC design like the POWER still has many
> instructions as a single micro-instructions, others are cracked
> into two. I believe RISC-V is designed so that it is a relatively
> pure RISC, and each instruction is designed so it more or
> less can be implemented directly. Of course, they advertise
> for instruction fusion for things they left out.
>
> So... has RISC taken over the world? You could argue as well that
> microcode (not static, but instructions that can be scheduled)
> rules supreme in x86-world. This is slightly at variance with
> the definition of microcode as it is used now (which is static
> RAM the same sort of micro-ops that the main engine uses).
>
>> And even the current implementations of z/Architecture are
>> implemented mostly as RISC, with a minority of opcodes invisibly
>> implemented in software using the hardware opcodes (a paradigm that
>> actually goes back to the S/360-44).
>
> That is _really_ hard to define. IIRC, the hardware runs a superset
> of a subset of the instructions that the programmer sees, and they
> use millicode (executing one machine instructions via several
> other machine instructions of the same format, but with some additional
> ones available which the programmer cannot use).
>
> Backwards compatibility to the mid-1960s comes at a price...

But American Expresses old software written in assembly and Cobol still
runs on IBM mainframes ...

Lynn

On 12/1/22 12:33 PM, Thomas Koenig wrote:
> John W Kennedy <john.w.kennedy@gmail.com> schrieb:
>> On 11/29/22 12:10 PM, Paul S Person wrote:
>>> On Mon, 28 Nov 2022 11:08:29 -0700, Jibini Kula Tumbili Kujisalimisha
>>> <taustinca@gmail.com> wrote:
>>>
>>>> Paul S Person <psperson@old.netcom.invalid> wrote in
>>>> news:qfr9oh1ghvqo1husle7uiu7drko9pq2gao@4ax.com:
>>>>
>>>>> On Sun, 27 Nov 2022 18:30:23 GMT, Ninapenda Jibini
>>>>> <taustinca@gmail.com> wrote:
>>>>>
>>>>>> scott@slp53.sl.home (Scott Lurndal) wrote in
>>>>>> news:huNgL.314169$Mlk.253947@fx17.iad:
>>>>>>
>>>>>>> Paul S Person <psperson@old.netcom.invalid> writes:
>>>>>>>> On Sat, 26 Nov 2022 17:26:44 GMT, scott@slp53.sl.home (Scott
>>>>>>>> Lurndal) wrote:
>>>>>>>>
>>>>>>>>> Paul S Person <psperson@old.netcom.invalid> writes:
>>>>>>>>>> On Thu, 24 Nov 2022 15:36:29 -0500, John W Kennedy
>>>>>>>>>> <john.w.kennedy@gmail.com> wrote:
>>>>>>>>>>
>>>>>>>>>>
>>>>>>>>>>>>>
>>>>>>>>>>>>> Badly written software - or simply badly /conceived/
>>>>>>>>>>>>> software - can kill any CPU.
>>>>>>>>>>>>
>>>>>>>>>>>> That's /always/ the excuse when the big promises turn out
>>>>>>>>>>>> to be, at best, overly optimistic.
>>>>>>>>>>>>
>>>>>>>>>>>> I seem to recall that the theory was that no such
>>>>>>>>>>>> software could possibly exist with the new OSes.
>>>>>>>>>>>
>>>>>>>>>>> Huh? ARM isn’t an OS; it’s a RISC architecture.
>>>>>>>>>>
>>>>>>>>>> It was claimed that the associated OSes would never lose
>>>>>>>>>> anything. IIRC.
>>>>>>>>>
>>>>>>>>> Claimed by whom?
>>>>>>>>
>>>>>>>> The people making the promises about RISC. IIRC.
>>>>>>>>
>>>>>>>> This was, what, 30 years ago? 25? Details fade.
>>>>>>>
>>>>>>> I've been in the hardware and OS side of the business for
>>>>>>> longer than that, and worked on and OS for the early RISC
>>>>>>> processor from Motrola, the 88100. I've never heard such a
>>>>>>> claim about "OS never loosing anything"[*].
>>>>>>>
>>>>>>>
>>>>>>>> It is the RISC proponents who were making these predictions.
>>>>>>>
>>>>>>> You'll need to find some citations to support your memory.
>>>>>>>
>>>>>>> The claims about RISC have always been around the simplicity
>>>>>>> of the hardware providing a path to easier and less
>>>>>>> expensive implementation.
>>>>>>>
>>>>>> I suspect that, as an industry insider, you've seen technical
>>>>>> claims by technical people, and he's seen marketing claims by
>>>>>> marketing "people".
>>>>>>
>>>>>> And you know how accurate marketing claims are.
>>>>>
>>>>> I think both points are quite possible.
>>>>>
>>>>> Although some of it may have come from articles in BYTE or DDJ.
>>>>> So perhaps "enthusiasts" rather than "marketing".
>>>>
>>>> Entusiasts are simply parroting the marketing spiel.
>>>
>>> I'm not sure that was the case. There were, and probably still are, a
>>> /lot/ of people who really really hate segmented architectures and
>>> Windows. The marketing campaign was much, much tamer.
>>>
>>> BTW, has anyone else noticed this interesting progression:
>>> 1) A claim is reported that RISC processors will take over the world.
>>
>> Apart from legacy architectures dating back to the 60s or 70s, haven’t
>> they?
>
> Well, yes and no - it is very much a matter of debate.
>
> Old systems (like almost all versions of the /360, the VAX, the
> Motorola 6800 or the DG Eclipse/MV of "The Soul of a New Machine"
> fame ) used static microcode, where each instruction was split into
> one or several microcode instructions, which were then executed.
>
> The original RISC designs were, in a way, machines which exposed
> the microcode directly to the user. At least the 801 was indeed
> used as such, to run a /370 (I believe).

The IBM JRD article compared the performance of the 801 to—a 165, I
think—one of the almost-an-85 models at any rate—but they talk about it
as a target for production programs written in a PL/I derivative. (They
were, by the way, rather astonished that they could breadboard a machine
that could beat a water-cooled monster.)

> They also used pipeplining
> on their instructions to gain performance. They also (usually) had
> one cycle per instruction, later versions had superscalar execution,
> out-of-order execution and whatnot.
>
> Today's CISC designs like the different AMD64 versions out there
> first translate their CICS instructions into micro-ops (microcode,
> if you will), which they then pipeline, schedule out-of-order
> and whatnot.
>
> A relatively pure RISC design like the POWER still has many
> instructions as a single micro-instructions, others are cracked
> into two. I believe RISC-V is designed so that it is a relatively
> pure RISC, and each instruction is designed so it more or
> less can be implemented directly. Of course, they advertise
> for instruction fusion for things they left out.
>
> So... has RISC taken over the world? You could argue as well that
> microcode (not static, but instructions that can be scheduled)
> rules supreme in x86-world. This is slightly at variance with
> the definition of microcode as it is used now (which is static
> RAM the same sort of micro-ops that the main engine uses).
>
>> And even the current implementations of z/Architecture are
>> implemented mostly as RISC, with a minority of opcodes invisibly
>> implemented in software using the hardware opcodes (a paradigm that
>> actually goes back to the S/360-44).
>
> That is _really_ hard to define. IIRC, the hardware runs a superset
> of a subset of the instructions that the programmer sees, and they
> use millicode (executing one machine instructions via several
> other machine instructions of the same format, but with some additional
> ones available which the programmer cannot use).
>
> Backwards compatibility to the mid-1960s comes at a price...

--
John W. Kennedy
Algernon Burbage, Lord Roderick, Father Martin, Bishop Baldwin,
King Pellinore, Captain Bailey, Merlin -- A Kingdom for a Stage!

In article <i8r9oh5313imsoa485uf7q87gp0ajarc14@4ax.com>,
Paul S Person <psperson@old.netcom.invalid> wrote:
>n Sun, 27 Nov 2022 21:35:09 GMT, djheydt@kithrup.com (Dorothy J Heydt)
>wrote:
>
>>In article <tlhr3e$3nihq$2@newsreader4.netcologne.de>,
>>Thomas Koenig <tkoenig@netcologne.de> wrote:
>>>An iPad has 3GB RAM these days, it is astonishing that serious
>>>business work can be done in a 2GB address space. But I suspect
>>>that many applications come from earlier times, when 2GB was
>>>luxury undreamt of.
>>
>>(Hal Heydt)
>>Raspberry Pi 4 Model B comes with up to 8GB. I run the DunDraCon
>>con reg on a pair (replicated database) of 4GB models. I used to
>>run it on 1GB SBCs. The shift was because the Pi4B finally got
>>fast enough I/O to suit me. Con reg kind of rattles around loose
>>with that much RAM. I suspect that MariaDB just sucks the entire
>>database into memory.
>
>My HP Envy has 12GB (IIRC, the HP Pavilion has 8GB).

(Hal Heydt)
Ah...but do either of those machines sell for $55? (Ganted,
that's without PSU, keyboard, mouse/tracball, mass storage
device, cables, or monitor. But with a KVM switch, some of that
can be shared. Since I'm using 120GB SSDs for mass storage, the
*total* outlay for each Pi4B-4 is right about $100 since I
already had some of the required devices on hand.)

djheydt@kithrup.com (Dorothy J Heydt) wrote in
news:rMC1IG.23q6@kithrup.com:

> In article <i8r9oh5313imsoa485uf7q87gp0ajarc14@4ax.com>,
> Paul S Person <psperson@old.netcom.invalid> wrote:
>>n Sun, 27 Nov 2022 21:35:09 GMT, djheydt@kithrup.com (Dorothy J
>>Heydt) wrote:
>>
>>>In article <tlhr3e$3nihq$2@newsreader4.netcologne.de>,
>>>Thomas Koenig <tkoenig@netcologne.de> wrote:
>>>>An iPad has 3GB RAM these days, it is astonishing that serious
>>>>business work can be done in a 2GB address space. But I
>>>>suspect that many applications come from earlier times, when
>>>>2GB was luxury undreamt of.
>>>
>>>(Hal Heydt)
>>>Raspberry Pi 4 Model B comes with up to 8GB. I run the
>>>DunDraCon con reg on a pair (replicated database) of 4GB
>>>models. I used to run it on 1GB SBCs. The shift was because
>>>the Pi4B finally got fast enough I/O to suit me. Con reg kind
>>>of rattles around loose with that much RAM. I suspect that
>>>MariaDB just sucks the entire database into memory.
>>
>>My HP Envy has 12GB (IIRC, the HP Pavilion has 8GB).
>
> (Hal Heydt)
> Ah...but do either of those machines sell for $55? (Ganted,
> that's without PSU, keyboard, mouse/tracball, mass storage
> device, cables, or monitor. But with a KVM switch, some of that
> can be shared. Since I'm using 120GB SSDs for mass storage, the
> *total* outlay for each Pi4B-4 is right about $100 since I
> already had some of the required devices on hand.)
>
Complete kits start under $200, and prices in the last couple of
years have been *outrageiously* high. They'll come back down
eventually, to probably 2/3 of that or less.

--
Terry Austin

Proof that Alan Baker is a liar and a fool, and even stupider than
Lynn:
https://www.cbp.gov/newsroom/stats/sw-border-migration

"Terry Austin: like the polio vaccine, only with more asshole."
-- David Bilek

Jesus forgives sinners, not criminals.

In article <80fcohdrjkbg26f4r6m5fsled7hknqka5n@4ax.com>,
Paul S Person <psperson@old.netcom.invalid> wrote:
>On Mon, 28 Nov 2022 11:08:29 -0700, Jibini Kula Tumbili Kujisalimisha
><taustinca@gmail.com> wrote:
>
>>Paul S Person <psperson@old.netcom.invalid> wrote in
>>news:qfr9oh1ghvqo1husle7uiu7drko9pq2gao@4ax.com:
>>
>>> On Sun, 27 Nov 2022 18:30:23 GMT, Ninapenda Jibini
>>> <taustinca@gmail.com> wrote:
>>>
>>>>scott@slp53.sl.home (Scott Lurndal) wrote in
>>>>news:huNgL.314169$Mlk.253947@fx17.iad:
>>>>
>>>>> Paul S Person <psperson@old.netcom.invalid> writes:
>>>>>>On Sat, 26 Nov 2022 17:26:44 GMT, scott@slp53.sl.home (Scott
>>>>>>Lurndal) wrote:
>>>>>>
>>>>>>>Paul S Person <psperson@old.netcom.invalid> writes:
>>>>>>>>On Thu, 24 Nov 2022 15:36:29 -0500, John W Kennedy
>>>>>>>><john.w.kennedy@gmail.com> wrote:
>>>>>>>>
>>>>>>>>
>>>>>>>>>>>
>>>>>>>>>>> Badly written software - or simply badly /conceived/
>>>>>>>>>>> software - can kill any CPU.
>>>>>>>>>>
>>>>>>>>>> That's /always/ the excuse when the big promises turn out
>>>>>>>>>> to be, at best, overly optimistic.
>>>>>>>>>>
>>>>>>>>>> I seem to recall that the theory was that no such
>>>>>>>>>> software could possibly exist with the new OSes.
>>>>>>>>>
>>>>>>>>>Huh? ARM isn�t an OS; it�s a RISC architecture.
>>>>>>>>
>>>>>>>>It was claimed that the associated OSes would never lose
>>>>>>>>anything. IIRC.
>>>>>>>
>>>>>>>Claimed by whom?
>>>>>>
>>>>>>The people making the promises about RISC. IIRC.
>>>>>>
>>>>>>This was, what, 30 years ago? 25? Details fade.
>>>>>
>>>>> I've been in the hardware and OS side of the business for
>>>>> longer than that, and worked on and OS for the early RISC
>>>>> processor from Motrola, the 88100. I've never heard such a
>>>>> claim about "OS never loosing anything"[*].
>>>>>
>>>>>
>>>>>>It is the RISC proponents who were making these predictions.
>>>>>
>>>>> You'll need to find some citations to support your memory.
>>>>>
>>>>> The claims about RISC have always been around the simplicity
>>>>> of the hardware providing a path to easier and less
>>>>> expensive implementation.
>>>>>
>>>>I suspect that, as an industry insider, you've seen technical
>>>>claims by technical people, and he's seen marketing claims by
>>>>marketing "people".
>>>>
>>>>And you know how accurate marketing claims are.
>>>
>>> I think both points are quite possible.
>>>
>>> Although some of it may have come from articles in BYTE or DDJ.
>>> So perhaps "enthusiasts" rather than "marketing".
>>
>>Entusiasts are simply parroting the marketing spiel.
>
>I'm not sure that was the case. There were, and probably still are, a
>/lot/ of people who really really hate segmented architectures and
>Windows. The marketing campaign was much, much tamer.
>
>BTW, has anyone else noticed this interesting progression:
>1) A claim is reported that RISC processors will take over the world.
>2) I point out that this same claim was made 25 (say) years ago, and
>it didn't happen.
>3) Others claim that modern "segmented" processors are really RISC
>processors which mimic segmentation so the software will run.
>
>Which, of course, leads to the question:
>
>If RISC processors have /already/ taken over the world, why was the
>new prediction made at all?
>
>I suspect that, as always, we have long-since descended into semantic
>mush.

(Hal Heydt)
In a sense...RISC (in the form of ARM designs) *has* taken over
the world. Compare the annual sales of desktop and laptop sales
(mostly x86, Intel and AMD) against the sales of tablets and
"smart" phones (almost exclusively ARM/ARM-derived RISC designs).

Dorothy J Heydt <djheydt@kithrup.com> schrieb:

> (Hal Heydt)
> In a sense...RISC (in the form of ARM designs) *has* taken over
> the world. Compare the annual sales of desktop and laptop sales
> (mostly x86, Intel and AMD) against the sales of tablets and
> "smart" phones (almost exclusively ARM/ARM-derived RISC designs).

And now for the discussion if an architecture with 12000 pages of
manual can be called "reduced" in any meaningful way :-)

I have the Motorola 6800 handbook from 1979 upstairs, it's rather
thin.

On Sat, 3 Dec 2022 20:42:16 GMT, djheydt@kithrup.com (Dorothy J Heydt)
wrote:

>In article <i8r9oh5313imsoa485uf7q87gp0ajarc14@4ax.com>,
>Paul S Person <psperson@old.netcom.invalid> wrote:
>>n Sun, 27 Nov 2022 21:35:09 GMT, djheydt@kithrup.com (Dorothy J Heydt)
>>wrote:
>>
>>>In article <tlhr3e$3nihq$2@newsreader4.netcologne.de>,
>>>Thomas Koenig <tkoenig@netcologne.de> wrote:
>>>>An iPad has 3GB RAM these days, it is astonishing that serious
>>>>business work can be done in a 2GB address space. But I suspect
>>>>that many applications come from earlier times, when 2GB was
>>>>luxury undreamt of.
>>>
>>>(Hal Heydt)
>>>Raspberry Pi 4 Model B comes with up to 8GB. I run the DunDraCon
>>>con reg on a pair (replicated database) of 4GB models. I used to
>>>run it on 1GB SBCs. The shift was because the Pi4B finally got
>>>fast enough I/O to suit me. Con reg kind of rattles around loose
>>>with that much RAM. I suspect that MariaDB just sucks the entire
>>>database into memory.
>>
>>My HP Envy has 12GB (IIRC, the HP Pavilion has 8GB).
>
>(Hal Heydt)
>Ah...but do either of those machines sell for $55? (Ganted,
>that's without PSU, keyboard, mouse/tracball, mass storage
>device, cables, or monitor. But with a KVM switch, some of that
>can be shared. Since I'm using 120GB SSDs for mass storage, the
>*total* outlay for each Pi4B-4 is right about $100 since I
>already had some of the required devices on hand.)

Of course not.

Even though I bought a desktop version [1] through Office Depot at a
discount. (This had two video outputs, DVI and VGA, rather than one
HDMI. As it happened, my existing monitors were both VGA, but one of
them had a DVI port and even included a DVI cable. OTOH, I had no
choice between wired and wireless mouse/keyboard; I got wireless and
so kept the existing trackball/keyboard.)

[1] It has been a while since I checked but, at least at one time, a
/portable/ version of the HP Envy existed -- at a much higher price
than the HP Pavilion I eventually bought or the desktop HP Envy.
--
"In this connexion, unquestionably the most significant
development was the disintegration, under Christian
influence, of classical conceptions of the family and
of family right."

On 12/4/22 7:45 AM, Thomas Koenig wrote:
> Dorothy J Heydt <djheydt@kithrup.com> schrieb:
>
>> (Hal Heydt)
>> In a sense...RISC (in the form of ARM designs) *has* taken over
>> the world. Compare the annual sales of desktop and laptop sales
>> (mostly x86, Intel and AMD) against the sales of tablets and
>> "smart" phones (almost exclusively ARM/ARM-derived RISC designs).
>
> And now for the discussion if an architecture with 12000 pages of
> manual can be called "reduced" in any meaningful way :-)
>
> I have the Motorola 6800 handbook from 1979 upstairs, it's rather
> thin.

All that proves is that not all architectures are documented in the same
detail. The most complex instructions that I know of in ARM are Load
Multiple and Store Multiple. Have you looked at any recent edition of
z/Architecture Principles of Operation?

--
John W. Kennedy
Algernon Burbage, Lord Roderick, Father Martin, Bishop Baldwin,
King Pellinore, Captain Bailey, Merlin -- A Kingdom for a Stage!

On 04/12/2022 23:45, Thomas Koenig wrote:
> Dorothy J Heydt <djheydt@kithrup.com> schrieb:
>
>> (Hal Heydt)
>> In a sense...RISC (in the form of ARM designs) *has* taken over
>> the world. Compare the annual sales of desktop and laptop sales
>> (mostly x86, Intel and AMD) against the sales of tablets and
>> "smart" phones (almost exclusively ARM/ARM-derived RISC designs).
>
> And now for the discussion if an architecture with 12000 pages of
> manual can be called "reduced" in any meaningful way :-)
>
> I have the Motorola 6800 handbook from 1979 upstairs, it's rather
> thin.
And somewhere in a box I have the same for the M88000 - it's two
volumes. :-)

Cheers,
Gary B-)

John W Kennedy <john.w.kennedy@gmail.com> writes:
>On 12/4/22 7:45 AM, Thomas Koenig wrote:
>> Dorothy J Heydt <djheydt@kithrup.com> schrieb:
>>
>>> (Hal Heydt)
>>> In a sense...RISC (in the form of ARM designs) *has* taken over
>>> the world. Compare the annual sales of desktop and laptop sales
>>> (mostly x86, Intel and AMD) against the sales of tablets and
>>> "smart" phones (almost exclusively ARM/ARM-derived RISC designs).
>>
>> And now for the discussion if an architecture with 12000 pages of
>> manual can be called "reduced" in any meaningful way :-)
>>
>> I have the Motorola 6800 handbook from 1979 upstairs, it's rather
>> thin.
>
>All that proves is that not all architectures are documented in the same
>detail. The most complex instructions that I know of in ARM are Load
>Multiple and Store Multiple.

You haven't been paying attention. ARM processors support three distinct
instructions sets (T32, A32, A64). The A64 set includes three distinct
SIMD instruction sets (NEON, SVE, SME). The A64 set inclues instructions
for memory tagging, for pointer authentication, for cryptography, for
data movement (instructions to implement memcpy and memset), in addition
to the normal integer data and bit manipulation instructions.

And the total documentation for the latest ARM processors runs to well
more than 20,000 pages when the interrupt controller, IOMMU and coresight
(external JTAG debug) deocumentation is included.

"Gary R. Schmidt" <grschmidt@acm.org> writes:
>On 04/12/2022 23:45, Thomas Koenig wrote:
>> Dorothy J Heydt <djheydt@kithrup.com> schrieb:
>>
>>> (Hal Heydt)
>>> In a sense...RISC (in the form of ARM designs) *has* taken over
>>> the world. Compare the annual sales of desktop and laptop sales
>>> (mostly x86, Intel and AMD) against the sales of tablets and
>>> "smart" phones (almost exclusively ARM/ARM-derived RISC designs).
>>
>> And now for the discussion if an architecture with 12000 pages of
>> manual can be called "reduced" in any meaningful way :-)
>>
>> I have the Motorola 6800 handbook from 1979 upstairs, it's rather
>> thin.
>And somewhere in a box I have the same for the M88000 - it's two
>volumes. :-)

The original 88100 manual was a single volume for the processor
and a second for the 88200 (MMU).

John W Kennedy <john.w.kennedy@gmail.com> schrieb:
> On 12/4/22 7:45 AM, Thomas Koenig wrote:
>> Dorothy J Heydt <djheydt@kithrup.com> schrieb:
>>
>>> (Hal Heydt)
>>> In a sense...RISC (in the form of ARM designs) *has* taken over
>>> the world. Compare the annual sales of desktop and laptop sales
>>> (mostly x86, Intel and AMD) against the sales of tablets and
>>> "smart" phones (almost exclusively ARM/ARM-derived RISC designs).
>>
>> And now for the discussion if an architecture with 12000 pages of
>> manual can be called "reduced" in any meaningful way :-)
>>
>> I have the Motorola 6800 handbook from 1979 upstairs, it's rather
>> thin.
>
> All that proves is that not all architectures are documented in the same
> detail. The most complex instructions that I know of in ARM are Load
> Multiple and Store Multiple.

Not in the 64-bit version of ARM (aka ARMv8). Take a look at their
vector instructions one day, like (random grab) UQRSHL.

On 06/12/2022 01:19, Scott Lurndal wrote:
> "Gary R. Schmidt" <grschmidt@acm.org> writes:
>> On 04/12/2022 23:45, Thomas Koenig wrote:
>>> Dorothy J Heydt <djheydt@kithrup.com> schrieb:
>>>
>>>> (Hal Heydt)
>>>> In a sense...RISC (in the form of ARM designs) *has* taken over
>>>> the world. Compare the annual sales of desktop and laptop sales
>>>> (mostly x86, Intel and AMD) against the sales of tablets and
>>>> "smart" phones (almost exclusively ARM/ARM-derived RISC designs).
>>>
>>> And now for the discussion if an architecture with 12000 pages of
>>> manual can be called "reduced" in any meaningful way :-)
>>>
>>> I have the Motorola 6800 handbook from 1979 upstairs, it's rather
>>> thin.
>> And somewhere in a box I have the same for the M88000 - it's two
>> volumes. :-)
>
> The original 88100 manual was a single volume for the processor
> and a second for the 88200 (MMU).
>
Mayhap that's what I'm remembering - it's not like I've looked at them
in the last thirty-odd years!

Cheers,
Gary B-)

In article <XnsAF628BD7D2E8taustincagmailcom@85.12.62.232>,
Ninapenda Jibini <taustinca@gmail.com> wrote:
>djheydt@kithrup.com (Dorothy J Heydt) wrote in
>news:rMC1IG.23q6@kithrup.com:
>
>> In article <i8r9oh5313imsoa485uf7q87gp0ajarc14@4ax.com>,
>> Paul S Person <psperson@old.netcom.invalid> wrote:
>>>n Sun, 27 Nov 2022 21:35:09 GMT, djheydt@kithrup.com (Dorothy J
>>>Heydt) wrote:
>>>
>>>>In article <tlhr3e$3nihq$2@newsreader4.netcologne.de>,
>>>>Thomas Koenig <tkoenig@netcologne.de> wrote:
>>>>>An iPad has 3GB RAM these days, it is astonishing that serious
>>>>>business work can be done in a 2GB address space. But I
>>>>>suspect that many applications come from earlier times, when
>>>>>2GB was luxury undreamt of.
>>>>
>>>>(Hal Heydt)
>>>>Raspberry Pi 4 Model B comes with up to 8GB. I run the
>>>>DunDraCon con reg on a pair (replicated database) of 4GB
>>>>models. I used to run it on 1GB SBCs. The shift was because
>>>>the Pi4B finally got fast enough I/O to suit me. Con reg kind
>>>>of rattles around loose with that much RAM. I suspect that
>>>>MariaDB just sucks the entire database into memory.
>>>
>>>My HP Envy has 12GB (IIRC, the HP Pavilion has 8GB).
>>
>> (Hal Heydt)
>> Ah...but do either of those machines sell for $55? (Ganted,
>> that's without PSU, keyboard, mouse/tracball, mass storage
>> device, cables, or monitor. But with a KVM switch, some of that
>> can be shared. Since I'm using 120GB SSDs for mass storage, the
>> *total* outlay for each Pi4B-4 is right about $100 since I
>> already had some of the required devices on hand.)
>>
>Complete kits start under $200, and prices in the last couple of
>years have been *outrageiously* high. They'll come back down
>eventually, to probably 2/3 of that or less.

(Hal Heydt)
Depends on how you buy them. If you go on FleaBay or the like,
yes, you'll pay way over list. If you stick to the authorized
resellers, then you get the RPF parts (SBC, case, video cable,
PSU) for list price.

The current problem is that, like every other electronics
manufacturer on the planet, Pis have been adversely affected by
COVID-induced supply chain disruptions. The RPTL folks have been
open and up-front about the issues, and how they are working to
deal with them. They have give some priority to commercial
customers so as to minimize the adverse impact of shortages on
employment. The rest go into the retail channels--where, due to
high demand and limited supply--they sell out practically as fast
as they can be delivered.

What the RPTL has *not* done is respond to these pressures by
raising list price (with one, very minor, exception). So *if*
you can find a Pi in stock at an authorized reseller, you can buy
it at list price (plus the usual local taxes and shipping).

djheydt@kithrup.com (Dorothy J Heydt) wrote in
news:rMKzJL.1nuE@kithrup.com:

> In article <XnsAF628BD7D2E8taustincagmailcom@85.12.62.232>,
> Ninapenda Jibini <taustinca@gmail.com> wrote:
>>djheydt@kithrup.com (Dorothy J Heydt) wrote in
>>news:rMC1IG.23q6@kithrup.com:
>>
>>> In article <i8r9oh5313imsoa485uf7q87gp0ajarc14@4ax.com>,
>>> Paul S Person <psperson@old.netcom.invalid> wrote:
>>>>n Sun, 27 Nov 2022 21:35:09 GMT, djheydt@kithrup.com (Dorothy
>>>>J Heydt) wrote:
>>>>
>>>>>In article <tlhr3e$3nihq$2@newsreader4.netcologne.de>,
>>>>>Thomas Koenig <tkoenig@netcologne.de> wrote:
>>>>>>An iPad has 3GB RAM these days, it is astonishing that
>>>>>>serious business work can be done in a 2GB address space.
>>>>>>But I suspect that many applications come from earlier
>>>>>>times, when 2GB was luxury undreamt of.
>>>>>
>>>>>(Hal Heydt)
>>>>>Raspberry Pi 4 Model B comes with up to 8GB. I run the
>>>>>DunDraCon con reg on a pair (replicated database) of 4GB
>>>>>models. I used to run it on 1GB SBCs. The shift was because
>>>>>the Pi4B finally got fast enough I/O to suit me. Con reg
>>>>>kind of rattles around loose with that much RAM. I suspect
>>>>>that MariaDB just sucks the entire database into memory.
>>>>
>>>>My HP Envy has 12GB (IIRC, the HP Pavilion has 8GB).
>>>
>>> (Hal Heydt)
>>> Ah...but do either of those machines sell for $55? (Ganted,
>>> that's without PSU, keyboard, mouse/tracball, mass storage
>>> device, cables, or monitor. But with a KVM switch, some of
>>> that can be shared. Since I'm using 120GB SSDs for mass
>>> storage, the *total* outlay for each Pi4B-4 is right about
>>> $100 since I already had some of the required devices on
>>> hand.)
>>>
>>Complete kits start under $200, and prices in the last couple of
>>years have been *outrageiously* high. They'll come back down
>>eventually, to probably 2/3 of that or less.
>
> (Hal Heydt)
> Depends on how you buy them. If you go on FleaBay or the like,
> yes, you'll pay way over list. If you stick to the authorized
> resellers, then you get the RPF parts (SBC, case, video cable,
> PSU) for list price.
>
If you can find them. Therein lies the problem.

--
Terry Austin

"Terry Austin: like the polio vaccine, only with more asshole."
-- David Bilek

Jesus forgives sinners, not criminals.

In article <suipohtuhgss9ttkksqmhcve9dt0iigtsg@4ax.com>,
Paul S Person <psperson@old.netcom.invalid> wrote:
>On Sat, 3 Dec 2022 20:42:16 GMT, djheydt@kithrup.com (Dorothy J Heydt)
>wrote:
>
>>In article <i8r9oh5313imsoa485uf7q87gp0ajarc14@4ax.com>,
>>Paul S Person <psperson@old.netcom.invalid> wrote:
>>>n Sun, 27 Nov 2022 21:35:09 GMT, djheydt@kithrup.com (Dorothy J Heydt)
>>>wrote:
>>>
>>>>In article <tlhr3e$3nihq$2@newsreader4.netcologne.de>,
>>>>Thomas Koenig <tkoenig@netcologne.de> wrote:
>>>>>An iPad has 3GB RAM these days, it is astonishing that serious
>>>>>business work can be done in a 2GB address space. But I suspect
>>>>>that many applications come from earlier times, when 2GB was
>>>>>luxury undreamt of.
>>>>
>>>>(Hal Heydt)
>>>>Raspberry Pi 4 Model B comes with up to 8GB. I run the DunDraCon
>>>>con reg on a pair (replicated database) of 4GB models. I used to
>>>>run it on 1GB SBCs. The shift was because the Pi4B finally got
>>>>fast enough I/O to suit me. Con reg kind of rattles around loose
>>>>with that much RAM. I suspect that MariaDB just sucks the entire
>>>>database into memory.
>>>
>>>My HP Envy has 12GB (IIRC, the HP Pavilion has 8GB).
>>
>>(Hal Heydt)
>>Ah...but do either of those machines sell for $55? (Ganted,
>>that's without PSU, keyboard, mouse/tracball, mass storage
>>device, cables, or monitor. But with a KVM switch, some of that
>>can be shared. Since I'm using 120GB SSDs for mass storage, the
>>*total* outlay for each Pi4B-4 is right about $100 since I
>>already had some of the required devices on hand.)
>
>Of course not.
>
>Even though I bought a desktop version [1] through Office Depot at a
>discount. (This had two video outputs, DVI and VGA, rather than one
>HDMI. As it happened, my existing monitors were both VGA, but one of
>them had a DVI port and even included a DVI cable. OTOH, I had no
>choice between wired and wireless mouse/keyboard; I got wireless and
>so kept the existing trackball/keyboard.)
>
>[1] It has been a while since I checked but, at least at one time, a
>/portable/ version of the HP Envy existed -- at a much higher price
>than the HP Pavilion I eventually bought or the desktop HP Envy.

(Hal Heydt)
DVI-D is signal compatable with HDMI. All you need is--a quite
inexpensive--HDMI to DVI adapter. Or you can get HDMI to DVI
cables. I've got a good sized collection of monitors that all
have at least DVI input. Last batch of adapters I got were less
than $2 each.

VGA is a whole 'nother animal. Conversion requires an active
device and most of the cheap devices to do that aren't very
good. Plus converters are one way only. You get *either* HDMI to
VGA *or* VGA to HDMI.

The other headache that's coming along is DisplyPort (DP). Like
VGA conversion, any given device is either DP to HDMI or HDMI to
DP. DP to HDMI are very common. To find an HDMI to DP, you've
got to sift through a lot of entries. And, again, there are
quality issues as well as having to be an active device.