So, I've basically forgotten a lot from my university days to do with digital electronics, and want to do some things a bit complex on the proposed processor deign. So, any resources out there useful simplified guide for doing a simple 1000 transistor plus core, and designs for memory, rom and storage memory, on the same process? I only am looking at this because I learnt the basics of digital electronic circuit design, and it shouldn't be any more difficult, with the right software.

I want to explore crossing paths to reuse transistors with path depending on selection, maybe by source and destination to establish path and some other tricks, to inactivate alternative paths? I know this is a path to possible problems, especially with age or environmental deterioration. This is for an compacted design. I'm also interested in progressively waking and turning off the circuit (or at least sleep) as the signal moves through it, for energy.

Thanks again.

Wayne.

On Thursday, July 7, 2022 at 9:58:39 AM UTC-4, Wayne morellini wrote:
> So, I've basically forgotten a lot from my university days to do with digital electronics, and want to do some things a bit complex on the proposed processor deign. So, any resources out there useful simplified guide for doing a simple 1000 transistor plus core, and designs for memory, rom and storage memory, on the same process? I only am looking at this because I learnt the basics of digital electronic circuit design, and it shouldn't be any more difficult, with the right software.
>
>
> I want to explore crossing paths to reuse transistors with path depending on selection, maybe by source and destination to establish path and some other tricks, to inactivate alternative paths? I know this is a path to possible problems, especially with age or environmental deterioration. This is for an compacted design. I'm also interested in progressively waking and turning off the circuit (or at least sleep) as the signal moves through it, for energy.

This sounds a bit like async logic design. I don't know about the "crossing paths", that sounds like something that is extremely hard to implement, coming under the heading of extreme optimization. As you may know, optimization is the enemy of flexibility. Optimize in this manner and find you have a simple change to make to fix an error, and you have to do the optimization all over again.

However, if you have nothing but time on your hands, there's no reason to not give it a go. I suggest working with some very simple design first, to solidify your concepts. They certainly can use some degree of solidification.

One power optimization that many people don't understand, is to put enabled registers at the input of each section of logic, rather than at the output of each section. Power is dissipated by the logic elements changing. If a logic section's output is not going to be used, it is the inputs that need to remain stable to prevent power waste in pointless calculations. So enabled registers at the input of each logic section saves that wasted power.

These days, it's not so important to make tiny processors into even smaller processors. Even if you want to put 1000s of them on a single chip, it is better to design for short term goals, than to try to bite off the whole cow at once.

Just some friendly advice. If you follow it, you might just start to get somewhere rather than always talking about a new direction you wish to go.

--

Rick C.

- Get 1,000 miles of free Supercharging
- Tesla referral code - https://ts.la/richard11209

On 7/7/22 8:58 AM, Wayne morellini wrote:
> So, I've basically forgotten a lot from my university days to do with digital electronics, and want to do some things a bit complex on the proposed processor deign. So, any resources out there useful simplified guide for doing a simple 1000 transistor plus core, and designs for memory, rom and storage memory, on the same process? I only am looking at this because I learnt the basics of digital electronic circuit design, and it shouldn't be any more difficult, with the right software.
>
You will need more transistors than that. An ALU, some registers, and
control logic. It adds up fast. A RAM/register cell is 4 transistors in
CMOS plus the access and decode logic.

My course work is now more than 20 years old but way back when the
standard text was:
https://www.amazon.com/CMOS-VLSI-Design-Circuits-Perspective/dp/0321547748

Then of course there was the now wildly outdated course in computer
architecture.

--
http://davesrocketworks.com
David Schultz

On Friday, July 8, 2022 at 12:38:05 AM UTC+10, gnuarm.del...@gmail.com wrote:
> On Thursday, July 7, 2022 at 9:58:39 AM UTC-4, Wayne morellini wrote:
> > So, I've basically forgotten a lot from my university days to do with digital electronics, and want to do some things a bit complex on the proposed processor deign. So, any resources out there useful simplified guide for doing a simple 1000 transistor plus core, and designs for memory, rom and storage memory, on the same process? I only am looking at this because I learnt the basics of digital electronic circuit design, and it shouldn't be any more difficult, with the right software.
> >
> >
> > I want to explore crossing paths to reuse transistors with path depending on selection, maybe by source and destination to establish path and some other tricks, to inactivate alternative paths? I know this is a path to possible problems, especially with age or environmental deterioration. This is for an compacted design. I'm also interested in progressively waking and turning off the circuit (or at least sleep) as the signal moves through it, for energy.
> This sounds a bit like async logic design. I don't know about the "crossing paths", that sounds like something that is extremely hard to implement, coming under the heading of extreme optimization. As you may know, optimization is the enemy of flexibility. Optimize in this manner and find you have a simple change to make to fix an error, and you have to do the optimization all over again.
>
> However, if you have nothing but time on your hands, there's no reason to not give it a go. I suggest working with some very simple design first, to solidify your concepts. They certainly can use some degree of solidification.
>
> One power optimization that many people don't understand, is to put enabled registers at the input of each section of logic, rather than at the output of each section. Power is dissipated by the logic elements changing. If a logic section's output is not going to be used, it is the inputs that need to remain stable to prevent power waste in pointless calculations. So enabled registers at the input of each logic section saves that wasted power.
>
> These days, it's not so important to make tiny processors into even smaller processors. Even if you want to put 1000s of them on a single chip, it is better to design for short term goals, than to try to bite off the whole cow at once.
>
> Just some friendly advice. If you follow it, you might just start to get somewhere rather than always talking about a new direction you wish to go.
>
> --
>
> Rick C.
>
> - Get 1,000 miles of free Supercharging
> - Tesla referral code - https://ts.la/richard11209

Thanks Rick. The stable outputs makes sense. A register doesn't. But maybe there is some circuit to hold the output or inputs stable, but do I want them to turn off completely with the section idea. However, there was that three state logic Chuck was using which was stable, but that would be part of a special node process, not implementable in a normal process?

I look at doing optimisation, because I'm aiming at a low cost 1000+ trasistor design instead of a large complex design. So, the optimisation can be done a lot quicker to a higher perfection. Competition is cost, performance, low energy and reliability. I'm worried about reliability here of a optimised design. It's something I can't prove. Products will last in field certain times.

I didn't go and work at ITV, because they wanted me to self fund going there, and I didn't trust my family, and that turned out to be so true. Otherwise I could have been over there designing processors too by now.

In this small design, there are ways to design to maximise performance or minimise energy, or design more costly for each. It's a matter of picking one of the first two for me. The smaller processor allows for faster processing timed and lower costs. I am interested in using space for memory. Where GA144 uses a segmented space and lots of processors. I'm interested in a low segmented space with flatter addressing, with each segment tied to one of more processors tied to input or code work (thanks fur the pep talk in the other thread, I actually came up with the design to answer many of your objections). So, all cores and inputs/outputs and memory are tightly bonded to the flow of work, with some flexibility to reassign some cores etc, to where there is more work. Using simple signaling coordinating buffer access, a workflow could be pipelined like in a GA row, or mini array. Because the structure is dynamic, the amount of memory available to a core, is not restricted by inter core spacing, like on the 144. Of course I'm looking at banked dual access (and associative) memory techniques. It's more dynamic and general purpose. It's not aimed at what the 144 is aimed at, but in performing custom feature sets simply fast. A perfect processor for an simpler 1970's/1980's computer, to perform most functions. I've already came up with a simple interface to replace D controllers, rs232, parralel, USB, sound, video, wifi on such a computer leaving memory cards as the last thing. Using rom back then could implement the standard part of the functions for the features (in 1976 ram would be thousands for hardly anything). I've worked out I can add lots of patterns on the card proposal at cheap prices. So, some tiling and some object techniques, give you some pretty good imagery with little real memory. Allowing for more state bits stored for the game and graphics in the limited memory. It's not adding things, it's about including enough to make it a good product. holistic design rather thsnr There is a lot I don't intend to add here, unless it is done as a close product. This is just enough to make it marketable.

A 1000+ transistor core on its own is pretty useless, as the 16 bit+ lines are going make it cost. So, adding relatively sized internal memory and IO bus configuration and processing, makes it a marketable product. I'm looking at single core design, but also repeating the then existing core, IO pin configuration blocks and memories, to make a multiple core design simply. It's all tedious work to make things right. If you start out wrong, you can be compromised for the life of the product. So, I don't aim for perfection, but an educational example base designs, hopefully complete and perfect, which can be improved upon. Analyse, use and rely on, at one's own risk. As such, I probably will be looking for an engineer's funded verification.

On Friday, July 8, 2022 at 1:23:03 AM UTC+10, David Schultz wrote:
> On 7/7/22 8:58 AM, Wayne morellini wrote:
> > So, I've basically forgotten a lot from my university days to do with digital electronics, and want to do some things a bit complex on the proposed processor deign. So, any resources out there useful simplified guide for doing a simple 1000 transistor plus core, and designs for memory, rom and storage memory, on the same process? I only am looking at this because I learnt the basics of digital electronic circuit design, and it shouldn't be any more difficult, with the right software.
> >
> You will need more transistors than that. An ALU, some registers, and
> control logic. It adds up fast. A RAM/register cell is 4 transistors in
> CMOS plus the access and decode logic.
>
> My course work is now more than 20 years old but way back when the
> standard text was:
> https://www.amazon.com/CMOS-VLSI-Design-Circuits-Perspective/dp/0321547748
>
> Then of course there was the now wildly outdated course in computer
> architecture.
>
> --
> http://davesrocketworks.com
> David Schultz

That's the lower end target, but will be as big as it will be. It's meant to compete with low cost integrated controllers out there, so size matters. It's straight forwards 16 opcode or less 16 bit misc processor, very light weight processors. Are you from around here? So, hopefully 4 instructions per memory access. In the extreme end of simple value generating and comparing decision tree and data shifting applications. But, not that it can't be used for more advanced applications. I admit, it would be challenge and just have 4 slots per return and data stacks equals 512 transistors, a 4 bit version 128 transistors. A challenge to aim towards. As with the other thread, a coffee maker application requires very little, so a 4 bit version would be fine. Even just storing the stacks in memory leaves two stack pointers. The whole thing slows down, and energy might go up, but a coffeemaker it makes very little difference in practical terms. On chip memory, yes. 4 or 8 bit versions, yes. But, 1000 is only a base line potential target for the core, which die size for cache segment could be increased, and bids width (but then again, optimisation might make extension difficult.

Thanks for the book link David.

Are you from around here?

On 7/7/22 8:22 PM, Wayne morellini wrote:
> Are you from around here?

That depends on where "here" is.

--
http://davesrocketworks.com
David Schultz

On Friday, July 8, 2022 at 11:28:47 AM UTC+10, David Schultz wrote:
> On 7/7/22 8:22 PM, Wayne morellini wrote:
> > Are you from around here?
> That depends on where "here" is.
> --
> http://davesrocketworks.com
> David Schultz
Comp.lang.forth?

On 7/7/22 9:02 PM, Wayne morellini wrote:
> On Friday, July 8, 2022 at 11:28:47 AM UTC+10, David Schultz wrote:
>> On 7/7/22 8:22 PM, Wayne morellini wrote:
>>> Are you from around here?
>> That depends on where "here" is.
>> --
>> http://davesrocketworks.com
>> David Schultz
> Comp.lang.forth?

Nobody can be from there because it is nowhere. Or perhaps wherever the
distributed servers are.

In any case, my first news reader was rn.

--
http://davesrocketworks.com
David Schultz

On Friday, July 8, 2022 at 12:02:55 PM UTC+10, Wayne morellini wrote:
> On Friday, July 8, 2022 at 11:28:47 AM UTC+10, David Schultz wrote:
> > On 7/7/22 8:22 PM, Wayne morellini wrote:
> > > Are you from around here?
> > That depends on where "here" is.
> > --
> > http://davesrocketworks.com
> > David Schultz
> Comp.lang.forth?

Yes. I see you here David. Thanks for the past advice on the magic design tool. I'm still trying to decide if magic or Okad is easier to do this. The glow version is supposed to be used by high school children.

I don't know why they don't go towards magnetic computing you could also print. But it would be potentially a few millions times less energy and much faster.

Does anybody know if their are restrictions on short haul video transmission to a in room tv via a tv digital channel, like they allowed with analogue tv channels?

Is there a way to produce a carrier clock that fast enough on chip? So send to tv from devices.

On Thu, 7 Jul 2022 18:00:34 -0700 (PDT)
Wayne morellini <waynemorellini@gmail.com> wrote:

> But maybe there is some circuit to hold the output or inputs stable,
> but do I want them to turn off completely with the section idea.

Transparent latch? (Not available in most FPGAs)

Wayne morellini <waynemorellini@gmail.com> writes:
> Does anybody know if their are restrictions on short haul video
> transmission to a in room tv via a tv digital channel, like they
> allowed with analogue tv channels?

Nobody cares about that any more. Everyone has cable and TV sets have
HDMI inputs.

On Friday, July 8, 2022 at 6:44:35 PM UTC+10, Paul Rubin wrote:
> Wayne morellini <waynemo...@gmail.com> writes:
> > Does anybody know if their are restrictions on short haul video
> > transmission to a in room tv via a tv digital channel, like they
> > allowed with analogue tv channels?
> Nobody cares about that any more. Everyone has cable and TV sets have
> HDMI inputs.

But HDMI is very impractical for very small portable devices. That's why I'm trying to come up with a HDMI attached relay alternative, but in the meantime digital TV signal is an existing standard that can be adopted in. It's all very messy, but a digital tv signal is a compromise.. do, the question was, what restrictions are there.

On Friday, July 8, 2022 at 5:56:20 PM UTC+10, Jan Coombs wrote:
> On Thu, 7 Jul 2022 18:00:34 -0700 (PDT)
> Wayne morellini <waynemo...@gmail.com> wrote:
>
> > But maybe there is some circuit to hold the output or inputs stable,
> > but do I want them to turn off completely with the section idea.
> Transparent latch? (Not available in most FPGAs)
Thanks Jan.

My.jtmoru 8s vkmy.bsck
Doesn't GA use some three state technology, or something like thyresistor or memristor?

On Thursday, July 7, 2022 at 9:00:35 PM UTC-4, Wayne morellini wrote:
> On Friday, July 8, 2022 at 12:38:05 AM UTC+10, gnuarm.del...@gmail.com wrote:
> > On Thursday, July 7, 2022 at 9:58:39 AM UTC-4, Wayne morellini wrote:
> > > So, I've basically forgotten a lot from my university days to do with digital electronics, and want to do some things a bit complex on the proposed processor deign. So, any resources out there useful simplified guide for doing a simple 1000 transistor plus core, and designs for memory, rom and storage memory, on the same process? I only am looking at this because I learnt the basics of digital electronic circuit design, and it shouldn't be any more difficult, with the right software.
> > >
> > >
> > > I want to explore crossing paths to reuse transistors with path depending on selection, maybe by source and destination to establish path and some other tricks, to inactivate alternative paths? I know this is a path to possible problems, especially with age or environmental deterioration. This is for an compacted design. I'm also interested in progressively waking and turning off the circuit (or at least sleep) as the signal moves through it, for energy.
> > This sounds a bit like async logic design. I don't know about the "crossing paths", that sounds like something that is extremely hard to implement, coming under the heading of extreme optimization. As you may know, optimization is the enemy of flexibility. Optimize in this manner and find you have a simple change to make to fix an error, and you have to do the optimization all over again.
> >
> > However, if you have nothing but time on your hands, there's no reason to not give it a go. I suggest working with some very simple design first, to solidify your concepts. They certainly can use some degree of solidification.
> >
> > One power optimization that many people don't understand, is to put enabled registers at the input of each section of logic, rather than at the output of each section. Power is dissipated by the logic elements changing. If a logic section's output is not going to be used, it is the inputs that need to remain stable to prevent power waste in pointless calculations. So enabled registers at the input of each logic section saves that wasted power..
> >
> > These days, it's not so important to make tiny processors into even smaller processors. Even if you want to put 1000s of them on a single chip, it is better to design for short term goals, than to try to bite off the whole cow at once.
> >
> > Just some friendly advice. If you follow it, you might just start to get somewhere rather than always talking about a new direction you wish to go..
> >
> > --
> >
> > Rick C.
> >
> > - Get 1,000 miles of free Supercharging
> > - Tesla referral code - https://ts.la/richard11209
> Thanks Rick. The stable outputs makes sense. A register doesn't. But maybe there is some circuit to hold the output or inputs stable, but do I want them to turn off completely with the section idea. However, there was that three state logic Chuck was using which was stable, but that would be part of a special node process, not implementable in a normal process?

Tristate??? If you want to turn off logic, that is done at the power connection and has nothing to do with tristate outputs. There is literally no use for tristate outputs in internal logic on a remotely modern chip. They used to provide tristate buffers for long line drivers in FPGAs, in the very earliest devices (circa 1990s), because they allow multiple drivers to implement "wire OR" or "wire AND" buses, eliminating what can be large multiplexer logic. But driving long lines on a chip is slow, so they were quickly eliminated from FPGA designs, being replaced with standard logic.

Powering down logic is typically done on large sections of logic, such as individual peripheral devices. Better is to stop the clock, which eliminates the dynamic power draw. If you are going to use more recent process nodes (anything below approximately 90 nm), they also have significant static current. So stopping the clock is not as effective. Even more recent process nodes (not sure of exact numbers) use special gate geometry to have more control over the channel carriers, and so reduce subthreshold leakage, only high-k dielectrics can mitigate gate oxide leakage which become a problem with the most recent process nodes. So powering down logic can reduce some of the impact of the high static current.

> I look at doing optimisation, because I'm aiming at a low cost 1000+ trasistor design instead of a large complex design. So, the optimisation can be done a lot quicker to a higher perfection. Competition is cost, performance, low energy and reliability. I'm worried about reliability here of a optimised design. It's something I can't prove. Products will last in field certain times.

Instead of a large, complex design (but no more complex than other designs, so not really complex at all), you wish to create a small, complex design, that is complex in ways most people can even imagine.

> I didn't go and work at ITV, because they wanted me to self fund going there, and I didn't trust my family, and that turned out to be so true. Otherwise I could have been over there designing processors too by now.
>
> In this small design, there are ways to design to maximise performance or minimise energy, or design more costly for each. It's a matter of picking one of the first two for me. The smaller processor allows for faster processing timed and lower costs. I am interested in using space for memory. Where GA144 uses a segmented space and lots of processors. I'm interested in a low segmented space with flatter addressing, with each segment tied to one of more processors tied to input or code work (thanks fur the pep talk in the other thread, I actually came up with the design to answer many of your objections). So, all cores and inputs/outputs and memory are tightly bonded to the flow of work, with some flexibility to reassign some cores etc, to where there is more work. Using simple signaling coordinating buffer access, a workflow could be pipelined like in a GA row, or mini array. Because the structure is dynamic, the amount of memory available to a core, is not restricted by inter core spacing, like on the 144. Of course I'm looking at banked dual access (and associative) memory techniques. It's more dynamic and general purpose. It's not aimed at what the 144 is aimed at, but in performing custom feature sets simply fast. A perfect processor for an simpler 1970's/1980's computer, to perform most functions. I've already came up with a simple interface to replace D controllers, rs232, parralel, USB, sound, video, wifi on such a computer leaving memory cards as the last thing. Using rom back then could implement the standard part of the functions for the features (in 1976 ram would be thousands for hardly anything). I've worked out I can add lots of patterns on the card proposal at cheap prices. So, some tiling and some object techniques, give you some pretty good imagery with little real memory. Allowing for more state bits stored for the game and graphics in the limited memory. It's not adding things, it's about including enough to make it a good product. holistic design rather thsnr There is a lot I don't intend to add here, unless it is done as a close product. This is just enough to make it marketable.
>
> A 1000+ transistor core on its own is pretty useless, as the 16 bit+ lines are going make it cost. So, adding relatively sized internal memory and IO bus configuration and processing, makes it a marketable product. I'm looking at single core design, but also repeating the then existing core, IO pin configuration blocks and memories, to make a multiple core design simply. It's all tedious work to make things right. If you start out wrong, you can be compromised for the life of the product. So, I don't aim for perfection, but an educational example base designs, hopefully complete and perfect, which can be improved upon. Analyse, use and rely on, at one's own risk. As such, I probably will be looking for an engineer's funded verification.

Lots of MCUs have very, very little memory, a fraction of 1kB RAM and only a handful kB of Flash. So you don't need to use much memory to design a useful processor. In fact, the real question comes back to application. What is the target application? That will strongly impact the memory size since the memory has the biggest area impact on other small MCUs, and at 1000 transistors, the memory will totally dominate this design, and so, the cost..

In fact, you will see the memory size will be the only important cost controlling feature. If your CPU is 1,000 or 2,000 or even 4,000 transistors will barely matter at all if you have 8 kB of Flash and 1 kB of RAM.

It's only a multi CPU design where the processor size would be optimized usefully, but then you are back to a GA144 sort of design with a scrap of memory on each node. If you add more significant memory to each node, you are back to the memory dominating chip size. If you try to share a single memory between all the nodes, you end up with a chip dominated by routing.

Why do you think no one has been able to improve on this to date? Do you think no one is smart enough?

As I've said, many, many times. Until you select a target application, you won't be able to pick the optimal trade off between the many, many factors involved.

On Friday, July 8, 2022 at 11:58:30 PM UTC+10, gnuarm.del...@gmail.com wrote:
> On Thursday, July 7, 2022 at 9:00:35 PM UTC-4, Wayne morellini wrote:
> > On Friday, July 8, 2022 at 12:38:05 AM UTC+10, gnuarm.del...@gmail.com wrote:
> > > On Thursday, July 7, 2022 at 9:58:39 AM UTC-4, Wayne morellini wrote:
...
> > I look at doing optimisation, because I'm aiming at a low cost 1000+ trasistor design instead of a large complex design. So, the optimisation can be done a lot quicker to a higher perfection. Competition is cost, performance, low energy and reliability. I'm worried about reliability here of a optimised design. It's something I can't prove. Products will last in field certain times.
> Instead of a large, complex design (but no more complex than other designs, so not really complex at all), you wish to create a small, complex design, that is complex in ways most people can even imagine.

Doing it with 1 million transistors by hand on an incredibly intertwined complex circuit would not normally be possible in normal lifetime. 2000 transistors would be exponentially more complex than 1000 transistors. It's likely that only certain parts are optimal to be complexed to get a lot of gains. So, even if the core is 4000 transistors only 1000 or less might be in that category (a lot is memory in a full version). Maybe I should just say the core is without stacks (to the side of the core), but placement of stacks will affect performance.

> Lots of MCUs have very, very little memory, a fraction of 1kB RAM and only a handful kB of Flash. So you don't need to use much memory to design a useful processor. In fact, the real question comes back to application. What is the target application? That will strongly

Most applications. It's general purpose, and can be made with differing amounts of pins, memory or processors. If an open community processor, manufacturers can pick the size of everything while maintaining binary compatibility (obviously, if 4 or 8 bit stacks and memory, 16 bit usage is not included).

> impact the memory size since the memory has the biggest area impact on other small MCUs, and at 1000 transistors, the memory will totally dominate this design, and so, the cost.

Core. Only stack memory and pointers etc to be included, however, I am amending that to potentially not have stacks in the design. Secretly. I'm looking at 2 or less transistor memory design, but sram is likely faster for stacks. If the available node process isn't able to do this, my reaction will likely just be to use what it does support. If I can use rom to implement the features, it is still external to the core figure, which I have been saying is at least 1000 transistors (1000+). For a more fuller design, there would be memory on die, if a memory die can't be packed in cheaply, as a multichip, (sorry loosing track here) instead of the extra cost of connecting it to an external memory. This would hopefully optimise performance and energy. So, there is a certain level of on-chip memory you can have before a multiple chip package or external memory, would be cheaper. The fuller version would include multiple processors tied to the pin workflow. But, that includes the separate core, io and memory section stages, and maybe just a simple one core version with external memory, might be done as proof of concept.

> In fact, you will see the memory size will be the only important cost controlling feature. If your CPU is 1,000 or 2,000 or even 4,000 transistors will barely matter at all if you have 8 kB of Flash and 1 kB of RAM.

I want to explore packaged storage chip concepts, if flash can't be done, like flash. I think that the rom concept might be all that's needed at the cheapest prices. I mean, your coffee maker function can be made right once and not need an update. Plus, external memory is commodity pricing, low processor die runs are more expensive. The reduced core size has distinctive advantages and allows for more in die memory, raising the effective wafer area usage, reducing manufacturing cost per unit of area for the same amount of chips, until you get to the cross over point where using external memory to the die is cheaper. But, it depends on what is available in the manufacturing for the process. It maybe a process set up to support on due memory cheap. But, I really would like to avoid the use of complex external serial dram schemes. That can be done later if things are go well. These motors, and flash have a lot of issues.

> It's only a multi CPU design where the processor size would be optimized usefully,

I described that it can be dynamically setup to maximise usage, for that reason. What ever is surplus to optimal performance can be turned off or clocked down.

> If you add more significant memory to each node, you are back to the memory dominating chip size. If you try to share a single memory between all the nodes, you end up with a chip dominated by routing.

No. The manufacturer adds as much memory and cores as needed. It's just that I want it to support a range from 16 words to megabytes. There would be a simple bus and transactional structure. In my simple scheme for other array processors, there is space for each chip, and shared spaces fur each neighbours but there were some other low complexity buses, including one at a time shared buses. So using signaling as a token passing method you avoid access conflicts. Now, if you have the memory such that the other neighbour can dump work into part of your processor's memory, and signal to you to process it (single user system, programmer can control interactions). You work on other parts of the memory, while the nearest neighbour works on that section, then you work on that section. So, I would like dual access for performance etc, a lot can be done by dividing address sieve up into banks with a common bus, with access lines tied off until the processor is signaled, then the neighbour lines are tied off and the processor accesses. Tieing off can be as simple as not accessing it. But, I do want to restrict rogue executing, incase of a execution fault, so only certain things give down until the user can get out and recover the system by rebooting.

Anyway, having multiple neighbours handling the same data is maybe a bit more complex, but a common bus and signaling, different processors can read and perform processing, and as they process another can access. Unless you pass to nearest neighbour, like a simple pipelined approach, you are likely dealing with chunks, so that processing a chunk will take more time than loading it in, leaving the next processors free to load in. There is a bit more to the scheme than I'm saying, but remember the non neighbour general access is really meant for very heavy unnusual loads, or signaling and exceptional messaging. It could be fine with a single data line serially. However, In have another scheme in mind. But nearest neighbour is at least a group of three processors, which is a lot, and you could say 9 processors etc, but then that might get tricky.

> Why do you think no one has been able to improve on this to date? Do you think no one is smart enough?

Improve on what? Which part are you referring too? I assume others might have done something. Chuck certainly improved on it on various areas. There is a variety of ways to do things, and people often just dint see it. Smart is not the issue, it's only part of it. I've been at this for decades.. You can't just design a ISA, you have to think about the hardware design to make the ISA work better. I might have difficulty now, but I have a wealth of previous experience on this to draw upon, what I can remember. I'm literally making a lot of this up as I type. I used to do that with complex stuff and no experience with a subject, a long time back, faster than I could type or write. You won't find many people like that. I used to think in structure and dynamic structural concepts. People always say stuff, while it's obvious that it can be done differently. I wish things were a lot better, I got really sick in the death trap I lived in, and literally trapped there against my wishes. I pulled something like 21 or 27 hormone based cockroach baits out over three years or so, and picked up, relatively, before the Lymes like disease there, then something else twisted to that etc, and other things which should have never been done. I had to virtually stop all work on my OS design due to sickness there early on. The last major section so was working on was an API spec for a full body VR control interface, as the last part of my physical controller device interface spec. Every joint and part movements, but that gets down to muscle movements. So fortunately I stopped then, lots of muscle movements to get into, which I wasn't up to speed on. You could literally use such a spec to monitor a patents health non contact remotely.

> As I've said, many, many times. Until you select a target application you won't be able to pick the optimal trade off between the many, many factors involved.

Look Rick, when I was 10 or 12 I was mapping human intelligence worked and how to design it for a machine to do the same. Research since had proved my theory right band improvements since then.

When I was 14, our science teacher (the daughter of the South African mine manager that Roger More played in the movie Gold about a famous mine accident where they hit a pocket of water) told us that perpetual motion machines weren't possible, giving the spinning axis motion stuff. Within 30 seconds I came up with a way it could be fine, and with 15 minutes or so, how to do it with conventional technology, and within 45 minutes, after class, I concluded it would disrupt the economy and energy sectors, and decided it wasn't a good idea. It seems related to other ones out there. I used to annotate what was wrong with summary science articles all the time, and you would be surprised at how much is wrong on each page. So what do you think Rick? You come along with stuff and I keep answering it. But, what have you done that's original thought? The past stuff I'm not putting here, is more new than anything out there. Like contextual serial computing, strange and weird 2 bit, conventional processing like, architectures, fpga dsp and gpu and distributed parralel processing architectures where hundreds of thousands of cores could be useful (obviously I'm dropping the serial contextual stuff, too awkward). .the freakin tic tac patent is like my surface affect design but extended down into the surface to be more robust safe and reliable, which I might have pursued if I hadn't been so sick). I see people with a chunk of what, but they can't see any features, and I tell them to get the best equipment and look for nanolayers of complexity, and that's what they have found now, and also with that patent. And I have to listen to everybody groan about how difficult it is, and what a genius Steve Jobs or other celebrities, were. But, they had the money to do so much more. Some of them really care about people, which is something.

In article <874jzsc7tb.fsf@nightsong.com>,
Paul Rubin <no.email@nospam.invalid> wrote:
>Wayne morellini <waynemorellini@gmail.com> writes:
>> Does anybody know if their are restrictions on short haul video
>> transmission to a in room tv via a tv digital channel, like they
>> allowed with analogue tv channels?
>
>Nobody cares about that any more. Everyone has cable and TV sets have
>HDMI inputs.

If one needs to generate an analogue tv signal, it could be done
on one of the io coprocessors in the raspberry pico.

Groetjes Albert
--
"in our communism country Viet Nam, people are forced to be
alive and in the western country like US, people are free to
die from Covid 19 lol" duc ha
albert@spe&ar&c.xs4all.nl &=n http://home.hccnet.nl/a.w.m.van.der.horst

In article <9c5abe4c-d255-43bd-b92b-7f0d9b2343bfn@googlegroups.com>,
Rick C <gnuarm.deletethisbit@gmail.com> wrote:
<SNIP>
>
>As I've said, many, many times. Until you select a target application,
>you won't be able to pick the optimal trade off between the many, many
>factors involved.

I'm interested to read your comments, but could you please
snip the text you respond to.
Especially because Waynotelli doesnot restrict line length,
so that proper quoting doesn't work, and I'm tricked in reading
his text, again.

>Rick C.

Groetjes Albert
--
"in our communism country Viet Nam, people are forced to be
alive and in the western country like US, people are free to
die from Covid 19 lol" duc ha
albert@spe&ar&c.xs4all.nl &=n http://home.hccnet.nl/a.w.m.van.der.horst

On Friday, July 8, 2022 at 3:17:24 PM UTC-4, none albert wrote:
> In article <9c5abe4c-d255-43bd...@googlegroups.com>,
> Rick C <gnuarm.del...@gmail.com> wrote:
> <SNIP>
> >
> >As I've said, many, many times. Until you select a target application,
> >you won't be able to pick the optimal trade off between the many, many
> >factors involved.
> I'm interested to read your comments, but could you please
> snip the text you respond to.
> Especially because Waynotelli doesnot restrict line length,
> so that proper quoting doesn't work, and I'm tricked in reading
> his text, again.

I'm more inclined to not reply at all. I have no idea what the guy is thinking. As soon as he starts to make a bit of sense, he goes back into wide open, doing everything while doing nothing mode. I can't find much to respond to.

--

Rick C.

-- Get 1,000 miles of free Supercharging
-- Tesla referral code - https://ts.la/richard11209

On Saturday, July 9, 2022 at 6:27:38 AM UTC+10, gnuarm.del...@gmail.com wrote:
> On Friday, July 8, 2022 at 3:17:24 PM UTC-4, none albert wrote:
> > In article <9c5abe4c-d255-43bd...@googlegroups.com>,
> > Rick C <gnuarm.del...@gmail.com> wrote:
> > <SNIP>
> > >
> > >As I've said, many, many times. Until you select a target application,
> > >you won't be able to pick the optimal trade off between the many, many
> > >factors involved.
> > I'm interested to read your comments, but could you please
> > snip the text you respond to.
> > Especially because Waynotelli doesnot restrict line length,
> > so that proper quoting doesn't work, and I'm tricked in reading
> > his text, again.
> I'm more inclined to not reply at all. I have no idea what the guy is thinking. As soon as he starts to make a bit of sense, he goes back into wide open, doing everything while doing nothing mode. I can't find much to respond to.

It's much to do with the talent of the reader. I certainly never have had 10-100x times more talented people react in such ways, usually the opposite.. I have however had more talented, say they don't come here because of this behaviour. Viva le death of Forth, guys.

One doesn't just obstinately dig a little tiny microscopic trench in obscure territory, and declare "There is no gold here!". You have to dig for it, everywhere you can, and declare what you actually can find with reason. Google groups is certainly an issue. You can't seem to get through to them, and so the mobile view continues to have no reply icon for many years, and using the desktop version just flashes and jumps around as you try to edit things. So, you have to write it outside to speed up writing many many times, and paste it back in, which is a real problem if the products don't handle compatibility issues between products in the pasting. So, I suggest you talk to them about how their system works. Go to the the menu system, and select feedback. I'm certainly sick of doing it after a handful of times over the years, without much success but maybe if more took responsibility for talking to them, they would take responsibility for fixing things. Some groups do and change problems, others don't. I mainly talk to the former.

You could also take responsibility for reading design factors. But where is your original thought to justify commenting and where is your responsibility for reading to understand. As I said, actual superior people don't act like I read here, they are humble and read to understand, rather than not to dismiss. As I said, most better types will not turn up because of this. I get to communicate behind the scenes. But, this is virtually the only place to have discussion left so know of, and it's dominated by deliberate disruption. As a certainly subgroup level of people always, seemingly, do on every technical forum on the internet. Only really naive people can't see past them. Raise your game. If you are going comment, comment rightly. I certainly don't have time to address all the stuff wrongly raised to promote understanding. I woke sick today, and this has caused me to forget an urgent medical appointment. Better to be part of solutions, rather than problems.

On Friday, July 8, 2022 at 10:38:24 PM UTC-4, Wayne morellini wrote:
> On Saturday, July 9, 2022 at 6:27:38 AM UTC+10, gnuarm.del...@gmail.com wrote:
> > On Friday, July 8, 2022 at 3:17:24 PM UTC-4, none albert wrote:
> > > In article <9c5abe4c-d255-43bd...@googlegroups.com>,
> > > Rick C <gnuarm.del...@gmail.com> wrote:
> > > <SNIP>
> > > >
> > > >As I've said, many, many times. Until you select a target application,
> > > >you won't be able to pick the optimal trade off between the many, many
> > > >factors involved.
> > > I'm interested to read your comments, but could you please
> > > snip the text you respond to.
> > > Especially because Waynotelli doesnot restrict line length,
> > > so that proper quoting doesn't work, and I'm tricked in reading
> > > his text, again.
> > I'm more inclined to not reply at all. I have no idea what the guy is thinking. As soon as he starts to make a bit of sense, he goes back into wide open, doing everything while doing nothing mode. I can't find much to respond to.
> It's much to do with the talent of the reader. I certainly never have had 10-100x times more talented people react in such ways, usually the opposite. I have however had more talented, say they don't come here because of this behaviour. Viva le death of Forth, guys.
>
> One doesn't just obstinately dig a little tiny microscopic trench in obscure territory, and declare "There is no gold here!". You have to dig for it, everywhere you can, and declare what you actually can find with reason. Google groups is certainly an issue. You can't seem to get through to them, and so the mobile view continues to have no reply icon for many years, and using the desktop version just flashes and jumps around as you try to edit things. So, you have to write it outside to speed up writing many many times, and paste it back in, which is a real problem if the products don't handle compatibility issues between products in the pasting. So, I suggest you talk to them about how their system works. Go to the the menu system, and select feedback. I'm certainly sick of doing it after a handful of times over the years, without much success but maybe if more took responsibility for talking to them, they would take responsibility for fixing things. Some groups do and change problems, others don't. I mainly talk to the former.
>
> You could also take responsibility for reading design factors. But where is your original thought to justify commenting and where is your responsibility for reading to understand. As I said, actual superior people don't act like I read here, they are humble and read to understand, rather than not to dismiss. As I said, most better types will not turn up because of this. I get to communicate behind the scenes. But, this is virtually the only place to have discussion left so know of, and it's dominated by deliberate disruption. As a certainly subgroup level of people always, seemingly, do on every technical forum on the internet. Only really naive people can't see past them. Raise your game. If you are going comment, comment rightly. I certainly don't have time to address all the stuff wrongly raised to promote understanding. I woke sick today, and this has caused me to forget an urgent medical appointment. Better to be part of solutions, rather than problems.

As usual, you fail to understand. That's ok. I don't really care much about what you talk about. It's really just talk as far as I can tell. The fact that you waste your time responding with such long, involved posts when it's just to defend yourself, in spite of your not caring what I say, says you do care a lot. The point being you are very easily distracted from whatever your goals are.

Stop being weird about what I post that you don't like. Ignore it. Then you will do much better here. Or waste your breath discussing what is not worth discussing and fail to get on with what ever it is you are trying to do.

What I have observed here is that the people who talk about the life or death of Forth accomplish little. Others, who just get on with it, do very well. I don't use Forth a lot. I have designed stack processors over the years and have some ideas I'd like to work on, but have many other priorities at this time. My lack of experience with Forth actually holds me back in not being able to design a good software development tool for one of the processors I want to extend.

--

Rick C.

-+ Get 1,000 miles of free Supercharging
-+ Tesla referral code - https://ts.la/richard11209

On 07/07/2022 14:58, Wayne morellini wrote:
> So, I've basically forgotten a lot from my university days to do with digital electronics, and want to do some things a bit complex on the proposed processor deign.

Does that mean you've no experience of digital hardware design at all?
You're full of ideas on advanced features to incorporate into a
processor, if you've no experience how can you evaluate what is
practical or not?

Have you any significant experience of writing Forth software. If not
how can you devise a suitable instruction set and on-chip architecture
to support the language.

So, any resources out there useful simplified guide for doing a simple
1000 transistor plus core, and designs for memory, rom and storage
memory, on the same process? I only am looking at this because I learnt
the basics of digital electronic circuit design, and it shouldn't be any
more difficult, with the right software

I've heard that sort of statement said before until reality hits.

>
>
> I want to explore crossing paths to reuse transistors with path depending on selection, maybe by source and destination to establish path and some other tricks, to inactivate alternative paths? I know this is a path to possible problems, especially with age or environmental deterioration. This is for an compacted design. I'm also interested in progressively waking and turning off the circuit (or at least sleep) as the signal moves through it, for energy.

No doubt you'll interpret this as negativity, but some negativity is
part of the design process, e.g. you design something and should ask
yourself "why won't this work" - both for hardware and software.

--
Gerry

On Fri, 8 Jul 2022 10:00:52 -0700 (PDT)
Wayne morellini <waynemorellini@gmail.com> wrote:
[]
[Teacher] told us that perpetual motion machines weren't possible, giving the spinning axis motion stuff. Within 30 seconds I came up with a way it could be fine, and with 15 minutes or so, how to do it with conventional technology, and within 45 minutes, after class, I concluded it would disrupt the economy and energy sectors, and decided it wasn't a good idea. It seems related to other ones out there. I used to annotate what was wrong with
[]

Wait: you've invent a PMM and won't tell us?

--
Bah, and indeed Humbug.

On Friday, July 8, 2022 at 9:15:14 AM UTC-4, Wayne morellini wrote:

>impractical for very small portable devices. That's why I'm trying to come up with a HDMI attached relay alternative, but in the >meantime digital TV signal is an existing standard that can be adopted in. It's all very messy, but a digital tv signal is a >compromise.. do, the question was, what restrictions are there.

You might be late for that product concept...

https://www.amazon.ca/Dummy-Headless-Display-Emulator-Generation/dp/B07FB4VJL9/ref=asc_df_B07FB4VJL9/?tag=googleshopc0c-20&linkCode=df0&hvadid=335118530598&hvpos=&hvnetw=g&hvrand=12878053212799315034&hvpone=&hvptwo=&hvqmt=&hvdev=c&hvdvcmdl=&hvlocint=&hvlocphy=9001065&hvtargid=pla-901877952212&th=1

On Saturday, July 9, 2022 at 8:16:56 PM UTC+10, Kerr-Mudd, John wrote:
> On Fri, 8 Jul 2022 10:00:52 -0700 (PDT)
> Wayne morellini <waynemo...@gmail.com> wrote:
> []
> [Teacher] told us that perpetual motion machines weren't possible, giving the spinning axis motion stuff. Within 30 seconds I came up with a way it could be fine, and with 15 minutes or so, how to do it with conventional technology, and within 45 minutes, after class, I concluded it would disrupt the economy and energy sectors, and decided it wasn't a good idea. It seems related to other ones out there. I used to annotate what was wrong with
> []
>
> Wait: you've invent a PMM and won't tell us?
>
> --
> Bah, and indeed Humbug.

Yes. It's a misunderstanding of science. But when you say it like that.. We even had a local guy here decades latter, that lived on the same street as a freind, who was famous for inventing something, but it guess nowhere, and people died. Just saw a video last night of somebody making a device from an old oil company patent, trying to prove to everybody it has no this that or the other. I'm sitting there also going, what about this that or other other" way of faking it. They covered most areas in the video, but not remote projection of electrical energy, and can't convince me they couldn't have hidden a power storage device. But, not everybody is dishonest. I took a careful look at the asymmetrical factors in the design, which is part of the trick. It's all a bit, most guys die unusually, who design these things (which seems to actually
be the case) so we don't want to reveal the complete secret until we hit 100 million subscribers. But, the we don't want to get sued for copying a 50 years old patent, is what gets me. Unless there is a special classification of military classified patent I don't know of, these people should know that dyes t make sense, which might be a strong indicator of a fake. I used to examine sceptic claims for validity (often very fanciful people, looking for what they want to find to discredit instead of objectivity). The only way these sorts of things can work is a trick that violates normal symmetry of reactions. There are many failings in science, such as the notion of quantum randomness and symmetry leading to completely reversible reactions sets. If you have a complete set of reversible symmetrical reactions then you can't have true reversibility, unless you have time reversibility. Which brings up another whole can of worms to do with the generation of matter and interaction with gravitational, and other, forces in a time stream, depending on how things actually work. Anyway, scientifically, further discoveries will sort things out. Some of these theories are stranger than fiction, and even in science fiction, there are a number of key technologies ideas actually covered from historical stories (I do some mild archeological/anthropological information into earliest layers of history where these things happen to be copied from. That's how I'm aware of them. You will find high intelligence capable workers, have an interest in interesting things in general). You get to a level, where people are interested in understanding and exploring sets of information, which less intelligent people are not good at, but merely opinionated about part information as the limit of things. Really bad. An intellectual explorer will at least try to understand the limits of information, even if they can't come up with the information themselves. Believe me, I know people who believe all sorts of things, and apart from put up with their antics, have to tell them why it can't be true (the actual limits of what can be true, but what do I know, you find things are different than what you think at times. We have these holographic universe experts running around, and I point to local independent interaction of forces unless there is a method of remote local interactions, which sub implied a way to instantly interact over distance, or speed limits (maybe implying that light is speed limited by remote interaction speed. But, it is all "if"'s is these hypothesis. Lost my train of thought, a new message notification turned up. I point to diffuse information at distance not interacting. So, you get to need a different version of such a theory, to work, and or local interactions. I'm theorising a local local model.