On Thursday, July 14, 2022 at 8:06:48 AM UTC+2, dxforth wrote:
> On 14/07/2022 15:52, Marcel Hendrix wrote:
> > On Thursday, July 14, 2022 at 2:54:15 AM UTC+2, Paul Rubin wrote:
> >> Marcel Hendrix <m...@iae.nl> writes:
> >> > In your opinion: would it be worth the (i.e. my) effort to translate
> >> > algorithms into an FPGA implementation? I need FP (double precision)
> >> > and it would need to be faster than a current PC
> >> There are definitely applications where using an FPGA is a big win,
> >> because of the high amount of parallelism available. But, you likely
> >> have to design the algorithm specifically for FPGA implementation.
> >>
> >> It may be simpler to use a GPU, if your algorithm can be arranged to
> >> make good use of one.
> >
> > I would need a sponsor (NVIDIA H100 GPU == $36,550).
> iForth Pty Ltd

They might sponsor a few tons of flour.

-marcel

On Thursday, July 14, 2022 at 8:29:16 AM UTC+2, Paul Rubin wrote:
> Marcel Hendrix <m...@iae.nl> writes:
> > I would need a sponsor (NVIDIA H100 GPU == $36,550).
> Can you use a smaller gpu? Or several? Look on tensordock.com for
> rentals starting at 0.32 USD/hour.

Interesting idea! Maybe I can go one step further before throwing cash around.

-marcel

On Thursday, July 14, 2022 at 4:00:10 AM UTC+10, Myron Plichota wrote:
> On Wednesday, July 13, 2022 at 12:43:41 PM UTC-4, Wayne morellini wrote:
> > On Thursday, July 14, 2022 at 2:17:26 AM UTC+10, Myron Plichota wrote:
> > > > What I have observed here is that the people who talk about the life or death of Forth accomplish little. Others, who just get on with it, do very well.
> > >
> > > Well said! And InMyOpinion, the smaller the design commitee, the better. (I'm not good at politics.)
> > > What enables me is cheap FPGA eval kits and free Icarus Verilog design and simulation tools (and doc).
> > >
> > > Trade secret1: You don't need to be a Grand Master Of Verilog to express the desired results.
> > > Trade secret2: Test your original hardware modules with at least 1 test bench before you trust them.
> > > These pertain to the entire design, whether CPU, (initialized)RAM, or IO modules.
> > >
> > > I posit that since I have designed reliable SoCs on FPGA eval boards, anyone else can, with due diligence.
> > > Due diligence starts with knowing what you want, and what the board, FPGA fabric and tools you are using provide.
> > > We have vast opportunities.
> > >
> > > Jimbo is not James Bond.
> > > - Myron Plichota
> > You realise who has done 0 to doing a public forth processor outside undermining and holding people back?
> > That you aren't good at politics, otherwise you would recognise the proverbial Nazi's in the room, who have
> > hooked you on a leash. Seriously, who are the only people who haven't really contributed anything much?
> >
> > Nobody much, is interested in virtually unsellable FPGA, where a proper forth design would be much better. If you
> > want fpga, there, are processors on some, and smaller FPGA CPU images to use than forth. If you want to
> > make an FPGA into a Forth processor, you have a very slow expensive power hungry forth processor. An
> > FPGA is often about the functionality programmed in, requiring little in an administrative soft CPU. In most
> > instances where this CPU would sell, and fpga one wouldn't, because of their inefficient sloppy style.
> More fool me, I thought I was being 100% positive about grassroots effort in Forth CPU design.
> If you (or anyone else) wish to peruse one of my entirely public (and copyright free) designs, unzip
> https://drive.google.com/file/d/1cWZmDik5PlWaEd-srekTiF51chDR8b7_/view?usp=sharing
> Jimbo is not James Bond.
> - Myron Plichota

I love you man! I agree with
your effort, but my point
was that you shouldn't be
positive about people so
positive, that they hold
positive people back. We
see this in most threads on
the subject, it is just killing
things for decades.
Imagine 100's of billions of
dollars just vanishing into
the distance. That's the
difference negative people have made to forth
hardware Now, it's nearly
pointless. GA should make
a different language and
call it Glow! (Glow for
schools, include some icon
and object based
programming modelling).
Just to try to stay away
from this sort of
negativity. People with low
real forwards talent, that
just want to jump in on
things.

Now, for FPGA. Until a
programmable circuit costs
closer to the same as custom
silicon, in high volume and
performs just as well, it is
two different markets. FPGA
lower entry point for lower
volumes often, and custom
for lower price at higher
volumes with higher
performance. FPGA, is there,
I'm more interested in the
custom silicon. If I can get
close enough with a
programmable circuit device
on metrics, that would be ok,
then. If the difference in
energy, speed, price, were 10
times or less (such as, for
example, each were 3.33
times different, combined,
that would be great. Which is
why I'm thinking a more
conventional single
programmable hard gate
array device, similar to
performance difference as
they did with Novix) might
get on that range. You can
literally manufacture
hundreds of millions of
blanks, and everybody buy a
pack according to the size
they need, and keep using the
same pack for projects for
years. When I did my
research into doing in house
fabrication years ago, I
determined such a scheme
es the way to go.

It's a shame Chuck didn't just
go to Mos technologies years
ago. Sure Jack would
probably try to give him a
pretty resistible deal, but they
could have afforded to
upgrade the plant to smaller
node processes, and
manufacture cheap and sold
a stack of chips, at 10mhz
maybe, on the old lines, and
keep up to 3x clock
advantage on a new process.
The whole bottom end of the
industry could still be
dominated by a superior
efficiency it.

When we look at what can be
done cheaper, it's pretty
poor. In matter of fact, those
4 bit Chinese processor
factories could be used to
make an ultra low spec misc,
as part of the product line.
They could literally make
smart watch MCU lines,
cheaper than wear os
devices. People lack
inventive practical
imaginations. Such a design.
Would be suitable for
wireless autonomous
interactive smart tags.
Starting at around a cent or
something. Program and
install, and you are off. An
advanced tag is an Access or
Info Panel, even a $1000
dollar one, controlled by the
same sort of technology.
Military for $10,000 all
endurance panel.

The truth of the matter. You ask some people, and
you won't make a single
dollar, even loose millions.
They will say it won't
succeed, that won't succeed.
All in their superiority, which
has no evidence. We all seen
tech companies fall over left
right and centre due to
incompetence over the
decades. You sit back and
say why are they doing this or
that for years, and they fall
over, not being able to see
how wrong those decisions
were, and not selecting the
right decisions which made
other companies succeed.
I've done enough with
companies to know, even
when you hand them things
on a platter, they still manage
to stuff things up. You can't
even help them for their own
good.

On Thursday, 14 July 2022 at 08:23:54 UTC+1, Wayne morellini wrote:
> On Thursday, July 14, 2022 at 4:00:10 AM UTC+10, Myron Plichota wrote:
> > On Wednesday, July 13, 2022 at 12:43:41 PM UTC-4, Wayne morellini wrote:
> > > On Thursday, July 14, 2022 at 2:17:26 AM UTC+10, Myron Plichota wrote:
> > > > > What I have observed here is that the people who talk about the life or death of Forth accomplish little. Others, who just get on with it, do very well.
> > > >
> > > > Well said! And InMyOpinion, the smaller the design commitee, the better. (I'm not good at politics.)
> > > > What enables me is cheap FPGA eval kits and free Icarus Verilog design and simulation tools (and doc).
> > > >
> > > > Trade secret1: You don't need to be a Grand Master Of Verilog to express the desired results.
> > > > Trade secret2: Test your original hardware modules with at least 1 test bench before you trust them.
> > > > These pertain to the entire design, whether CPU, (initialized)RAM, or IO modules.
> > > >
> > > > I posit that since I have designed reliable SoCs on FPGA eval boards, anyone else can, with due diligence.
> > > > Due diligence starts with knowing what you want, and what the board, FPGA fabric and tools you are using provide.
> > > > We have vast opportunities.
> > > >
> > > > Jimbo is not James Bond.
> > > > - Myron Plichota
> > > You realise who has done 0 to doing a public forth processor outside undermining and holding people back?
> > > That you aren't good at politics, otherwise you would recognise the proverbial Nazi's in the room, who have
> > > hooked you on a leash. Seriously, who are the only people who haven't really contributed anything much?
> > >
> > > Nobody much, is interested in virtually unsellable FPGA, where a proper forth design would be much better. If you
> > > want fpga, there, are processors on some, and smaller FPGA CPU images to use than forth. If you want to
> > > make an FPGA into a Forth processor, you have a very slow expensive power hungry forth processor. An
> > > FPGA is often about the functionality programmed in, requiring little in an administrative soft CPU. In most
> > > instances where this CPU would sell, and fpga one wouldn't, because of their inefficient sloppy style.
> > More fool me, I thought I was being 100% positive about grassroots effort in Forth CPU design.
> > If you (or anyone else) wish to peruse one of my entirely public (and copyright free) designs, unzip
> > https://drive.google.com/file/d/1cWZmDik5PlWaEd-srekTiF51chDR8b7_/view?usp=sharing
> > Jimbo is not James Bond.
> > - Myron Plichota
> I love you man! I agree with
> your effort, but my point
> was that you shouldn't be
> positive about people so
> positive, that they hold
> positive people back. We
> see this in most threads on
> the subject, it is just killing
> things for decades.
> Imagine 100's of billions of
> dollars just vanishing into
> the distance. That's the
> difference negative people have made to forth
> hardware Now, it's nearly
> pointless. GA should make
> a different language and
> call it Glow! (Glow for
> schools, include some icon
> and object based
> programming modelling).
> Just to try to stay away
> from this sort of
> negativity. People with low
> real forwards talent, that
> just want to jump in on
> things.
>
> Now, for FPGA. Until a
> programmable circuit costs
> closer to the same as custom
> silicon, in high volume and
> performs just as well, it is
> two different markets. FPGA
> lower entry point for lower
> volumes often, and custom
> for lower price at higher
> volumes with higher
> performance. FPGA, is there,
> I'm more interested in the
> custom silicon. If I can get
> close enough with a
> programmable circuit device
> on metrics, that would be ok,
> then. If the difference in
> energy, speed, price, were 10
> times or less (such as, for
> example, each were 3.33
> times different, combined,
> that would be great. Which is
> why I'm thinking a more
> conventional single
> programmable hard gate
> array device, similar to
> performance difference as
> they did with Novix) might
> get on that range. You can
> literally manufacture
> hundreds of millions of
> blanks, and everybody buy a
> pack according to the size
> they need, and keep using the
> same pack for projects for
> years. When I did my
> research into doing in house
> fabrication years ago, I
> determined such a scheme
> es the way to go.
>
> It's a shame Chuck didn't just
> go to Mos technologies years
> ago. Sure Jack would
> probably try to give him a
> pretty resistible deal, but they
> could have afforded to
> upgrade the plant to smaller
> node processes, and
> manufacture cheap and sold
> a stack of chips, at 10mhz
> maybe, on the old lines, and
> keep up to 3x clock
> advantage on a new process.
> The whole bottom end of the
> industry could still be
> dominated by a superior
> efficiency it.
>
> When we look at what can be
> done cheaper, it's pretty
> poor. In matter of fact, those
> 4 bit Chinese processor
> factories could be used to
> make an ultra low spec misc,
> as part of the product line.
> They could literally make
> smart watch MCU lines,
> cheaper than wear os
> devices. People lack
> inventive practical
> imaginations. Such a design.
> Would be suitable for
> wireless autonomous
> interactive smart tags.
> Starting at around a cent or
> something. Program and
> install, and you are off. An
> advanced tag is an Access or
> Info Panel, even a $1000
> dollar one, controlled by the
> same sort of technology.
> Military for $10,000 all
> endurance panel.
>
> The truth of the matter. You ask some people, and
> you won't make a single
> dollar, even loose millions.
> They will say it won't
> succeed, that won't succeed.
> All in their superiority, which
> has no evidence. We all seen
> tech companies fall over left
> right and centre due to
> incompetence over the
> decades. You sit back and
> say why are they doing this or
> that for years, and they fall
> over, not being able to see
> how wrong those decisions
> were, and not selecting the
> right decisions which made
> other companies succeed.
> I've done enough with
> companies to know, even
> when you hand them things
> on a platter, they still manage
> to stuff things up. You can't
> even help them for their own
> good.

Can you please reset you mental countar from 25 to 75 characters per line.
Lines will then be 3x longer than you did,
and normal people can more easily read them.
Thank you.
Or are you doing this on purpose to annoy us?

Marcel Hendrix <mhx@iae.nl> writes:
> > It may be simpler to use a GPU, if your algorithm can be arranged to
> > make good use of one.
> I would need a sponsor (NVIDIA H100 GPU == $36,550).

You made me curious... it's an April Fool's joke?

https://wccftech.com/nvidia-h100-hopper-gpu-monster-graphics-card-with-100-billion-transistors-across-2-dies-43008-cuda-cores-and-48-gb-hbm4-memory/

Andy Valencia
Home page: https://www.vsta.org/andy/
To contact me: https://www.vsta.org/contact/andy.html

On Thursday, July 14, 2022 at 3:15:33 PM UTC+2, Andy Valencia wrote:
> Marcel Hendrix <m...@iae.nl> writes:
> > > It may be simpler to use a GPU, if your algorithm can be arranged to
> > > make good use of one.
> > I would need a sponsor (NVIDIA H100 GPU == $36,550).
> You made me curious... it's an April Fool's joke?
>
> https://wccftech.com/nvidia-h100-hopper-gpu-monster-graphics-card-with-100-billion-transistors-across-2-dies-43008-cuda-cores-and-48-gb-hbm4-memory/

I don't think so. Google returns a couple of references, and at least one
of them is from Nvidia's website.

-marcel

On Thursday, July 14, 2022 at 6:04:58 PM UTC+10, jpit...@gmail.com wrote:
> On Thursday, 14 July 2022 at 08:23:54 UTC+1, Wayne morellini wrote:
> > On Thursday, July 14, 2022 at 4:00:10 AM UTC+10, Myron Plichota wrote:
> > > On Wednesday, July 13, 2022 at 12:43:41 PM UTC-4, Wayne morellini wrote:
> > > > On Thursday, July 14, 2022 at 2:17:26 AM UTC+10, Myron Plichota wrote:

> Can you please reset you mental countar from 25 to 75 characters per line.
> Lines will then be 3x longer than you did,
> and normal people can more easily read them.
> Thank you.
> Or are you doing this on purpose to annoy us?

No, it fits the screen. Is easy to cut.
Makes it easier to read.

On Thursday, 14 July 2022 at 17:04:10 UTC+1, Wayne morellini wrote:
> On Thursday, July 14, 2022 at 6:04:58 PM UTC+10, jpit...@gmail.com wrote:
> > On Thursday, 14 July 2022 at 08:23:54 UTC+1, Wayne morellini wrote:
> > > On Thursday, July 14, 2022 at 4:00:10 AM UTC+10, Myron Plichota wrote:
> > > > On Wednesday, July 13, 2022 at 12:43:41 PM UTC-4, Wayne morellini wrote:
> > > > > On Thursday, July 14, 2022 at 2:17:26 AM UTC+10, Myron Plichota wrote:
>
> > Can you please reset you mental countar from 25 to 75 characters per line.
> > Lines will then be 3x longer than you did,
> > and normal people can more easily read them.
> > Thank you.
> > Or are you doing this on purpose to annoy us?
> No, it fits the screen. Is easy to cut.
> Makes it easier to read.

So you are saying
that you already have a very narrow screen
for an even narrower Forth chip?
Can we still take you serious?

On Friday, July 15, 2022 at 2:11:03 AM UTC+10, jpit...@gmail.com wrote:
> On Thursday, 14 July 2022 at 17:04:10 UTC+1, Wayne morellini wrote:
> > On Thursday, July 14, 2022 at 6:04:58 PM UTC+10, jpit...@gmail.com wrote:
> > > On Thursday, 14 July 2022 at 08:23:54 UTC+1, Wayne morellini wrote:
> > > > On Thursday, July 14, 2022 at 4:00:10 AM UTC+10, Myron Plichota wrote:
> > > > > On Wednesday, July 13, 2022 at 12:43:41 PM UTC-4, Wayne morellini wrote:
> > > > > > On Thursday, July 14, 2022 at 2:17:26 AM UTC+10, Myron Plichota wrote:
> >
> > > Can you please reset you mental countar from 25 to 75 characters per line.
> > > Lines will then be 3x longer than you did,
> > > and normal people can more easily read them.
> > > Thank you.
> > > Or are you doing this on purpose to annoy us?
> > No, it fits the screen. Is easy to cut.
> > Makes it easier to read.
> So you are saying
> that you already have a very narrow screen
> for an even narrower Forth chip?
> Can we still take you serious?

Narrower forth chip ? I didn't mention that in
my reply (actually that was one actual plan that
has some advantages).

But seriously, I knew you would be back to
complain about something. Accept it. I've
got trouble typing at the moment and will have
to leave it.

On Thursday, July 7, 2022 at 11:58:39 PM UTC+10, Wayne morellini wrote:
> So, I've basically forgotten a lot from my university days to do with digital electronics, and want to do some things a bit complex on the proposed processor deign. So, any resources out there useful simplified guide for doing a simple 1000 transistor plus core, and designs for memory, rom and storage memory, on the same process? I only am looking at this because I learnt the basics of digital electronic circuit design, and it shouldn't be any more difficult, with the right software.
>
>
> I want to explore crossing paths to reuse transistors with path depending on selection, maybe by source and destination to establish path and some other tricks, to inactivate alternative paths? I know this is a path to possible problems, especially with age or environmental deterioration. This is for an compacted design. I'm also interested in progressively waking and turning off the circuit (or at least sleep) as the signal moves through it, for energy.
>
>
> Thanks again.
>
>
>
> Wayne.

Syncing forth processor project threads.

On Sunday, September 4, 2022 at 3:06:16 PM UTC+10, Wayne morellini wrote:
> On Thursday, July 7, 2022 at 11:58:39 PM UTC+10, Wayne morellini wrote:
> > So, I've basically forgotten a lot from my university days to do with digital electronics, and want to do some things a bit complex on the proposed processor deign. So, any resources out there useful simplified guide for doing a simple 1000 transistor plus core, and designs for memory, rom and storage memory, on the same process? I only am looking at this because I learnt the basics of digital electronic circuit design, and it shouldn't be any more difficult, with the right software.
> >
> >
> > I want to explore crossing paths to reuse transistors with path depending on selection, maybe by source and destination to establish path and some other tricks, to inactivate alternative paths? I know this is a path to possible problems, especially with age or environmental deterioration. This is for an compacted design. I'm also interested in progressively waking and turning off the circuit (or at least sleep) as the signal moves through it, for energy.
> >
> >
> > Thanks again.
> >
> >
> >
> > Wayne.
>
> Syncing forth processor project threads.

Forth processor project

Is it time for another Forth chip?

https://groups.google.com/u/2/g/comp.lang.forth/c/6adve-Z1ppU

Designing a Forth Processor?

https://groups.google.com/u/2/g/comp.lang.forth/c/9lpG9yey_NQ

A low cost chip prototyping technique.

https://groups.google.com/u/2/g/comp.lang.forth/c/s27tSebmF-I

Comments: ColorForth binary in JavaScript!

https://groups.google.com/u/2/g/comp.lang.forth/c/3py7TwKu6b0

Looking for some advice on Offete p8, p16, p24, p32, p64. Ep16, ep24, ep32, and others.

https://groups.google.com/u/2/g/comp.lang.forth/c/EMgCYdV8NR8

On Monday, September 5, 2022 at 1:23:41 AM UTC+10, Wayne morellini wrote:
> On Sunday, September 4, 2022 at 3:06:16 PM UTC+10, Wayne morellini wrote:
> > On Thursday, July 7, 2022 at 11:58:39 PM UTC+10, Wayne morellini wrote:
> > > So, I've basically forgotten a lot from my university days to do with digital electronics, and want to do some things a bit complex on the proposed processor deign. So, any resources out there useful simplified guide for doing a simple 1000 transistor plus core, and designs for memory, rom and storage memory, on the same process? I only am looking at this because I learnt the basics of digital electronic circuit design, and it shouldn't be any more difficult, with the right software.
> > >
> > >
> > > I want to explore crossing paths to reuse transistors with path depending on selection, maybe by source and destination to establish path and some other tricks, to inactivate alternative paths? I know this is a path to possible problems, especially with age or environmental deterioration. This is for an compacted design. I'm also interested in progressively waking and turning off the circuit (or at least sleep) as the signal moves through it, for energy.
> > >
> > >
> > > Thanks again.
> > >
> > >
> > >
> > > Wayne.
> >
> > Syncing forth processor project threads.
> Forth processor project
>
> Is it time for another Forth chip?
>
> https://groups.google.com/u/2/g/comp.lang.forth/c/6adve-Z1ppU
>
> Designing a Forth Processor?
>
> https://groups.google.com/u/2/g/comp.lang.forth/c/9lpG9yey_NQ
>
> A low cost chip prototyping technique.
>
> https://groups.google.com/u/2/g/comp.lang.forth/c/s27tSebmF-I
>
> Comments: ColorForth binary in JavaScript!
>
> https://groups.google.com/u/2/g/comp.lang.forth/c/3py7TwKu6b0
>
> Looking for some advice on Offete p8, p16, p24, p32, p64. Ep16, ep24, ep32, and others.
>
> https://groups.google.com/u/2/g/comp.lang.forth/c/EMgCYdV8NR8

First list:

Forth processor project

https://groups.google.com/g/comp.lang.forth/c/6adve-Z1ppU/m/ymmLagxEBwAJ