On Wednesday, October 11, 2023 at 8:04:35 AM UTC-7, S wrote:
> On Tuesday, 3 October 2023 at 5:20:51 pm UTC+10, Hugh Aguilar wrote:
> > On Monday, October 2, 2023 at 10:33:55 AM UTC-7, Hans Bezemer wrote:
> > > On Monday, October 2, 2023 at 7:04:44 PM UTC+2, Hugh Aguilar wrote:
> > > > John Hart wrote a simulator for microprocessor code. He was using the
> > > Hans Bezemer
> > I meant SCASW not SCASB --- these were 16-bit opcodes --- not even John Hart
> > is so incompetent that he would use a sequential search for 8-bit opcodes
> > in which the sparse jump-table is only 256 words.
> > "The fastest is of course direct access -
> > where the thing to search is an index to a table."
> > Thank you very much, Captain Obvious!
> Hugh, for my home computer like chip I originally aimed to use 8 bit codes
> as the upper bits of the address space, which is ok in simple tasks.
> I am expanded this to multiple 8 bit spaces, and 16 bits etc and other
> sophisticated schemes into something new. But, I prefered 10 and 20 bits.

Is this in Verilog? Do you support interrupts?
I have a design for a chip but I haven't built it due to not knowing Verilog.
I did write an assembler and simulator for it.
I'm interested in any design that has some creativity to it --- not just a
fork of the J1 processor.

My design is for the HX8K. It has especial support for a byte-code VM.
The idea is to have a 64KW external memory that holds the Forth compiler,
application code and data (more 64KW banks can be provided for large
amounts of data, but the Forth code has to be in the 0th bank).
The 8KW of internal memory is divided into 5KW for machine-code
and 3KW for data. ISRs and other speed-critical code are assembled.

On Thursday, October 12, 2023 at 12:53:28 PM UTC-4, Hugh Aguilar wrote:
> On Wednesday, October 11, 2023 at 8:04:35 AM UTC-7, S wrote:
> > On Tuesday, 3 October 2023 at 5:20:51 pm UTC+10, Hugh Aguilar wrote:
> > > On Monday, October 2, 2023 at 10:33:55 AM UTC-7, Hans Bezemer wrote:
> > > > On Monday, October 2, 2023 at 7:04:44 PM UTC+2, Hugh Aguilar wrote:
> > > > > John Hart wrote a simulator for microprocessor code. He was using the
> > > > Hans Bezemer
> > > I meant SCASW not SCASB --- these were 16-bit opcodes --- not even John Hart
> > > is so incompetent that he would use a sequential search for 8-bit opcodes
> > > in which the sparse jump-table is only 256 words.
> > > "The fastest is of course direct access -
> > > where the thing to search is an index to a table."
> > > Thank you very much, Captain Obvious!
> > Hugh, for my home computer like chip I originally aimed to use 8 bit codes
> > as the upper bits of the address space, which is ok in simple tasks.
> > I am expanded this to multiple 8 bit spaces, and 16 bits etc and other
> > sophisticated schemes into something new. But, I prefered 10 and 20 bits.
> Is this in Verilog? Do you support interrupts?
> I have a design for a chip but I haven't built it due to not knowing Verilog.
> I did write an assembler and simulator for it.
> I'm interested in any design that has some creativity to it --- not just a
> fork of the J1 processor.
>
> My design is for the HX8K.

I'm curious. What did you put in your design that is specific for the HX8K?

> It has especial support for a byte-code VM.
> The idea is to have a 64KW external memory that holds the Forth compiler,
> application code and data (more 64KW banks can be provided for large
> amounts of data, but the Forth code has to be in the 0th bank).
> The 8KW of internal memory is divided into 5KW for machine-code
> and 3KW for data. ISRs and other speed-critical code are assembled.

Why external memory, rather than internal memory in a different FPGA? I think it is easy to find them with 64 kB of internal RAM.

--

Rick C.

-- Get 1,000 miles of free Supercharging
-- Tesla referral code - https://ts.la/richard11209

On Wednesday, October 11, 2023 at 10:30:21 AM UTC+2, none albert wrote:
> In article <9176e0ac-11b5-4048...@googlegroups.com>,
> Hugh Aguilar <hughag...@gmail.com> wrote:
> >On Tuesday, October 3, 2023 at 2:01:05 AM UTC-7, none albert wrote:
> >> In an assembler it is worth it using hash codes.
> >> There are tools to generate a perfect hash... if you are after speed.
> >
> >I'm talking about the simulator that looks up opcodes.
> >Albert van der Horst says "assembler" --- he may be confused
> >about what the topic of discussion is. I'm not talking about
> >the symbol table --- try to be more alert!
> >
> >People are always telling me what I should do,
> >although they have done nothing.
> >
> >A binary search, as I have in SLOW-SWITCH>, has predictable speed.
> >It is easy to calculate the worst-case speed (the maximum number
> >of comparisons), and the worst-case is not much worse than the
> >best-case. Consistency is more important than average speed
> >in a simulator because you may want to simulate the target processor
> >running at a certain Mhz., and simulate each instruction's speed
> >consistent to how many clock-cycles it takes on the target processor.
> >A hash-table could be used in a simulator, but it would be difficult
> >to predict the worst-case speed (a collision followed by a long
> >sequential search).
> You are not paying attention. A perfect hash is O(1) time.

Listening is not one of Hugh strengths. Changing the goalposts is. Praising and promoting his own pet libraries is. But listening? Not really..

Hans Bezemer
> Groetjes Albert
> --
> Don't praise the day before the evening. One swallow doesn't make spring.
> You must not say "hey" before you have crossed the bridge. Don't sell the
> hide of the bear until you shot it. Better one bird in the hand than ten in
> the air. First gain is a cat spinning. - the Wise from Antrim -

On Thursday, October 12, 2023 at 2:23:36 PM UTC-7, Lorem Ipsum wrote:
> On Thursday, October 12, 2023 at 12:53:28 PM UTC-4, Hugh Aguilar wrote:
> > My design is for the HX8K.
> I'm curious. What did you put in your design that is specific for the HX8K?

I'm curious. Why do you think that I'm going to respond to you?
I have told you dozens of times: PISS OFF!

> > It has especial support for a byte-code VM.
> > The idea is to have a 64KW external memory that holds the Forth compiler,
> > application code and data (more 64KW banks can be provided for large
> > amounts of data, but the Forth code has to be in the 0th bank).
> > The 8KW of internal memory is divided into 5KW for machine-code
> > and 3KW for data. ISRs and other speed-critical code are assembled.
> Why external memory, rather than internal memory in a different FPGA?
> I think it is easy to find them with 64 kB of internal RAM.

I think that you should just leave me alone --- nasty troll!

P.S. You are too stupid to know the difference between
64KB and 64KW. You don't known that there is a difference in price
between an 18-bit FPGA with 32KW of internal memory and the
16-bit HX8K with 8KW of internal memory.
I don't think that you are a programmer at all.
You are a total fake. PISS OFF!

On Friday, October 13, 2023 at 4:28:34 AM UTC+2, Hugh Aguilar wrote:
> I think that you should just leave me alone --- nasty troll!
There are plenty of people here that would like to be left alone too. By
a troll whose name shall not be mentioned.

> I don't think that you are a programmer at all.
> You are a total fake. PISS OFF!
Why do you think you're qualified in any way to judge people who've worked
for decades in that line of work? And why do you think people asked for that
judgement, value that judgement - or even care about that judgement?

Hans Bezemer

On Thursday, October 12, 2023 at 10:28:34 PM UTC-4, Hugh Aguilar wrote:
> On Thursday, October 12, 2023 at 2:23:36 PM UTC-7, Lorem Ipsum wrote:
> > On Thursday, October 12, 2023 at 12:53:28 PM UTC-4, Hugh Aguilar wrote:
> > > My design is for the HX8K.
> > I'm curious. What did you put in your design that is specific for the HX8K?
> I'm curious. Why do you think that I'm going to respond to you?
> I have told you dozens of times: PISS OFF!
> > > It has especial support for a byte-code VM.
> > > The idea is to have a 64KW external memory that holds the Forth compiler,
> > > application code and data (more 64KW banks can be provided for large
> > > amounts of data, but the Forth code has to be in the 0th bank).
> > > The 8KW of internal memory is divided into 5KW for machine-code
> > > and 3KW for data. ISRs and other speed-critical code are assembled.
> > Why external memory, rather than internal memory in a different FPGA?
> > I think it is easy to find them with 64 kB of internal RAM.
> I think that you should just leave me alone --- nasty troll!

You confuse me sometimes. You tell me not to respond to you, then you respond to me... which is it???

> P.S. You are too stupid to know the difference between
> 64KB and 64KW.

Yes, I missed that you were saying kW. So, how large are your words? If you say 18 bits, that's not likely. The iCE40 parts don't provide 9, 18 or 36 bit data paths like many other FPGAs.

> You don't known that there is a difference in price
> between an 18-bit FPGA with 32KW of internal memory and the
> 16-bit HX8K with 8KW of internal memory.

There are many prices for these devices. What you might not appreciate is that while Lattice prices through Digikey, may be close to actual prices you will get from other distribution, the prices for other brands are artificially high at Digikey, because they will negotiate better prices through other channels.

> I don't think that you are a programmer at all.
> You are a total fake. PISS OFF!

I thought we had discussed this before. I am a hardware designer who programs as needed. I typically use VHDL for hardware and forth for software. You have your own special standards for who you consider to be a "programmer". That's not important to me. I use software as a tool to get my work done. I'm not trying to achieve sainthood through programming.

I will say that from what you have described of your hardware designs, you are not much of a hardware designer. When I've tried to offer advice, you get cranky and refuse my suggestions. That's ok too. At least no one can blame me for your lack of progress.

--

Rick C.

-+ Get 1,000 miles of free Supercharging
-+ Tesla referral code - https://ts.la/richard11209

On 13/10/2023 6:41 pm, Hans Bezemer wrote:
> On Friday, October 13, 2023 at 4:28:34 AM UTC+2, Hugh Aguilar wrote:
>> I think that you should just leave me alone --- nasty troll!
> There are plenty of people here that would like to be left alone too. By
> a troll whose name shall not be mentioned.
>
>> I don't think that you are a programmer at all.
>> You are a total fake. PISS OFF!
>
> Why do you think you're qualified in any way to judge people who've worked
> for decades in that line of work? And why do you think people asked for that
> judgement, value that judgement - or even care about that judgement?

In any society the greatest insult is to be told one has 'achieved nothing'.

On Friday, October 13, 2023 at 12:41:11 AM UTC-7, Hans Bezemer wrote:
> On Friday, October 13, 2023 at 4:28:34 AM UTC+2, Hugh Aguilar wrote:
> > I don't think that you [Rick Collins] are a programmer at all.
> > You are a total fake. PISS OFF!

> Why do you think you're qualified in any way to judge people who've worked
> for decades in that line of work? And why do you think people asked for that
> judgement, value that judgement - or even care about that judgement?

If John Hart had said in 1994 that I'm in no way qualified to write software
except as a code-monkey who has to be told exactly what to do,
then MFX would not have been written. Neither of the two programmers
at Testra (John Hart and Steve Brault) were capable of writing MFX.

I can easily see that Rick Collins is a total fake.
He has never written any Forth code that anybody has ever seen.
You are a total fake too --- you produce instructional videos in which
you teach us that your 8086 Forth is "Harvard Architecture."

During my job interview at Testra, John Hart told me that Tom Hart
had written a text user-interface package in UR/Forth that he was
very proud of, and he asked me if I wanted to become an expert in
using it. I said: "No!" John Hart laughed and said: "Nobody ever does."
I knew at that time that Tom Hart was a total fake. This was confirmed
during my lengthy employment there when I saw Tom Hart show up
every couple of weeks to spend a couple of hours acting like a big boss,
but he never wrote any code or did any hardware design or made any
technical contribution whatsoever.

Tom Hart responded to Juergen Pintaske as his peer.
This is because Juergen Pintaske is totally focused on the idea
that a programmer needs validation from somebody important
to be considered to be a programmer, and Tom Hart felt flattered
that Juergen Pintaske considered him to be that important person.
Juergen Pintaske felt flattered that Tom Hart responded to him
because most people ignore him. Tom Hart and Juergen Pintaske
mutually flattered each other --- effectively jerking each other off.

Juergen Pintaske contacted your employer and tried to convince
them to denounce you on comp.lang.forth the same way that
he convinced Tom Hart to denounce me on comp.lang.forth.
They did not respond to him.
Now you support Juergen Pintaske in attacking me.
Why don't you just be a man an admit that you have been wrong
in your understanding of Harvard Architecture? Would it really
kill you to admit your mistake? Instead you persist in being
wrong, making a complete fool out of yourself --- and you ally
yourself with Juergen Pintaske in attacking me to appease him
so that he stops attacking you. Coward!

On Saturday, October 14, 2023 at 2:12:44 AM UTC+2, Hugh Aguilar wrote:
> I can easily see that Rick Collins is a total fake.
> He has never written any Forth code that anybody has ever seen.
I know of another guy who says he's written "fast switch" libs and "string
stack" libs - and nobody has ever seen the code. It seems Rick is not the
only fake wandering around in this forum.

> You are a total fake too --- you produce instructional videos in which
> you teach us that your 8086 Forth is "Harvard Architecture."
Last time, I was thinking of challenging dxforth to take a bet with me
that you would bring this up again. Gee - I should have done that! Darn!

And I've had my own Forth compiler since 1994. I don't need to blame
another vendor if my pet code doesn't work anymore. So who is the
fake here?

> Juergen Pintaske contacted your employer and tried to convince
> them to denounce you on comp.lang.forth the same way that
> he convinced Tom Hart to denounce me on comp.lang.forth.
> They did not respond to him.
I've been playing the corporate game for decades now. It comes with
the job. Did "I've never written any Forth" really think I wouldn't be
prepared? Think again.

> Now you support Juergen Pintaske in attacking me.
I'm not attacking you. I've been trying for ages to talk some sense
into you. But like I said before: you-just-don't-listen. You've been
making a fool of yourself for ages - and you don't even seem to get
it.

So - that was fun. If you want to get serious, lemme know.

Hans Bezemer

On Saturday, October 14, 2023 at 11:41:47 AM UTC-4, Hans Bezemer wrote:
>
> I'm not attacking you. I've been trying for ages to talk some sense
> into you. But like I said before: you-just-don't-listen. You've been
> making a fool of yourself for ages - and you don't even seem to get
> it.

It's not just himself who is being made a fool of. We (anyone to responds to him) are the fools.

I would love to have a rational discussion with him. But there's always something that triggers his delusions of persecution. I think he is afraid of a discussion with me ever since he complained about some "inefficient" code I posted, where his approach had exactly the same issue. Others chimed into to point out that our code worked identically and he simply stopped replying. The reality is it was no big deal. It was just the hypocrisy of his remarks that made everyone dump on him.

--

Rick C.

+- Get 1,000 miles of free Supercharging
+- Tesla referral code - https://ts.la/richard11209

On Sunday, October 15, 2023 at 7:30:28 AM UTC+2, Lorem Ipsum wrote:

> It's not just himself who is being made a fool of. We (anyone to responds to him) are the fools.
I consider that a defensible position.

> I would love to have a rational discussion with him. But there's always
> something that triggers his delusions of persecution.
Well, that's true. He certainly has some trigger points - although they
differ per person. He also sees alliances where there are none. Most of
us have only communicated here in the open - without using any other
channels of communications. But he sees them conspiring behind his
back - with the only objective to damage him.

I can't deny there are some toxic elements here that are certainly out to
damage people. That having said, it's not the majority of people he has
a beef with.

>I think he is afraid of a discussion with me ever since he complained
> about some "inefficient" code I posted, where his approach had
> exactly the same issue. Others chimed into to point out that our code
> worked identically and he simply stopped replying.
There are several "tactics" he uses. One is "moving the goalposts", the
other is "plain contradiction". And yes, once cornered he just disappears -
or plainly ignores any sensible arguments as if they've never been uttered.

The sad thing is - although he has said and done despicable things to
people, I've seen him operate once in quite a different way. I can just
hope he starts to operate in a more constructive way some day. I still
think he has that capacity - although there are plenty of reasons to
differ with this point of view, since he's been going on in this fashion
for so long. It's kind of sad.

Hans Bezemer

On Friday, 13 October 2023 at 2:53:28 am UTC+10, Hugh Aguilar wrote:
> On Wednesday, October 11, 2023 at 8:04:35 AM UTC-7, S wrote:
> > On Tuesday, 3 October 2023 at 5:20:51 pm UTC+10, Hugh Aguilar wrote:
> > > On Monday, October 2, 2023 at 10:33:55 AM UTC-7, Hans Bezemer wrote:
> > > > On Monday, October 2, 2023 at 7:04:44 PM UTC+2, Hugh Aguilar wrote:
> > > > > John Hart wrote a simulator for microprocessor code. He was using the
> > > > Hans Bezemer
> > > I meant SCASW not SCASB --- these were 16-bit opcodes --- not even John Hart
> > > is so incompetent that he would use a sequential search for 8-bit opcodes
> > > in which the sparse jump-table is only 256 words.
> > > "The fastest is of course direct access -
> > > where the thing to search is an index to a table."
> > > Thank you very much, Captain Obvious!
> > Hugh, for my home computer like chip I originally aimed to use 8 bit codes
> > as the upper bits of the address space, which is ok in simple tasks.
> > I am expanded this to multiple 8 bit spaces, and 16 bits etc and other
> > sophisticated schemes into something new. But, I prefered 10 and 20 bits.
> Is this in Verilog? Do you support interrupts?
> I have a design for a chip but I haven't built it due to not knowing Verilog.
> I did write an assembler and simulator for it.
> I'm interested in any design that has some creativity to it --- not just a
> fork of the J1 processor.
>
> My design is for the HX8K. It has especial support for a byte-code VM.
> The idea is to have a 64KW external memory that holds the Forth compiler,
> application code and data (more 64KW banks can be provided for large
> amounts of data, but the Forth code has to be in the 0th bank).
> The 8KW of internal memory is divided into 5KW for machine-code
> and 3KW for data. ISRs and other speed-critical code are assembled.

Sorry Hugh, I completely missed this. I was coming back here to tell you,
that it is obvious you are being persecuted. But, don't worry about the last
20 years, it's the next 20 years you need to concentrate on. Forget these
people, make something good, and bring it out, but don't give up your
present business.

Anyway, back to your reply. I have just figured out the ISA/processing flow
schemes, that's where it starts. I was sharing from my experience a way to
overcome the 8 bit limitations. I've had numerous problems since covid (again)
and am only just getting well enough again to do more work on my legal issue.
So, I've basically had to give up helping my others and myself, to address this.
I'm a pretty much help a chunk of people sort, but unfortunately, people not like
that tend to block the way.

Now, your design. Is the 8 or 5k is divided by 256? I wasn't so good last time to
access my design memory properly, and should have suggested a seperate vector
address space for the 256 locations or 16 or more bits each. This is a seperate bus,
and can even be associative memory, so it passes onto the address bus, it can even
Be that the 8 bit location call forms the upper 8 bits of available memory and the
matching 8 bit location forms the offset. The issue is, without the vector locations,
dividing the address space by 256, is an inefficient use of space, as routines will often
not fit the space slot, and encroach on other slots. To use the encroached slot, you
need an offset, if any room is left, or use a 16 bit vector table. But, to reduce size of the
cpu 8 bit vectors in common memory, would be simpler. What you want, is a way to get
the address in the slot into the address bus for next cycle. That would require some
fancy hard like wiring, but as you are using fpga (is it) the forth cpu cycle should be
so much slower, that you could run a seperate memory controller to see the 8 bit call
coming in and in parallel at shorter cycle, load up the vector on the address bus next
cycle, rather than take an extra 1-2 cycles to complete. It's all reduced size or increased
performance. I try more sophisticated things to get many 8 bit call spaces, but one
thing you should look at with these schemes, for code cross compatibility between
spaces, is too declare the length, and maybe the start, of a code space to be divided
up by 256. So, your 5k gets divided up by 256 by the compiler. But, now it becomes a
pointer and as simple as mask bits to determine where the 8 bits go. Now, the 5k
program can fit anywhere in any practical memory configuration.

If you don't mind me asking, what do you plan to do with the processor?

I wouldn't mind using some of these foga processors if they could get those 4 bit
Chinese chip manufacturers (or watch chip manufacturers), with old chip equipment,
to make a descent version of them, with memory inci style with simple graphics and
sound (maybe with vectors). That's like 6000+ transistors plus memory. As I have
said before, it is as simple as packaging a psram die in the same package as the
processor, even two of them as a separate workspace, you could use as a graphics
buffer buffer, or other use, with dma. I think I was planning on hitting them up at one
stage with the idea of implementing one of the open source designs. Just another
exotic cheap chip, with performance, to sell.

Huge, I encourage you to go somewhere with it.

On Saturday, October 14, 2023 at 10:12:44 AM UTC+10, Hugh Aguilar wrote:

Hugh. How much energy and clock speed were you achieving on the PLD designs?