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devel / comp.lang.forth / Re: FPGA4th

SubjectAuthor
* FPGA4thJohn Hart
+* Re: FPGA4thJurgen Pitaske
|+* Re: FPGA4thA.T. Murray
||`- Re: FPGA4thBrian Fox
|+- Re: FPGA4thHugh Aguilar
|+* Re: FPGA4thJohn Hart
||`* Re: FPGA4thJurgen Pitaske
|| `* Re: FPGA4thJohn Hart
||  +* Re: FPGA4thJurgen Pitaske
||  |`* Re: FPGA4thJurgen Pitaske
||  | `* Re: FPGA4thLorem Ipsum
||  |  `* Re: FPGA4thJurgen Pitaske
||  |   `* Re: FPGA4thLorem Ipsum
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||  |     +- Re: FPGA4thJurgen Pitaske
||  |     `* Re: FPGA4thLorem Ipsum
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||  |           +* Re: FPGA4thJohn Hart
||  |           |+- Re: FPGA4thJurgen Pitaske
||  |           |`- Re: FPGA4thWayne morellini
||  |           `* Re: FPGA4thMyron Plichota
||  |            +- Re: FPGA4thJohn Hart
||  |            +* Re: FPGA4thLorem Ipsum
||  |            |`* Re: FPGA4thnone
||  |            | `* Re: FPGA4thLorem Ipsum
||  |            |  +- Re: FPGA4thJurgen Pitaske
||  |            |  `* Re: FPGA4thdxforth
||  |            |   `* Re: FPGA4thLorem Ipsum
||  |            |    `* Re: FPGA4thWayne morellini
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||  |            |                 `- Re: FPGA4thdxforth
||  |            +- Re: FPGA4thJurgen Pitaske
||  |            +- Re: FPGA4thWayne morellini
||  |            `- Re: FPGA4thWayne morellini
||  `- Re: FPGA4thnone
|`* Re: FPGA4thJohn Hart
| +* Re: FPGA4thJurgen Pitaske
| |`* Re: FPGA4thJohn Hart
| | `- Re: FPGA4thJurgen Pitaske
| +* Re: FPGA4thLorem Ipsum
| |`* Re: FPGA4thJohn Hart
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| | || `- Re: FPGA4thJurgen Pitaske
| | |`- Re: FPGA4thJohn Hart
| | `* Re: FPGA4thHugh Aguilar
| |  +- Re: FPGA4thJurgen Pitaske
| |  +- Re: FPGA4thnone
| |  +- Re: FPGA4thS 1
| |  `* Re: FPGA4thJohn Hart
| |   +* Re: FPGA4thHugh Aguilar
| |   |`* Re: FPGA4thJurgen Pitaske
| |   | `* Re: FPGA4thJohn Hart
| |   |  +- Re: FPGA4thJurgen Pitaske
| |   |  +* Re: FPGA4thHugh Aguilar
| |   |  |`* Re: FPGA4thJurgen Pitaske
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| |   |  |  |`* Re: FPGA4thLorem Ipsum
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| |   |  `* Re: FPGA4thHugh Aguilar
| |   |   +* Re: FPGA4thdxforth
| |   |   |`* Re: FPGA4thAnton Ertl
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| |   |   |    `- Re: FPGA4thJurgen Pitaske
| |   |   `- Re: FPGA4thdxforth
| |   +* Re: FPGA4thLorem Ipsum
| |   |`* Re: FPGA4thJohn Hart
| |   | `- Re: FPGA4thLorem Ipsum
| |   `* Re: FPGA4thHugh Aguilar
| |    `* Re: FPGA4thJurgen Pitaske
| |     `* Re: FPGA4thJohn Hart
| |      +- Re: FPGA4thLorem Ipsum
| |      `* Re: FPGA4thJurgen Pitaske
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| |        `* Re: FPGA4thHugh Aguilar
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| `* Re: FPGA4thHugh Aguilar
`* Re: FPGA4thHugh Aguilar

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Re: FPGA4th

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Subject: Re: FPGA4th
From: waynemor...@gmail.com (Wayne morellini)
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 by: Wayne morellini - Mon, 17 Oct 2022 07:30 UTC

On Monday, October 17, 2022 at 4:29:33 PM UTC+10, jpit...@gmail.com wrote:
...
> Please show us more as you have time.
>
> It reminds me somehow of how Forth started - as a tool for Chuck,
> Here it is a tool for you and for Testra.
> Chuck did not care about the opinion of others, still now does what he enjoys - and many do not understand.
But to understand others aswell, that's the trick.

It's all a bit funny. Instead of me doing my own product I was told to act in ways against it, and get the micromite, or some other such named microcomputer. If there is an open source, miniature fpga multimedia/retro computer, maybe you could add b16 orr ep32 too it, but it's not its own product then, and what you add may get caught up in the open source pool. Still, that would be an interesting thing. But, there is a lot of contrary stuff which happens. I really appreciate Jeff's efforts. He had something we could still be using, which could still be shifting in products today, but it never came out (things went awry). He's the one that nailed the x86 instructions for colorforth and machine forth. We owe a lot to him. The lowest end cell phone, and watch, bar might not be too high compared to that starting design, but with many higher level things, the bar is much higher now, and we need a revised new design to be at that level. If anybody can do fpga at near custom silicone, then it would be easier to get there. At the moment, for the retro designs I'm looking at custom designs within the range of FPGA's, using a basic respin of hardware technology back then, which is great for 1970's and 1980's, early 1990's not for today. Around here, doesn't seem as design adventurous as it once was.

Re: FPGA4th

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Subject: Re: FPGA4th
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 by: none - Mon, 17 Oct 2022 11:26 UTC

In article <c1720c64-6805-4bf0-978a-953661455ad7n@googlegroups.com>,
Lorem Ipsum <gnuarm.deletethisbit@gmail.com> wrote:
>On Sunday, October 16, 2022 at 4:22:36 PM UTC-4, johnro...@gmail.com wrote:
<SNIP>
>> Using verilog tools and IP express, provided by Diamond, it took about two years to move our IP to the X02,
>> I've designed a wide variety of IP from servo system to networks and developed tools along to way to
>> assist in making such devices. For example the software from Lattice used for the RACE could only
>> achieve 80% ultization, I devised a tool that allowed us to achieve 100%,
>
>Silicon is relatively inexpensive, these days. A project has to be very, very high volume to justify such an effort of optimization. I'm currently working
>on a redesign because of component optimization and I'm happy with 100% overkill on a new part, because the chip cost is only $5 each. I could use a $3
>part, but it is 4 kLUT and the previous design was using 90% of a 3 kLUT part. Since it is a change of not just family, but brand, I don't look forward to
>spending excessive time shoehorning a design into a device. That makes alterations in the design prohibitively expensive as well.
>
>Still, with a volume of perhaps 50,000 pieces, I might go with the smaller chip as long as I can share the footprint with the larger part.

You overlook an important detail. The company doesn't save on silicon.
They create value based on proprietary silicon that can not easily be
reverse engineered by others.
>--
>
>Rick C.
>

Groetjes Albert
--
"in our communism country Viet Nam, people are forced to be
alive and in the western country like US, people are free to
die from Covid 19 lol" duc ha
albert@spe&ar&c.xs4all.nl &=n http://home.hccnet.nl/a.w.m.van.der.horst

Re: FPGA4th

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Subject: Re: FPGA4th
From: gnuarm.d...@gmail.com (Lorem Ipsum)
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 by: Lorem Ipsum - Mon, 17 Oct 2022 13:47 UTC

On Monday, October 17, 2022 at 7:26:26 AM UTC-4, none albert wrote:
> In article <c1720c64-6805-4bf0...@googlegroups.com>,
> Lorem Ipsum <gnuarm.del...@gmail.com> wrote:
> >On Sunday, October 16, 2022 at 4:22:36 PM UTC-4, johnro...@gmail.com wrote:
> <SNIP>
> >> Using verilog tools and IP express, provided by Diamond, it took about two years to move our IP to the X02,
> >> I've designed a wide variety of IP from servo system to networks and developed tools along to way to
> >> assist in making such devices. For example the software from Lattice used for the RACE could only
> >> achieve 80% ultization, I devised a tool that allowed us to achieve 100%,
> >
> >Silicon is relatively inexpensive, these days. A project has to be very, very high volume to justify such an effort of optimization. I'm currently working
> >on a redesign because of component optimization and I'm happy with 100% overkill on a new part, because the chip cost is only $5 each. I could use a $3
> >part, but it is 4 kLUT and the previous design was using 90% of a 3 kLUT part. Since it is a change of not just family, but brand, I don't look forward to
> >spending excessive time shoehorning a design into a device. That makes alterations in the design prohibitively expensive as well.
> >
> >Still, with a volume of perhaps 50,000 pieces, I might go with the smaller chip as long as I can share the footprint with the larger part.
> You overlook an important detail. The company doesn't save on silicon.
> They create value based on proprietary silicon that can not easily be
> reverse engineered by others.

You might want to define "easily". The bitstream for a number of Lattice devices has been reverse engineered to the point that there are open source tools that do not rely on any part of the Lattice tools. So how hard can it be to reverse engineer the design?

"For example the software from Lattice used for the RACE could only achieve 80% ultization, I devised a tool that allowed us to achieve 100%,"

I assume this meant he was trying to stay in a given size part. Regardless, I recall from the early days when users would complain to Xilinx that they could only use 90% of the logic in the device, that Xilinx would reply, "We sell you the routing and give you the logic for free", meaning, it would be cost prohibitive to supply adequate routing to achieve 100% use of the logic for every design. Every design has different demands on the routing, so some users' designs are limited by the logic in an FPGA, others' are limited by the routing. That makes perfect sense to me. Achieving 100% utilization of a part is not a useful goal in design work. Getting your design completed in the schedule and budget is normally the important goal.

I recall Hugh talking about how important it was to implement the design in a CPLD rather than a more expensive FPGA because of the cost. I assume Hugh knew something about this, but perhaps not. I believe there are some differences in the accounts of Hugh's involvement.

--

Rick C.

+++ Get 1,000 miles of free Supercharging
+++ Tesla referral code - https://ts.la/richard11209

Re: FPGA4th

<e81bd909-806e-4b4a-a9d8-0e82d6663e6bn@googlegroups.com>

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Subject: Re: FPGA4th
From: jpita...@gmail.com (Jurgen Pitaske)
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 by: Jurgen Pitaske - Mon, 17 Oct 2022 16:24 UTC

On Monday, 17 October 2022 at 14:47:56 UTC+1, gnuarm.del...@gmail.com wrote:
> On Monday, October 17, 2022 at 7:26:26 AM UTC-4, none albert wrote:
> > In article <c1720c64-6805-4bf0...@googlegroups.com>,
> > Lorem Ipsum <gnuarm.del...@gmail.com> wrote:
> > >On Sunday, October 16, 2022 at 4:22:36 PM UTC-4, johnro...@gmail.com wrote:
> > <SNIP>
> > >> Using verilog tools and IP express, provided by Diamond, it took about two years to move our IP to the X02,
> > >> I've designed a wide variety of IP from servo system to networks and developed tools along to way to
> > >> assist in making such devices. For example the software from Lattice used for the RACE could only
> > >> achieve 80% ultization, I devised a tool that allowed us to achieve 100%,
> > >
> > >Silicon is relatively inexpensive, these days. A project has to be very, very high volume to justify such an effort of optimization. I'm currently working
> > >on a redesign because of component optimization and I'm happy with 100% overkill on a new part, because the chip cost is only $5 each. I could use a $3
> > >part, but it is 4 kLUT and the previous design was using 90% of a 3 kLUT part. Since it is a change of not just family, but brand, I don't look forward to
> > >spending excessive time shoehorning a design into a device. That makes alterations in the design prohibitively expensive as well.
> > >
> > >Still, with a volume of perhaps 50,000 pieces, I might go with the smaller chip as long as I can share the footprint with the larger part.
> > You overlook an important detail. The company doesn't save on silicon.
> > They create value based on proprietary silicon that can not easily be
> > reverse engineered by others.
> You might want to define "easily". The bitstream for a number of Lattice devices has been reverse engineered to the point that there are open source tools that do not rely on any part of the Lattice tools. So how hard can it be to reverse engineer the design?
> "For example the software from Lattice used for the RACE could only achieve 80% ultization, I devised a tool that allowed us to achieve 100%,"
> I assume this meant he was trying to stay in a given size part. Regardless, I recall from the early days when users would complain to Xilinx that they could only use 90% of the logic in the device, that Xilinx would reply, "We sell you the routing and give you the logic for free", meaning, it would be cost prohibitive to supply adequate routing to achieve 100% use of the logic for every design. Every design has different demands on the routing, so some users' designs are limited by the logic in an FPGA, others' are limited by the routing. That makes perfect sense to me. Achieving 100% utilization of a part is not a useful goal in design work. Getting your design completed in the schedule and budget is normally the important goal.
>
> I recall Hugh talking about how important it was to implement the design in a CPLD rather than a more expensive FPGA because of the cost. I assume Hugh knew something about this, but perhaps not. I believe there are some differences in the accounts of Hugh's involvement.
>
> --
>
> Rick C.
>
> +++ Get 1,000 miles of free Supercharging
> +++ Tesla referral code - https://ts.la/richard11209

WHAT A SURPRISE.
YOU CANNOT REMEMBER WHAT YOU READ 3 YEARS AGO.
YOU CANNOT REMEMBER WHAT YOU THEN POSTED 3 YEAR AGO.
YOU JUST MAKE IT UP AS YOU THINK IT SUITS.
BUT IT IS ALL DOCUMENTED IN THE THREAD FROM THEN

https://groups.google.com/g/comp.lang.forth/c/wydQr643gX0?pli=1

Re: FPGA4th

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Subject: Re: FPGA4th
Date: Tue, 18 Oct 2022 11:14:29 +1100
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 by: dxforth - Tue, 18 Oct 2022 00:14 UTC

On 18/10/2022 12:47 am, Lorem Ipsum wrote:
>
> I recall Hugh talking about how important it was to implement the design in a CPLD rather than a more expensive FPGA because of the cost. I assume Hugh knew something about this, but perhaps not. I believe there are some differences in the accounts of Hugh's involvement.

I don't recall Hugh ever claiming involvement in the design of the chip
(quite the opposite) but as he was employed to write software in support
of it, he would have gathered various info from the team that did. He's
makes it clear his knowledge of the chip was second-hand:

https://groups.google.com/g/comp.lang.forth/c/moqYqLF64v8/m/BKuFAWlUfEYJ

Re: FPGA4th

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Subject: Re: FPGA4th
From: gnuarm.d...@gmail.com (Lorem Ipsum)
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 by: Lorem Ipsum - Tue, 18 Oct 2022 01:34 UTC

On Monday, October 17, 2022 at 8:14:31 PM UTC-4, dxforth wrote:
> On 18/10/2022 12:47 am, Lorem Ipsum wrote:
> >
> > I recall Hugh talking about how important it was to implement the design in a CPLD rather than a more expensive FPGA because of the cost. I assume Hugh knew something about this, but perhaps not. I believe there are some differences in the accounts of Hugh's involvement.
> I don't recall Hugh ever claiming involvement in the design of the chip
> (quite the opposite) but as he was employed to write software in support
> of it, he would have gathered various info from the team that did. He's
> makes it clear his knowledge of the chip was second-hand:
>
> https://groups.google.com/g/comp.lang.forth/c/moqYqLF64v8/m/BKuFAWlUfEYJ

No, I'm not saying Hugh was involved in designing the CPLD. He simply talked about it being designed. That's why I said I assume he had knowledge of it, but maybe not. It was hard to have a conversation with Hugh. He would go off his nut at very little or even NO provocation at all. Reminds me of some other people here.

I remember trying to talk Hugh off a ledge a number of times, getting him to see that people here were not out to get him, it's just the way people are on the Internet sometimes. Again, reminds me of other people here. One in particular is obsessed with righting wrongs or whatever, by stirring the pot himself in the name of "justice" and clearing his good name. I try not to respond to those people. It seldom is productive in any manner.

But this post is not really useful in this thread. I just wanted to clarify that I didn't think Hugh was directly involved in designing any of the hardware. Heck, from the conversations with him, it was clear that he had no knowledge of designing any sort of PLD. He did want to do something, but had no idea where to begin really, and would not accept any advice either.

--

Rick C.

---- Get 1,000 miles of free Supercharging
---- Tesla referral code - https://ts.la/richard11209

Re: FPGA4th

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 by: Wayne morellini - Wed, 19 Oct 2022 13:36 UTC

On Tuesday, October 18, 2022 at 11:34:16 AM UTC+10, gnuarm.del...@gmail.com wrote:
> On Monday, October 17, 2022 at 8:14:31 PM UTC-4, dxforth wrote:
> > On 18/10/2022 12:47 am, Lorem Ipsum wrote:
> > >
> > > I recall Hugh talking about how important it was to implement the design in a CPLD rather than a more expensive FPGA because of the cost. I assume Hugh knew something about this, but perhaps not. I believe there are some differences in the accounts of Hugh's involvement.
> > I don't recall Hugh ever claiming involvement in the design of the chip
> > (quite the opposite) but as he was employed to write software in support
> > of it, he would have gathered various info from the team that did. He's
> > makes it clear his knowledge of the chip was second-hand:
> >
> > https://groups.google.com/g/comp.lang.forth/c/moqYqLF64v8/m/BKuFAWlUfEYJ
> No, I'm not saying Hugh was involved in designing the CPLD. He simply talked about it being designed. That's why I said I assume he had knowledge of it, but maybe not. It was hard to have a conversation with Hugh. He would go off his nut at very little or even NO provocation at all. Reminds me of some other people here.
>
> I remember trying to talk Hugh off a ledge a number of times, getting him to see that people here were not out to get him, it's just the way people are on the Internet sometimes. Again, reminds me of other people here. One in particular is obsessed with righting wrongs or whatever, by stirring the pot himself in the name of "justice" and clearing his good name. I try not to respond to those people. It seldom is productive in any manner.
>
> But this post is not really useful in this thread. I just wanted to clarify that I didn't think Hugh was directly involved in designing any of the hardware. Heck, from the conversations with him, it was clear that he had no knowledge of designing any sort of PLD. He did want to do something, but had no idea where to begin really, and would not accept any advice either.
>
> --
>
> Rick C.
>
Oh come on. Talk him off a ledge, in which direction?! Even here we see somebody's passive aggressive half baked attitude is the problem! Give up trying to win and going off on these tangents. John's got a point and products, good on him. It does not matter what you think, he has functional ideas implenented, you don't have to use or under mine them. A few people got a bit of a loose screw here, and it's not I. I'm impressed you have a 50k run instead of 5k I was suspecting, but just realised (apart from it not being the different dynanics of a much more intricate 1-5 million plus consumer electronic run being debated previously), you are not as good as when I first met you here many years ago, and most of us aren't. I myself am looking forwards to attempting to do things a fraction of the complexity I once was, and your ability is not what it used to be either. I genuinely feel sorry for High. I know what it's is like to have a few individuals trying to subvertly trying to antagonise, while making out they are not. Some people can't handle that pressure. I believe Hugh can do great things, I'm not negative on that. But every garden has to be grown, not trampled because it's not somebody else's type of garden!

Neurones are rewiring! :)

Re: FPGA4th

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Subject: Re: FPGA4th
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 by: dxforth - Thu, 20 Oct 2022 00:41 UTC

On 20/10/2022 12:36 am, Wayne morellini wrote:
>
> But every garden has to be grown, not trampled because it's not somebody else's type of garden!

The 'Steve' from this thread might be interested in being your gardener:

https://groups.google.com/g/comp.lang.forth/c/fDUuqeiXw0A/m/JJH5DJhxcoYJ

Re: FPGA4th

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 by: Wayne morellini - Thu, 20 Oct 2022 12:52 UTC

On Thursday, October 20, 2022 at 10:41:57 AM UTC+10, dxforth wrote:
> On 20/10/2022 12:36 am, Wayne morellini wrote:
> >
> > But every garden has to be grown, not trampled because it's not somebody else's type of garden!
> The 'Steve' from this thread might be interested in being your gardener:
>
> https://groups.google.com/g/comp.lang.forth/c/fDUuqeiXw0A/m/JJH5DJhxcoYJ

Now, now, no passive aggressive games. You know I'm talking about Hugh needing a gardner. Face it, if we help each other, a lot more would get done. Victimising people of practical talent, is not going help. Even I've thought of going into candle making. It would be a mediocre waste of my talent, if I got well enough to keep up, and not much of a living. I have trouble even finding the email icon and operating email in the last year, simple stuff, and that's as a computer scientist that should be designing such things. So, I've got a long way to go to get back into a descent normal range, and I may have to spend my life at 10%, but I'm an insanely good thinker and real writer, so that's the last things to really go. I get below 10% and it gets bad and a life sapping struggle, 1% and it's real bad. 0.1% and nothing is happening at all. Tick born diseases are the pits, and it's a struggle just to stay above 10 or 50%, not to mention hyper infections of toxo from tick born diseases lowering the immune system (and covid). I thought I might not last till the end of the year a few months ago, before I figured out what was happening and subdued the toxo somewhat. It's a word of warning, this thing is coming fur most people. Sooner or later, the body is going lower the immune system and its going take off like it never does in healthy people, and wreck organs and brain. To do something about it, might be a long and healthy life. The people complained about around here (and it's expected many autism spectrum people) are likely to have some bacterial, fungus and/or parasitical overgrowth. But Asperger's people tend to hold onto some rationality more, so it's not as obvious that's what's happening. Some people get it before very old some get it due to poor constitution younger. It's an active feild of research and one of the most under treated areas of the past (as healthy test subjects and professionals don't represent those people). A the super active stuff, is without those things. 'Do you want the last 90% of your energy? Then Uncle ... Wants You' (for our eastern European members, that's a reference to the old American "Uncle Sam" army recruiting posters). Our countries are living in a hodge podge of humiliating mess. But, without disease, people tend towards becoming Frankenstein's Monster, shallow, emotionally locked on, greedy, and unbalanced too. We are archeiving 10-20 percent in some western societies. Imagine achieving 100 years of technology progress on 10 years. Many of pot current population resource consumption problems could be fixed, in 10 years. That means that in the last 100 years we could have made 1000 years progress,vans skipped a lot of ecological problems! Amazing!

Re: FPGA4th

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Subject: Re: FPGA4th
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 by: dxforth - Fri, 21 Oct 2022 02:38 UTC

On 20/10/2022 11:52 pm, Wayne morellini wrote:
> On Thursday, October 20, 2022 at 10:41:57 AM UTC+10, dxforth wrote:
>> On 20/10/2022 12:36 am, Wayne morellini wrote:
>>>
>>> But every garden has to be grown, not trampled because it's not somebody else's type of garden!
>> The 'Steve' from this thread might be interested in being your gardener:
>>
>> https://groups.google.com/g/comp.lang.forth/c/fDUuqeiXw0A/m/JJH5DJhxcoYJ
>
> Now, now, no passive aggressive games. You know I'm talking about Hugh needing a gardner.

All I saw was metaphors about growing gardens and not allowing others to
trample it.

> Face it, if we help each other, a lot more would get done.

Perhaps c.l.f. doesn't need your help. It gets plenty of free offers as it
is - largely rejected, same as yours.

Why don't you chase up 'Steve' as he seems to hold similar interests to your
own. He appeared to concede c.l.f wasn't the best place for his growing his
MISC garden.

Re: FPGA4th

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Subject: Re: FPGA4th
From: waynemor...@gmail.com (S)
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 by: S - Fri, 21 Oct 2022 03:10 UTC

On Friday, October 21, 2022 at 12:39:01 PM UTC+10, dxforth wrote:
> On 20/10/2022 11:52 pm, Wayne morellini wrote:
> > On Thursday, October 20, 2022 at 10:41:57 AM UTC+10, dxforth wrote:
> >> On 20/10/2022 12:36 am, Wayne morellini wrote:
> >>>
> >>> But every garden has to be grown, not trampled because it's not somebody else's type of garden!
> >> The 'Steve' from this thread might be interested in being your gardener:
> >>
> >> https://groups.google.com/g/comp.lang.forth/c/fDUuqeiXw0A/m/JJH5DJhxcoYJ
> >
> > Now, now, no passive aggressive games. You know I'm talking about Hugh needing a gardner.

> All I saw was metaphors about growing gardens and not allowing others to
> trample it.

Now. It was pretty obvious we were just talking about somebody in particular, who had been badly treated here.

> > Face it, if we help each other, a lot more would get done.
> Perhaps c.l.f. doesn't need your help. It gets plenty of free offers as it
> is - largely rejected, same as yours.

We were talking about helping one another in the context of helping somebody in particular. Look up Look up contrasting and context.

We simply don't need your help!

Re: FPGA4th

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From: dxfo...@gmail.com (dxforth)
Newsgroups: comp.lang.forth
Subject: Re: FPGA4th
Date: Fri, 21 Oct 2022 16:19:23 +1100
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 by: dxforth - Fri, 21 Oct 2022 05:19 UTC

On 21/10/2022 2:10 pm, S wrote:
> On Friday, October 21, 2022 at 12:39:01 PM UTC+10, dxforth wrote:
>> On 20/10/2022 11:52 pm, Wayne morellini wrote:
>>> On Thursday, October 20, 2022 at 10:41:57 AM UTC+10, dxforth wrote:
>>>> On 20/10/2022 12:36 am, Wayne morellini wrote:
>>>>>
>>>>> But every garden has to be grown, not trampled because it's not somebody else's type of garden!
>>>> The 'Steve' from this thread might be interested in being your gardener:
>>>>
>>>> https://groups.google.com/g/comp.lang.forth/c/fDUuqeiXw0A/m/JJH5DJhxcoYJ
>>>
>>> Now, now, no passive aggressive games. You know I'm talking about Hugh needing a gardner.
>
>> All I saw was metaphors about growing gardens and not allowing others to
>> trample it.
>
> Now. It was pretty obvious we were just talking about somebody in particular, who had been badly treated here.

Identifying oneself with Hugh doesn't make for a great C.V. With the exception of
one person who admitted an axe to grind, I don't believe Hugh was treatly badly here
at all. Often his own worst enemy, he burned every bridge he crossed.

>
>>> Face it, if we help each other, a lot more would get done.
>> Perhaps c.l.f. doesn't need your help. It gets plenty of free offers as it
>> is - largely rejected, same as yours.
>
> We were talking about helping one another in the context of helping somebody in particular. Look up Look up contrasting and context.
>
> We simply don't need your help!

Look forward to the day you can say that to everyone.

Re: FPGA4th

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Subject: Re: FPGA4th
From: waynemor...@gmail.com (S)
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 by: S - Fri, 21 Oct 2022 05:44 UTC

On Friday, October 21, 2022 at 3:19:27 PM UTC+10, dxforth wrote:
> On 21/10/2022 2:10 pm, S wrote:
> > On Friday, October 21, 2022 at 12:39:01 PM UTC+10, dxforth wrote:
> >> On 20/10/2022 11:52 pm, Wayne morellini wrote:
> >>> On Thursday, October 20, 2022 at 10:41:57 AM UTC+10, dxforth wrote:
> >>>> On 20/10/2022 12:36 am, Wayne morellini wrote:

> >>> Now, now, no passive aggressive games. You know I'm talking about Hugh needing a gardner.
> >
> >> All I saw was metaphors about growing gardens and not allowing others to
> >> trample it.
> >
> > Now. It was pretty obvious we were just talking about somebody in particular, who had been badly treated here.
> Identifying oneself with Hugh doesn't make for a great C.V. With the exception of
> one person who admitted an axe to grind, I don't believe Hugh was treatly badly here
> at all. Often his own worst enemy, he burned every bridge he crossed.

Good on him. The quality of people coming against him was incredible, and dishonestly making believe about him and their intentions.. For instance, mixing everything up. I don't see myself identified with Hugh, he's different, I just value people, the better the human they are. I know plenty about themselves.

> >>> Face it, if we help each other, a lot more would get done.
> >> Perhaps c.l.f. doesn't need your help. It gets plenty of free offers as it
> >> is - largely rejected, same as yours.
> >
> > We were talking about helping one another in the context of helping somebody in particular. Look up Look up contrasting and context.
> >
> > We simply don't need your help!
> Look forward to the day you can say that to everyone.

Mixing things up. We were talking about people helping people, not everybody not helping anybody. Let's get on, and stop derailing the thread. I've pretty much covered it was bad, John, Hugh et al, being mistreated.

Re: FPGA4th

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From: dxfo...@gmail.com (dxforth)
Newsgroups: comp.lang.forth
Subject: Re: FPGA4th
Date: Fri, 21 Oct 2022 21:27:15 +1100
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 by: dxforth - Fri, 21 Oct 2022 10:27 UTC

On 21/10/2022 4:44 pm, S wrote:
> On Friday, October 21, 2022 at 3:19:27 PM UTC+10, dxforth wrote:
>> On 21/10/2022 2:10 pm, S wrote:
>>> On Friday, October 21, 2022 at 12:39:01 PM UTC+10, dxforth wrote:
>>>> On 20/10/2022 11:52 pm, Wayne morellini wrote:
>>>>> On Thursday, October 20, 2022 at 10:41:57 AM UTC+10, dxforth wrote:
>>>>>> On 20/10/2022 12:36 am, Wayne morellini wrote:
>
>
>>>>> Now, now, no passive aggressive games. You know I'm talking about Hugh needing a gardner.
>>>
>>>> All I saw was metaphors about growing gardens and not allowing others to
>>>> trample it.
>>>
>>> Now. It was pretty obvious we were just talking about somebody in particular, who had been badly treated here.
>> Identifying oneself with Hugh doesn't make for a great C.V. With the exception of
>> one person who admitted an axe to grind, I don't believe Hugh was treatly badly here
>> at all. Often his own worst enemy, he burned every bridge he crossed.
>
> Good on him. The quality of people coming against him was incredible, and dishonestly making believe about him and their intentions.. For instance, mixing everything up. I don't see myself identified with Hugh, he's different, I just value people, the better the human they are. I know plenty about themselves.

Yes, the value you place on people is boundless...

Sep 6, 2022, 10:07:48 PM

"But I, like many intelligent people, just leave them alone to their own delusions.
You can only help certain people."

Worthy of a Nobel Prize for humanity.

Re: FPGA4th

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Subject: Re: FPGA4th
From: waynes...@gmail.com (S 1)
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 by: S 1 - Fri, 21 Oct 2022 22:34 UTC

On Friday, 21 October 2022 at 8:27:18 pm UTC+10, dxforth wrote:
> On 21/10/2022 4:44 pm, S wrote:
> > On Friday, October 21, 2022 at 3:19:27 PM UTC+10, dxforth wrote:
> >> On 21/10/2022 2:10 pm, S wrote:
> >>> On Friday, October 21, 2022 at 12:39:01 PM UTC+10, dxforth wrote:
> >>>> On 20/10/2022 11:52 pm, Wayne morellini wrote:
> >>>>> On Thursday, October 20, 2022 at 10:41:57 AM UTC+10, dxforth wrote:
> >>>>>> On 20/10/2022 12:36 am, Wayne morellini wrote:
> >
> >
> >>>>> Now, now, no passive aggressive games. You know I'm talking about Hugh needing a gardner.
> >>>
> >>>> All I saw was metaphors about growing gardens and not allowing others to
> >>>> trample it.
> >>>
> >>> Now. It was pretty obvious we were just talking about somebody in particular, who had been badly treated here.
> >> Identifying oneself with Hugh doesn't make for a great C.V. With the exception of
> >> one person who admitted an axe to grind, I don't believe Hugh was treatly badly here
> >> at all. Often his own worst enemy, he burned every bridge he crossed.
> >
> > Good on him. The quality of people coming against him was incredible, and dishonestly making believe about him and their intentions.. For instance, mixing everything up. I don't see myself identified with Hugh, he's different, I just value people, the better the human they are. I know plenty about themselves.
> Yes, the value you place on people is boundless...
>
> Sep 6, 2022, 10:07:48 PM
>
> "But I, like many intelligent people, just leave them alone to their own delusions.
> You can only help certain people."
>
> Worthy of a Nobel Prize for humanity.

What are you quoting? But it is certain, you can only do so much, and some are too pathologically disrupted to be able to help further. Meaning they interfere, and will not listen. Moles and trolls.

I'm sorry if you have a need to follow people around, but I'm not interested. It may be good, if you stop derailing thread DX. The relevant side topics of how people have been addressed here have been addressed.

Re: FPGA4th

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Newsgroups: comp.lang.forth
Subject: Re: FPGA4th
Date: Sat, 22 Oct 2022 19:12:19 +1100
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 by: dxforth - Sat, 22 Oct 2022 08:12 UTC

On 22/10/2022 9:34 am, S 1 wrote:
> On Friday, 21 October 2022 at 8:27:18 pm UTC+10, dxforth wrote:
>> On 21/10/2022 4:44 pm, S wrote:
>>> On Friday, October 21, 2022 at 3:19:27 PM UTC+10, dxforth wrote:
>>>> On 21/10/2022 2:10 pm, S wrote:
>>>>> On Friday, October 21, 2022 at 12:39:01 PM UTC+10, dxforth wrote:
>>>>>> On 20/10/2022 11:52 pm, Wayne morellini wrote:
>>>>>>> On Thursday, October 20, 2022 at 10:41:57 AM UTC+10, dxforth wrote:
>>>>>>>> On 20/10/2022 12:36 am, Wayne morellini wrote:
>>>
>>>
>>>>>>> Now, now, no passive aggressive games. You know I'm talking about Hugh needing a gardner.
>>>>>
>>>>>> All I saw was metaphors about growing gardens and not allowing others to
>>>>>> trample it.
>>>>>
>>>>> Now. It was pretty obvious we were just talking about somebody in particular, who had been badly treated here.
>>>> Identifying oneself with Hugh doesn't make for a great C.V. With the exception of
>>>> one person who admitted an axe to grind, I don't believe Hugh was treatly badly here
>>>> at all. Often his own worst enemy, he burned every bridge he crossed.
>>>
>>> Good on him. The quality of people coming against him was incredible, and dishonestly making believe about him and their intentions.. For instance, mixing everything up. I don't see myself identified with Hugh, he's different, I just value people, the better the human they are. I know plenty about themselves.
>> Yes, the value you place on people is boundless...
>>
>> Sep 6, 2022, 10:07:48 PM
>>
>> "But I, like many intelligent people, just leave them alone to their own delusions.
>> You can only help certain people."
>>
>> Worthy of a Nobel Prize for humanity.
>
> What are you quoting? But it is certain, you can only do so much, and some are too pathologically disrupted to be able to help further. Meaning they interfere, and will not listen. Moles and trolls.
>
> I'm sorry if you have a need to follow people around, but I'm not interested. It may be good, if you stop derailing thread DX. The relevant side topics of how people have been addressed here have been addressed.

I'm not responsible for your priorities - or lack thereof. There'd be nothing to discuss
if it wasn't for your "side topics". The image of yourself as a great innovator and how
you have been hard done by pervades all your posts. So yeah - if you can leave all that
behind it would be great. But I seriously doubt you can. It's why you've been compared
with other infamous characters on c.l.f.

Re: FPGA4th

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Subject: Re: FPGA4th
From: waynes...@gmail.com (S 1)
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 by: S 1 - Sat, 22 Oct 2022 15:28 UTC

On Saturday, 22 October 2022 at 6:12:31 pm UTC+10, dxforth wrote:
> On 22/10/2022 9:34 am, S 1 wrote:
> > On Friday, 21 October 2022 at 8:27:18 pm UTC+10, dxforth wrote:
> >> On 21/10/2022 4:44 pm, S wrote:
> >>> On Friday, October 21, 2022 at 3:19:27 PM UTC+10, dxforth wrote:
> >>>> On 21/10/2022 2:10 pm, S wrote:
> >>>>> On Friday, October 21, 2022 at 12:39:01 PM UTC+10, dxforth wrote:
> >>>>>> On 20/10/2022 11:52 pm, Wayne morellini wrote:
> >>>>>>> On Thursday, October 20, 2022 at 10:41:57 AM UTC+10, dxforth wrote:
> >>>>>>>> On 20/10/2022 12:36 am, Wayne morellini wrote:
> >>>
> >>>
> >>>>>>> Now, now, no passive aggressive games. You know I'm talking about Hugh needing a gardner.
> >>>>>
> >>>>>> All I saw was metaphors about growing gardens and not allowing others to
> >>>>>> trample it.
> >>>>>
> >>>>> Now. It was pretty obvious we were just talking about somebody in particular, who had been badly treated here.
> >>>> Identifying oneself with Hugh doesn't make for a great C.V. With the exception of
> >>>> one person who admitted an axe to grind, I don't believe Hugh was treatly badly here
> >>>> at all. Often his own worst enemy, he burned every bridge he crossed..
> >>>
> >>> Good on him. The quality of people coming against him was incredible, and dishonestly making believe about him and their intentions.. For instance, mixing everything up. I don't see myself identified with Hugh, he's different, I just value people, the better the human they are. I know plenty about themselves.
> >> Yes, the value you place on people is boundless...
> >>
> >> Sep 6, 2022, 10:07:48 PM
> >>
> >> "But I, like many intelligent people, just leave them alone to their own delusions.
> >> You can only help certain people."
> >>
> >> Worthy of a Nobel Prize for humanity.
> >
> > What are you quoting? But it is certain, you can only do so much, and some are too pathologically disrupted to be able to help further. Meaning they interfere, and will not listen. Moles and trolls.
> >
> > I'm sorry if you have a need to follow people around, but I'm not interested. It may be good, if you stop derailing thread DX. The relevant side topics of how people have been addressed here have been addressed.

> I'm not responsible for your priorities - or lack thereof.
What a nutty sentence. You got nothing to say a relevance,again, by the looks of it.

No, it's just you being nutty again! As can be seen from your above conversation. If you are jealous of people getting it right, maybe you should try being right instead? If you lack innovation, get some or shut up, stop going on like you are a jealous school girl! You are just being rude and trolling again, who doesn't want to listen. Expressing what (shade) you like to think, with no credible reason to do so. Not a better human to be helped. Wake up and go away!. There is 0 need for you here doing this ego driven garbage.

Thank you.

Re: FPGA4th

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Subject: Re: FPGA4th
Date: Sun, 23 Oct 2022 10:42:53 +1100
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 by: dxforth - Sat, 22 Oct 2022 23:42 UTC

On 23/10/2022 2:28 am, S 1 wrote:
> ...> If you are jealous of people getting it right, maybe you should try being right instead? If you lack innovation, get some or shut up, stop going on like you are a jealous school girl!

So what you have actually accomplished and of which others could rightly be jealous?
I haven't read all of your posts and it's possible I missed it among the accounts of
opportunities never realized and people that failed you. So, yes, please list your
accomplishments. It just may get you the help for which you constantly make appeal.

Re: FPGA4th

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Subject: Re: FPGA4th
From: waynemor...@gmail.com (S)
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 by: S - Mon, 24 Oct 2022 03:24 UTC

On Sunday, October 23, 2022 at 9:42:56 AM UTC+10, dxforth wrote:
> On 23/10/2022 2:28 am, S 1 wrote:
> > ...> If you are jealous of people getting it right, maybe you should try being right instead? If you lack innovation, get some or shut up, stop going on like you are a jealous school girl!
>
> So what you have actually accomplished and of which others could rightly be jealous?
> I haven't read all of your posts and it's possible I missed it among the accounts of
> opportunities never realized and people that failed you. So, yes, please list your
> accomplishments. It just may get you the help for which you constantly make appeal.

Unbelievable, you being a pest to people, you haven't read up, don't know what you are talking about, and have achieved nothing but pestering, and shifting around.

Re: FPGA4th

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From: dxfo...@gmail.com (dxforth)
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Subject: Re: FPGA4th
Date: Mon, 24 Oct 2022 16:27:52 +1100
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 by: dxforth - Mon, 24 Oct 2022 05:27 UTC

On 24/10/2022 2:24 pm, S wrote:
> On Sunday, October 23, 2022 at 9:42:56 AM UTC+10, dxforth wrote:
>> On 23/10/2022 2:28 am, S 1 wrote:
>>> ...> If you are jealous of people getting it right, maybe you should try being right instead? If you lack innovation, get some or shut up, stop going on like you are a jealous school girl!
>>
>> So what you have actually accomplished and of which others could rightly be jealous?
>> I haven't read all of your posts and it's possible I missed it among the accounts of
>> opportunities never realized and people that failed you. So, yes, please list your
>> accomplishments. It just may get you the help for which you constantly make appeal.
>
> Unbelievable, you being a pest to people, you haven't read up, don't know what you are talking about, and have achieved nothing but pestering, and shifting around.

I'm not the one selling myself - you are. The question was simple enough. What can
you show people you have practically achieved that would make it worth their while
partnering with you. Your ability to exaggerate your importance isn't in doubt e.g.
offering to bring a thousand new members to c.l.f. What's lacking is evidence you
can bring anything to a conclusion. Even if it's just a series of posts.

Re: FPGA4th

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Subject: Re: FPGA4th
From: johnroge...@gmail.com (John Hart)
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 by: John Hart - Tue, 25 Apr 2023 17:13 UTC

On Thursday, November 25, 2021 at 2:39:20 AM UTC-7, Jurgen Pitaske wrote:
<clip>
> Thank you very much John - let's see what happens next.
> Just for the fun of it I formatted it slightly in a way that makes the blocks a bit clearer to me
> https://www.dropbox.com/sh/ah8umk0hgq1818s/AAC8nNEueZZcIYJ8uGP4F4wPa?dl=0

Finally getting close to finishing the development system and the processor..

The original design was for a FPLD not a FPGA. After we moved the design to a FPGA it became obvious
a major re-design was needed. PLD's are optimized for parallel operations and we were able to convert
forth code directly to logic for the design, but FPGA's require something more complex, so I decided to
build a map generator before beginning the project.

Re: FPGA4th

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Newsgroups: comp.lang.forth
Date: Tue, 25 Apr 2023 10:21:09 -0700 (PDT)
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Subject: Re: FPGA4th
From: jpita...@gmail.com (Jurgen Pitaske)
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 by: Jurgen Pitaske - Tue, 25 Apr 2023 17:21 UTC

On Tuesday, 25 April 2023 at 18:13:11 UTC+1, John Hart wrote:
> On Thursday, November 25, 2021 at 2:39:20 AM UTC-7, Jurgen Pitaske wrote:
> <clip>
> > Thank you very much John - let's see what happens next.
> > Just for the fun of it I formatted it slightly in a way that makes the blocks a bit clearer to me
> > https://www.dropbox.com/sh/ah8umk0hgq1818s/AAC8nNEueZZcIYJ8uGP4F4wPa?dl=0
>
> Finally getting close to finishing the development system and the processor.
>
> The original design was for a FPLD not a FPGA. After we moved the design to a FPGA it became obvious
> a major re-design was needed. PLD's are optimized for parallel operations and we were able to convert
> forth code directly to logic for the design, but FPGA's require something more complex, so I decided to
> build a map generator before beginning the project.

Looking forward to more ...

And I just checked the dropbox link - still works.
I hope the formatting was helpful.

Re: FPGA4th

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Subject: Re: FPGA4th
From: gnuarm.d...@gmail.com (Lorem Ipsum)
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 by: Lorem Ipsum - Wed, 26 Apr 2023 01:23 UTC

On Tuesday, April 25, 2023 at 1:13:11 PM UTC-4, John Hart wrote:
> On Thursday, November 25, 2021 at 2:39:20 AM UTC-7, Jurgen Pitaske wrote:
> <clip>
> > Thank you very much John - let's see what happens next.
> > Just for the fun of it I formatted it slightly in a way that makes the blocks a bit clearer to me
> > https://www.dropbox.com/sh/ah8umk0hgq1818s/AAC8nNEueZZcIYJ8uGP4F4wPa?dl=0
>
> Finally getting close to finishing the development system and the processor.
>
> The original design was for a FPLD not a FPGA. After we moved the design to a FPGA it became obvious
> a major re-design was needed. PLD's are optimized for parallel operations and we were able to convert
> forth code directly to logic for the design, but FPGA's require something more complex, so I decided to
> build a map generator before beginning the project.

What additional complexity do FPGAs require over CPLD? I literally have no idea what that means. You can use the same HDL code that was written for a CPLD (assuming there's a compiler for it) and compile that for an FPGA.

I can't think of anything that is harder to do in an FPGA than in a CPLD, unless CPLDs have something akin to "long lines" which FPGAs used to use, until they grew out of them with logic being faster.

There is nothing about FPGAs to preclude or make harder parallel operations.. FPGAs are the embodiment of parallel operations. Every component on an FPGA operates in parallel with all the others, unless you tie them to sequential operations in your code.

--

Rick C.

---+ Get 1,000 miles of free Supercharging
---+ Tesla referral code - https://ts.la/richard11209

Re: FPGA4th

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Subject: Re: FPGA4th
From: hughagui...@gmail.com (Hugh Aguilar)
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 by: Hugh Aguilar - Wed, 26 Apr 2023 18:07 UTC

On Tuesday, October 11, 2022 at 11:23:30 PM UTC-7, Jurgen Pitaske wrote:
> Just an idea:
> I could convince Steve Teal to write the Minimum RISC in VHDL.
> And as a bonus he added an eForth.
> https://github.com/Steve-Teal/eforth-misc16
>
> How difficult would it be to replicate this design using your tools and Forth as VHDL?
> And use the same FPGA you use now?
>
> This would be a way to show others a full design,
> using standard tools on one side,
> and then compare it with your tools.
> Your tools could then probably more easily show how to add additional IOs..
>
> Thanks again - and can we have more please

Juergen Pintaske assumes that the Testra development tools (including MFX)
are an internet freebie that anybody can download, similar to eForth.
This isn't true though. I wrote MFX in 32-bit UR/Forth under a DOS-extender
in 1994. I was told that Testra had the sign an NDA for Ray Duncan in order to
obtain the UR/Forth source-code. Since that time, Testra has upgraded UR/Forth
to run under Windows, so they could continue to use UR/Forth all the way to 2023.
The NDA is still in effect. Testra can't distribute MFX or any of the other development
tools to anybody who doesn't also sign the NDA for Ray Duncan.

In 1994 I was well aware of the problem with UR/Forth being a dead-end because LMI
(Ray Duncan's company: Laboratory Microsystems Inc.) had been killed by ANS-Forth.
This is why I only wrote a minimal amount of x86 assembly-language that would
required carnal-knowledge of UR/Forth, and I put all of this UR/Forth-specific code in
one file. My expectation was that MFX would later be ported to another Forth compiler
that was still being supported, and only this one small file would need to be rewritten.
Everything else in MFX was Forth-83 or, if it was UR/Forth specific, it didn't use any
carnal-knowledge or x86 assembly so it would be easy enough to port to another Forth.
Testra continues to use UR/Forth though! This is because neither John Hart or Steve Brault
know enough about MFX to port it to another Forth system, and they have never been
able to find any maintenance programmer who could learn MFX either.

On Friday, July 23, 2021 at 1:43:39 AM UTC-7, John Hart wrote:
> Hugh appears to be stuck in a time loop, like Phill Connors in Ground Hogs Day.

John Hart continues to use UR/Forth three decades after LMI went out of business.
John Hart does this so he can keep MFX running decade after decade.
John Hart is stuck in a time loop, like Phil Conners in the movie: "Ground Hog Day."
For John Hart, it will always be 1994 and he will always be running MFX under UR/Forth.
Just like in the movie, every day that John Hart wakes up it is 1994 again and he is running
my MFX under UR/Forth --- this time loop is John Hart's personal hell that never ends.

My recollection of working at Testra is that Tom Hart would show up for an hour or two
every two or three weeks. Tom Hart most likely doesn't know that I wrote MFX or even
know what MFX is. John Hart does know that I wrote MFX. It has been several years now
and John Hart has never admitted on comp.lang.forth that I wrote MFX. John Hart is a liar!
The truth is that I wrote MFX, and his refusal to admit the truth makes him a liar.
I think that John Hart is ashamed of the fact that he didn't know how to write an
assembler/simulator for his MiniForth processor and had to hire outside help to do this.
He has spent the last three decades telling the lie that he and Steve Brault wrote MFX
and now he can't tell the truth because doing so would require him to admit that he lied.

On Friday, July 23, 2021 at 1:43:39 AM UTC-7, John Hart wrote:
> His brother worked for us after he left on the HPGL converter, not Hugh.
> When he complained about it,
> I explained that Tom was confused about that, and thought that would be the end of it.

John Hart is a liar! He has now upgraded to attacking my family members with his filthy lies.
Also, when I visited Testra, John Hart did not explain to me about Tom being confused.
John Hart invented this lie about my brother years later to cover up the lie about me failing
to learn HPGL (I never even heard of HPGL until I got hit with this lie on comp.lang.forth).
Attacking family members is loathsome behavior, even by the low standards of comp.lang.forth..

On Tuesday, April 25, 2023 at 10:13:11 AM UTC-7, John Hart wrote:
> Finally getting close to finishing the development system and the processor.

John Hart is "finally getting close to finishing" in the year 2023. LOL
Using UR/Forth in the year 2023 is like competing in the Indianapolis 500 with a Model-T Ford.
Long after the race is over and all of the spectators have gone home, John Hart is
finally getting close to finishing the race. His Model-T Ford is zooming toward the finish line
at 20 mph! He is still using MFX although he doesn't understand how MFX works, just like a
race-car driver who doesn't understand how the internal-combustion engine works.

Re: FPGA4th

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Subject: Re: FPGA4th
From: johnroge...@gmail.com (John Hart)
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 by: John Hart - Thu, 27 Apr 2023 00:59 UTC

On Tuesday, April 25, 2023 at 6:23:15 PM UTC-7, Lorem Ipsum wrote:
> On Tuesday, April 25, 2023 at 1:13:11 PM UTC-4, John Hart wrote:
> > On Thursday, November 25, 2021 at 2:39:20 AM UTC-7, Jurgen Pitaske wrote:
> > <clip>
<clip>
> > The original design was for a FPLD not a FPGA. After we moved the design to a FPGA it became obvious
> > a major re-design was needed. PLD's are optimized for parallel operations and we were able to convert
> > forth code directly to logic for the design, but FPGA's require something more complex, so I decided to
> > build a map generator before beginning the project.
> What additional complexity do FPGAs require over CPLD? I literally have no idea what that means. You can use the same HDL code that was written for a CPLD (assuming there's a compiler for it) and compile that for an FPGA.
>
> I can't think of anything that is harder to do in an FPGA than in a CPLD, unless CPLDs have something akin to "long lines" which FPGAs used to use, until they grew out of them with logic being faster.
>
> There is nothing about FPGAs to preclude or make harder parallel operations. FPGAs are the embodiment of parallel operations. Every component on an FPGA operates in parallel with all the others, unless you tie them to sequential operations in your code.
> Rick C.
The basic logic unit of a FPGA is a LUT, typically 4 or 5 inputs. The basic logic unit of a CPGA has 16 to 20 inputs.
A 5 input LUT can decode all possible inputs, the basic logic unit of a FPGA, only 4 to 20. A large adder in a CPLD
is next to impossible, in a FPGA a simple task and with carry logic, trivial. The ALU in our Forth CPLD processor was
4 bits. Todays FPGAs outperform CPLDs to the point they're obsolete.

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