novaBBS - comp.lang.forth

On Sunday, 9 October 2022 at 18:51:06 UTC+1, gnuarm.del...@gmail.com wrote:
> On Sunday, October 9, 2022 at 12:50:32 PM UTC-4, jpit...@gmail.com wrote:
> > On Sunday, 9 October 2022 at 09:18:58 UTC+1, Jurgen Pitaske wrote:
> > > On Sunday, 9 October 2022 at 07:37:50 UTC+1, johnro...@gmail.com wrote:
> > > > On Wednesday, January 12, 2022 at 3:35:17 AM UTC-7, jpit...@gmail.com wrote:
> > > > > On Wednesday, 12 January 2022 at 08:01:17 UTC, johnro...@gmail.com wrote:
> > > > > > On Thursday, November 25, 2021 at 2:39:20 AM UTC-7, jpit...@gmail.com wrote:
> > > > > > > On Thursday, 25 November 2021 at 07:06:47 UTC, johnro...@gmail.com wrote:
> > > > > > > > \ Op Code File for MFX. Generated by MAKE-OPS v13
> > > > The Logic Compiler is working and the modules for the processor are done and tested. After the mem interface module is complete we'll be ready to put the design into the fpga. We're using a X02-7000 but the design will work in any equivalent part.
> > > > jrh
> > > Looking forward to it.
> > > Posting and distributing it in different places including facembbok should be easy.
> > >
> > > An idea crossed my mind:
> > > Why not do a presentation during a FIG Zoom?
> > > And this would help with where to post it.
> > > http://www.forth.org/svfig/
> > Just for people who might not know the context:
> >
> > Would it not be nice to use VHDL on an FPGA to write to it directly in Forth.
> > See the link to Testra where it has been done already.
> > http://testra.com/Forth/VHDL.htm
> >
> > And hopefully there is more soon from Testra posted here..
> Sorry, I don't follow. What are you describing by, "use VHDL on an FPGA to write to it directly in Forth"?
>
> If you are talking about a stack CPU, written in VHDL, running on an FPGA, that has been done many, many times, some published, many not published. It would seem to be a trivial exercise.
>
> --
>
> Rick C.
>
> --+ Get 1,000 miles of free Supercharging
> --+ Tesla referral code - https://ts.la/richard11209

You are proving again that you attention span is zero - or is it your reading capability?

Designing logic with the Forth VHDL

1. Write a software simulation of the design.
2. Test the design.
3. Convert the software simulation into a hardware definition.
4. Compile the hardware definition into logic equations.
5. Fit the logic equations into the device.
6. Verify that the logic equations work correctly.
7. Route the signals and assign the I/O pins.
8. Convert the routed design into a fusemap.

In article <990840c6-b5e9-4cf1-9efe-1579f2416a84n@googlegroups.com>,
John Hart <johnrogerhart@gmail.com> wrote:
>On Wednesday, January 12, 2022 at 3:35:17 AM UTC-7, jpit...@gmail.com wrote:
>> On Wednesday, 12 January 2022 at 08:01:17 UTC, johnro...@gmail.com wrote:
>> > On Thursday, November 25, 2021 at 2:39:20 AM UTC-7,
>jpit...@gmail.com wrote:
>> > > On Thursday, 25 November 2021 at 07:06:47 UTC, johnro...@gmail.com wrote:
>> > > > \ Op Code File for MFX. Generated by MAKE-OPS v13
>The Logic Compiler is working and the modules for the processor are done
>and tested. After the mem interface module is complete we'll be ready to
>put the design into the fpga. We're using a X02-7000 but the design will
>work in any equivalent part.
>jrh

Are you the John Hart made famous by Hugh Aguilar?
Welcome to c.l.f, whatever that is the case!

Groetjes Albert
--
"in our communism country Viet Nam, people are forced to be
alive and in the western country like US, people are free to
die from Covid 19 lol" duc ha
albert@spe&ar&c.xs4all.nl &=n http://home.hccnet.nl/a.w.m.van.der.horst

On Sunday, October 9, 2022 at 1:54:54 PM UTC-4, jpit...@gmail.com wrote:
> On Sunday, 9 October 2022 at 18:51:06 UTC+1, gnuarm.del...@gmail.com wrote:
> > On Sunday, October 9, 2022 at 12:50:32 PM UTC-4, jpit...@gmail.com wrote:
> > > On Sunday, 9 October 2022 at 09:18:58 UTC+1, Jurgen Pitaske wrote:
> > > > On Sunday, 9 October 2022 at 07:37:50 UTC+1, johnro...@gmail.com wrote:
> > > > > On Wednesday, January 12, 2022 at 3:35:17 AM UTC-7, jpit...@gmail..com wrote:
> > > > > > On Wednesday, 12 January 2022 at 08:01:17 UTC, johnro...@gmail.com wrote:
> > > > > > > On Thursday, November 25, 2021 at 2:39:20 AM UTC-7, jpit...@gmail.com wrote:
> > > > > > > > On Thursday, 25 November 2021 at 07:06:47 UTC, johnro...@gmail.com wrote:
> > > > > > > > > \ Op Code File for MFX. Generated by MAKE-OPS v13
> > > > > The Logic Compiler is working and the modules for the processor are done and tested. After the mem interface module is complete we'll be ready to put the design into the fpga. We're using a X02-7000 but the design will work in any equivalent part.
> > > > > jrh
> > > > Looking forward to it.
> > > > Posting and distributing it in different places including facembbok should be easy.
> > > >
> > > > An idea crossed my mind:
> > > > Why not do a presentation during a FIG Zoom?
> > > > And this would help with where to post it.
> > > > http://www.forth.org/svfig/
> > > Just for people who might not know the context:
> > >
> > > Would it not be nice to use VHDL on an FPGA to write to it directly in Forth.
> > > See the link to Testra where it has been done already.
> > > http://testra.com/Forth/VHDL.htm
> > >
> > > And hopefully there is more soon from Testra posted here..
> > Sorry, I don't follow. What are you describing by, "use VHDL on an FPGA to write to it directly in Forth"?
> >
> > If you are talking about a stack CPU, written in VHDL, running on an FPGA, that has been done many, many times, some published, many not published.. It would seem to be a trivial exercise.
> >
> > --
> >
> > Rick C.
> >
> > --+ Get 1,000 miles of free Supercharging
> > --+ Tesla referral code - https://ts.la/richard11209
> You are proving again that you attention span is zero - or is it your reading capability?
>
> Designing logic with the Forth VHDL
>
> 1. Write a software simulation of the design.
> 2. Test the design.
> 3. Convert the software simulation into a hardware definition.
> 4. Compile the hardware definition into logic equations.
> 5. Fit the logic equations into the device.
> 6. Verify that the logic equations work correctly.
> 7. Route the signals and assign the I/O pins.
> 8. Convert the routed design into a fusemap.

"Forth VHDL"??? You are talking about a VHDL synthesis tool written in Forth??? No, that doesn't fit the description of what is going on. In fact, your description doesn't seem to relate to VHDL at all.

I can't tell what you are talking about from this description, but it sounds like it is for CPLDs, rather than FPGAs. Maybe we are hitting a language barrier.

Rick C.

-+- Get 1,000 miles of free Supercharging
-+- Tesla referral code - https://ts.la/richard11209

On Sunday, 9 October 2022 at 20:15:22 UTC+1, gnuarm.del...@gmail.com wrote:
> On Sunday, October 9, 2022 at 1:54:54 PM UTC-4, jpit...@gmail.com wrote:
> > On Sunday, 9 October 2022 at 18:51:06 UTC+1, gnuarm.del...@gmail.com wrote:
> > > On Sunday, October 9, 2022 at 12:50:32 PM UTC-4, jpit...@gmail.com wrote:
> > > > On Sunday, 9 October 2022 at 09:18:58 UTC+1, Jurgen Pitaske wrote:
> > > > > On Sunday, 9 October 2022 at 07:37:50 UTC+1, johnro...@gmail.com wrote:
> > > > > > On Wednesday, January 12, 2022 at 3:35:17 AM UTC-7, jpit...@gmail.com wrote:
> > > > > > > On Wednesday, 12 January 2022 at 08:01:17 UTC, johnro...@gmail.com wrote:
> > > > > > > > On Thursday, November 25, 2021 at 2:39:20 AM UTC-7, jpit...@gmail.com wrote:
> > > > > > > > > On Thursday, 25 November 2021 at 07:06:47 UTC, johnro...@gmail.com wrote:
> > > > > > > > > > \ Op Code File for MFX. Generated by MAKE-OPS v13
> > > > > > The Logic Compiler is working and the modules for the processor are done and tested. After the mem interface module is complete we'll be ready to put the design into the fpga. We're using a X02-7000 but the design will work in any equivalent part.
> > > > > > jrh
> > > > > Looking forward to it.
> > > > > Posting and distributing it in different places including facembbok should be easy.
> > > > >
> > > > > An idea crossed my mind:
> > > > > Why not do a presentation during a FIG Zoom?
> > > > > And this would help with where to post it.
> > > > > http://www.forth.org/svfig/
> > > > Just for people who might not know the context:
> > > >
> > > > Would it not be nice to use VHDL on an FPGA to write to it directly in Forth.
> > > > See the link to Testra where it has been done already.
> > > > http://testra.com/Forth/VHDL.htm
> > > >
> > > > And hopefully there is more soon from Testra posted here..
> > > Sorry, I don't follow. What are you describing by, "use VHDL on an FPGA to write to it directly in Forth"?
> > >
> > > If you are talking about a stack CPU, written in VHDL, running on an FPGA, that has been done many, many times, some published, many not published. It would seem to be a trivial exercise.
> > >
> > > --
> > >
> > > Rick C.
> > >
> > > --+ Get 1,000 miles of free Supercharging
> > > --+ Tesla referral code - https://ts.la/richard11209
> > You are proving again that you attention span is zero - or is it your reading capability?
> >
> > Designing logic with the Forth VHDL
> >
> > 1. Write a software simulation of the design.
> > 2. Test the design.
> > 3. Convert the software simulation into a hardware definition.
> > 4. Compile the hardware definition into logic equations.
> > 5. Fit the logic equations into the device.
> > 6. Verify that the logic equations work correctly.
> > 7. Route the signals and assign the I/O pins.
> > 8. Convert the routed design into a fusemap.
> "Forth VHDL"??? You are talking about a VHDL synthesis tool written in Forth??? No, that doesn't fit the description of what is going on. In fact, your description doesn't seem to relate to VHDL at all.
>
> I can't tell what you are talking about from this description,
> but it sounds like it is for CPLDs, rather than FPGAs.
Maybe we are hitting a language barrier.
>
> --
>
> Rick C.
>
> -+- Get 1,000 miles of free Supercharging
> -+- Tesla referral code - https://ts.la/richard11209

The linfo at Testra clearly states:

Using Forth as a VHDL ( Virtual Hardware Definition Language )
John R. Hart, Testra Corporation

They used it on a CPLD first, and on a Lattice FPGA 7k now.
Hugh Aguilar was involved there.

And with all of the knowledge and experience here or elsewhere
it could probably be ported to
other FPGA families.

You have all of the advantages of Forth,
and no need for the overhead of FPGA tools as I understand.

I am surprised this has not been of interest for the last many years,
as the info on the Testra website was always there.

But now we hopefully get the opportunity to see a full example.

On Monday, 10 October 2022 at 07:23:05 UTC+1, Jurgen Pitaske wrote:
> On Sunday, 9 October 2022 at 20:15:22 UTC+1, gnuarm.del...@gmail.com wrote:
> > On Sunday, October 9, 2022 at 1:54:54 PM UTC-4, jpit...@gmail.com wrote:
> > > On Sunday, 9 October 2022 at 18:51:06 UTC+1, gnuarm.del...@gmail.com wrote:
> > > > On Sunday, October 9, 2022 at 12:50:32 PM UTC-4, jpit...@gmail.com wrote:
> > > > > On Sunday, 9 October 2022 at 09:18:58 UTC+1, Jurgen Pitaske wrote:
> > > > > > On Sunday, 9 October 2022 at 07:37:50 UTC+1, johnro...@gmail.com wrote:
> > > > > > > On Wednesday, January 12, 2022 at 3:35:17 AM UTC-7, jpit...@gmail.com wrote:
> > > > > > > > On Wednesday, 12 January 2022 at 08:01:17 UTC, johnro...@gmail.com wrote:
> > > > > > > > > On Thursday, November 25, 2021 at 2:39:20 AM UTC-7, jpit....@gmail.com wrote:
> > > > > > > > > > On Thursday, 25 November 2021 at 07:06:47 UTC, johnro....@gmail.com wrote:
> > > > > > > > > > > \ Op Code File for MFX. Generated by MAKE-OPS v13
> > > > > > > The Logic Compiler is working and the modules for the processor are done and tested. After the mem interface module is complete we'll be ready to put the design into the fpga. We're using a X02-7000 but the design will work in any equivalent part.
> > > > > > > jrh
> > > > > > Looking forward to it.
> > > > > > Posting and distributing it in different places including facembbok should be easy.
> > > > > >
> > > > > > An idea crossed my mind:
> > > > > > Why not do a presentation during a FIG Zoom?
> > > > > > And this would help with where to post it.
> > > > > > http://www.forth.org/svfig/
> > > > > Just for people who might not know the context:
> > > > >
> > > > > Would it not be nice to use VHDL on an FPGA to write to it directly in Forth.
> > > > > See the link to Testra where it has been done already.
> > > > > http://testra.com/Forth/VHDL.htm
> > > > >
> > > > > And hopefully there is more soon from Testra posted here..
> > > > Sorry, I don't follow. What are you describing by, "use VHDL on an FPGA to write to it directly in Forth"?
> > > >
> > > > If you are talking about a stack CPU, written in VHDL, running on an FPGA, that has been done many, many times, some published, many not published. It would seem to be a trivial exercise.
> > > >
> > > > --
> > > >
> > > > Rick C.
> > > >
> > > > --+ Get 1,000 miles of free Supercharging
> > > > --+ Tesla referral code - https://ts.la/richard11209
> > > You are proving again that you attention span is zero - or is it your reading capability?
> > >
> > > Designing logic with the Forth VHDL
> > >
> > > 1. Write a software simulation of the design.
> > > 2. Test the design.
> > > 3. Convert the software simulation into a hardware definition.
> > > 4. Compile the hardware definition into logic equations.
> > > 5. Fit the logic equations into the device.
> > > 6. Verify that the logic equations work correctly.
> > > 7. Route the signals and assign the I/O pins.
> > > 8. Convert the routed design into a fusemap.
> > "Forth VHDL"??? You are talking about a VHDL synthesis tool written in Forth??? No, that doesn't fit the description of what is going on. In fact, your description doesn't seem to relate to VHDL at all.
> >
> > I can't tell what you are talking about from this description,
> > but it sounds like it is for CPLDs, rather than FPGAs.
> Maybe we are hitting a language barrier.
> >
> > --
> >
> > Rick C.
> >
> > -+- Get 1,000 miles of free Supercharging
> > -+- Tesla referral code - https://ts.la/richard11209
> The linfo at Testra clearly states:
>
> Using Forth as a VHDL ( Virtual Hardware Definition Language )
> John R. Hart, Testra Corporation
>
> They used it on a CPLD first, and on a Lattice FPGA 7k now.
> Hugh Aguilar was involved there.
>
> And with all of the knowledge and experience here or elsewhere
> it could probably be ported to
> other FPGA families.
>
> You have all of the advantages of Forth,
> and no need for the overhead of FPGA tools as I understand.
>
> I am surprised this has not been of interest for the last many years,
> as the info on the Testra website was always there.
>
> But now we hopefully get the opportunity to see a full example.

Any language can probably be used, not just Forth - see C to HDL
https://en.wikipedia.org/wiki/C_to_HDL
I actually met Ian Page when he was part of our customer Celoxica, then ESL..

Reminded me of an article I wrote probably 20 years ago
https://www.design-reuse.com/articles/7656/fast-route-from-system-specification-to-implementation.html

I would love to this Minimum RISC as example for this Forth to Gates route
https://homepage.cs.uiowa.edu/~jones/arch/risc/
I could convince Steve Teal to write it in VHDL.
And he adapted an eForth to it.
But having the Minimum RISC written in Forth as VHDL would be even more interesting.

Re: FPGA4th

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by: Lorem Ipsum - Mon, 10 Oct 2022 07:35 UTC

On Monday, October 10, 2022 at 2:23:05 AM UTC-4, jpit...@gmail.com wrote:
> On Sunday, 9 October 2022 at 20:15:22 UTC+1, gnuarm.del...@gmail.com wrote:
> > On Sunday, October 9, 2022 at 1:54:54 PM UTC-4, jpit...@gmail.com wrote:
> > > On Sunday, 9 October 2022 at 18:51:06 UTC+1, gnuarm.del...@gmail.com wrote:
> > > > On Sunday, October 9, 2022 at 12:50:32 PM UTC-4, jpit...@gmail.com wrote:
> > > > > On Sunday, 9 October 2022 at 09:18:58 UTC+1, Jurgen Pitaske wrote:
> > > > > > On Sunday, 9 October 2022 at 07:37:50 UTC+1, johnro...@gmail.com wrote:
> > > > > > > On Wednesday, January 12, 2022 at 3:35:17 AM UTC-7, jpit...@gmail.com wrote:
> > > > > > > > On Wednesday, 12 January 2022 at 08:01:17 UTC, johnro...@gmail.com wrote:
> > > > > > > > > On Thursday, November 25, 2021 at 2:39:20 AM UTC-7, jpit....@gmail.com wrote:
> > > > > > > > > > On Thursday, 25 November 2021 at 07:06:47 UTC, johnro....@gmail.com wrote:
> > > > > > > > > > > \ Op Code File for MFX. Generated by MAKE-OPS v13
> > > > > > > The Logic Compiler is working and the modules for the processor are done and tested. After the mem interface module is complete we'll be ready to put the design into the fpga. We're using a X02-7000 but the design will work in any equivalent part.
> > > > > > > jrh
> > > > > > Looking forward to it.
> > > > > > Posting and distributing it in different places including facembbok should be easy.
> > > > > >
> > > > > > An idea crossed my mind:
> > > > > > Why not do a presentation during a FIG Zoom?
> > > > > > And this would help with where to post it.
> > > > > > http://www.forth.org/svfig/
> > > > > Just for people who might not know the context:
> > > > >
> > > > > Would it not be nice to use VHDL on an FPGA to write to it directly in Forth.
> > > > > See the link to Testra where it has been done already.
> > > > > http://testra.com/Forth/VHDL.htm
> > > > >
> > > > > And hopefully there is more soon from Testra posted here..
> > > > Sorry, I don't follow. What are you describing by, "use VHDL on an FPGA to write to it directly in Forth"?
> > > >
> > > > If you are talking about a stack CPU, written in VHDL, running on an FPGA, that has been done many, many times, some published, many not published. It would seem to be a trivial exercise.
> > > >
> > > > --
> > > >
> > > > Rick C.
> > > >
> > > > --+ Get 1,000 miles of free Supercharging
> > > > --+ Tesla referral code - https://ts.la/richard11209
> > > You are proving again that you attention span is zero - or is it your reading capability?
> > >
> > > Designing logic with the Forth VHDL
> > >
> > > 1. Write a software simulation of the design.
> > > 2. Test the design.
> > > 3. Convert the software simulation into a hardware definition.
> > > 4. Compile the hardware definition into logic equations.
> > > 5. Fit the logic equations into the device.
> > > 6. Verify that the logic equations work correctly.
> > > 7. Route the signals and assign the I/O pins.
> > > 8. Convert the routed design into a fusemap.
> > "Forth VHDL"??? You are talking about a VHDL synthesis tool written in Forth??? No, that doesn't fit the description of what is going on. In fact, your description doesn't seem to relate to VHDL at all.
> >
> > I can't tell what you are talking about from this description,
> > but it sounds like it is for CPLDs, rather than FPGAs.
> Maybe we are hitting a language barrier.
> >
> > --
> >
> > Rick C.
> >
> > -+- Get 1,000 miles of free Supercharging
> > -+- Tesla referral code - https://ts.la/richard11209
> The linfo at Testra clearly states:
>
> Using Forth as a VHDL ( Virtual Hardware Definition Language )
> John R. Hart, Testra Corporation

Ah, so he's bastardizing the term VHDL. That's normally used as the name of a language for programming digital logic (VHSIC Hardware Description Language).

> They used it on a CPLD first, and on a Lattice FPGA 7k now.
> Hugh Aguilar was involved there.
>
> And with all of the knowledge and experience here or elsewhere
> it could probably be ported to
> other FPGA families.
>
> You have all of the advantages of Forth,
> and no need for the overhead of FPGA tools as I understand.

It's not quite that simple. To target an FPGA device, you have to know the bitstream format. The vendors don't typically provide that information. Some people have reverse engineered a very few of the Lattice parts. I was not aware that the X02-7000 had been reverse engineered, but it's possible.. Figuring out the bit map for other devices is not at all simple. It's tons of work.

> I am surprised this has not been of interest for the last many years,
> as the info on the Testra website was always there.

Open source tools have been of interest and exist. But not for many parts, for the reasons I've explained.

> But now we hopefully get the opportunity to see a full example.

"Full example"???

It's a tool of little value in the FPGA world. Homebrew amateurs may find it interesting, but the FPGA world will simply yawn.

I don't know how accurate your list of steps in using the tool is, but it sounds to me like a lot more work than the use of typical FPGA tools. Here's the steps required for designing FPGAs.

1. Write the design in VHDL or Verilog
2. Write a test bench for the simulation stimulus and error checking.
3. Simulate the design using conventional simulators.
4. Synthesize the design for the target chip.
5. Test on the target board.

Done. The only "writing" of code is the design and the test bench for simulation. Everything else is a working tool.

Rick C.

-++ Get 1,000 miles of free Supercharging
-++ Tesla referral code - https://ts.la/richard11209

On Monday, 10 October 2022 at 08:35:40 UTC+1, gnuarm.del...@gmail.com wrote:
> On Monday, October 10, 2022 at 2:23:05 AM UTC-4, jpit...@gmail.com wrote:
> > On Sunday, 9 October 2022 at 20:15:22 UTC+1, gnuarm.del...@gmail.com wrote:
> > > On Sunday, October 9, 2022 at 1:54:54 PM UTC-4, jpit...@gmail.com wrote:
> > > > On Sunday, 9 October 2022 at 18:51:06 UTC+1, gnuarm.del...@gmail.com wrote:
> > > > > On Sunday, October 9, 2022 at 12:50:32 PM UTC-4, jpit...@gmail.com wrote:
> > > > > > On Sunday, 9 October 2022 at 09:18:58 UTC+1, Jurgen Pitaske wrote:
> > > > > > > On Sunday, 9 October 2022 at 07:37:50 UTC+1, johnro...@gmail.com wrote:
> > > > > > > > On Wednesday, January 12, 2022 at 3:35:17 AM UTC-7, jpit...@gmail.com wrote:
> > > > > > > > > On Wednesday, 12 January 2022 at 08:01:17 UTC, johnro...@gmail.com wrote:
> > > > > > > > > > On Thursday, November 25, 2021 at 2:39:20 AM UTC-7, jpit...@gmail.com wrote:
> > > > > > > > > > > On Thursday, 25 November 2021 at 07:06:47 UTC, johnro....@gmail.com wrote:
> > > > > > > > > > > > \ Op Code File for MFX. Generated by MAKE-OPS v13
> > > > > > > > The Logic Compiler is working and the modules for the processor are done and tested. After the mem interface module is complete we'll be ready to put the design into the fpga. We're using a X02-7000 but the design will work in any equivalent part.
> > > > > > > > jrh
> > > > > > > Looking forward to it.
> > > > > > > Posting and distributing it in different places including facembbok should be easy.
> > > > > > >
> > > > > > > An idea crossed my mind:
> > > > > > > Why not do a presentation during a FIG Zoom?
> > > > > > > And this would help with where to post it.
> > > > > > > http://www.forth.org/svfig/
> > > > > > Just for people who might not know the context:
> > > > > >
> > > > > > Would it not be nice to use VHDL on an FPGA to write to it directly in Forth.
> > > > > > See the link to Testra where it has been done already.
> > > > > > http://testra.com/Forth/VHDL.htm
> > > > > >
> > > > > > And hopefully there is more soon from Testra posted here..
> > > > > Sorry, I don't follow. What are you describing by, "use VHDL on an FPGA to write to it directly in Forth"?
> > > > >
> > > > > If you are talking about a stack CPU, written in VHDL, running on an FPGA, that has been done many, many times, some published, many not published. It would seem to be a trivial exercise.
> > > > >
> > > > > --
> > > > >
> > > > > Rick C.
> > > > >
> > > > > --+ Get 1,000 miles of free Supercharging
> > > > > --+ Tesla referral code - https://ts.la/richard11209
> > > > You are proving again that you attention span is zero - or is it your reading capability?
> > > >
> > > > Designing logic with the Forth VHDL
> > > >
> > > > 1. Write a software simulation of the design.
> > > > 2. Test the design.
> > > > 3. Convert the software simulation into a hardware definition.
> > > > 4. Compile the hardware definition into logic equations.
> > > > 5. Fit the logic equations into the device.
> > > > 6. Verify that the logic equations work correctly.
> > > > 7. Route the signals and assign the I/O pins.
> > > > 8. Convert the routed design into a fusemap.
> > > "Forth VHDL"??? You are talking about a VHDL synthesis tool written in Forth??? No, that doesn't fit the description of what is going on. In fact, your description doesn't seem to relate to VHDL at all.
> > >
> > > I can't tell what you are talking about from this description,
> > > but it sounds like it is for CPLDs, rather than FPGAs.
> > Maybe we are hitting a language barrier.
> > >
> > > --
> > >
> > > Rick C.
> > >
> > > -+- Get 1,000 miles of free Supercharging
> > > -+- Tesla referral code - https://ts.la/richard11209
> > The linfo at Testra clearly states:
> >
> > Using Forth as a VHDL ( Virtual Hardware Definition Language )
> > John R. Hart, Testra Corporation
> Ah, so he's bastardizing the term VHDL. That's normally used as the name of a language for programming digital logic (VHSIC Hardware Description Language).
> > They used it on a CPLD first, and on a Lattice FPGA 7k now.
> > Hugh Aguilar was involved there.
> >
> > And with all of the knowledge and experience here or elsewhere
> > it could probably be ported to
> > other FPGA families.
> >
> > You have all of the advantages of Forth,
> > and no need for the overhead of FPGA tools as I understand.
> It's not quite that simple. To target an FPGA device, you have to know the bitstream format. The vendors don't typically provide that information. Some people have reverse engineered a very few of the Lattice parts. I was not aware that the X02-7000 had been reverse engineered, but it's possible. Figuring out the bit map for other devices is not at all simple. It's tons of work.
> > I am surprised this has not been of interest for the last many years,
> > as the info on the Testra website was always there.
> Open source tools have been of interest and exist. But not for many parts, for the reasons I've explained.
> > But now we hopefully get the opportunity to see a full example.
> "Full example"???
>
> It's a tool of little value in the FPGA world. Homebrew amateurs may find it interesting, but the FPGA world will simply yawn.
>
> I don't know how accurate your list of steps in using the tool is, but it sounds to me like a lot more work than the use of typical FPGA tools. Here's the steps required for designing FPGAs.
>
> 1. Write the design in VHDL or Verilog
> 2. Write a test bench for the simulation stimulus and error checking.
> 3. Simulate the design using conventional simulators.
> 4. Synthesize the design for the target chip.
> 5. Test on the target board.
>
> Done. The only "writing" of code is the design and the test bench for simulation. Everything else is a working tool.
>
> --
>
> Rick C.
>
> -++ Get 1,000 miles of free Supercharging
> -++ Tesla referral code - https://ts.la/richard11209

I am sorry, but your post does not make sense to me.

Testra use this setup for many years in their products
and it must make sense there,
otherwise they would just use the standard Lattice tools.

If it is not relevant to you - fine - I never asked you.
Just like asking an experienced C programmer - why not Forth ...

Re: FPGA4th

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Subject: Re: FPGA4th
From: gnuarm.d...@gmail.com (Lorem Ipsum)
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by: Lorem Ipsum - Mon, 10 Oct 2022 15:52 UTC

On Monday, October 10, 2022 at 11:19:41 AM UTC-4, jpit...@gmail.com wrote:
> On Monday, 10 October 2022 at 08:35:40 UTC+1, gnuarm.del...@gmail.com wrote:
> > On Monday, October 10, 2022 at 2:23:05 AM UTC-4, jpit...@gmail.com wrote:
> > > On Sunday, 9 October 2022 at 20:15:22 UTC+1, gnuarm.del...@gmail.com wrote:
> > > > On Sunday, October 9, 2022 at 1:54:54 PM UTC-4, jpit...@gmail.com wrote:
> > > > > On Sunday, 9 October 2022 at 18:51:06 UTC+1, gnuarm.del...@gmail.com wrote:
> > > > > > On Sunday, October 9, 2022 at 12:50:32 PM UTC-4, jpit...@gmail.com wrote:
> > > > > > > On Sunday, 9 October 2022 at 09:18:58 UTC+1, Jurgen Pitaske wrote:
> > > > > > > > On Sunday, 9 October 2022 at 07:37:50 UTC+1, johnro...@gmail.com wrote:
> > > > > > > > > On Wednesday, January 12, 2022 at 3:35:17 AM UTC-7, jpit....@gmail.com wrote:
> > > > > > > > > > On Wednesday, 12 January 2022 at 08:01:17 UTC, johnro....@gmail.com wrote:
> > > > > > > > > > > On Thursday, November 25, 2021 at 2:39:20 AM UTC-7, jpit...@gmail.com wrote:
> > > > > > > > > > > > On Thursday, 25 November 2021 at 07:06:47 UTC, johnro...@gmail.com wrote:
> > > > > > > > > > > > > \ Op Code File for MFX. Generated by MAKE-OPS v13
> > > > > > > > > The Logic Compiler is working and the modules for the processor are done and tested. After the mem interface module is complete we'll be ready to put the design into the fpga. We're using a X02-7000 but the design will work in any equivalent part.
> > > > > > > > > jrh
> > > > > > > > Looking forward to it.
> > > > > > > > Posting and distributing it in different places including facembbok should be easy.
> > > > > > > >
> > > > > > > > An idea crossed my mind:
> > > > > > > > Why not do a presentation during a FIG Zoom?
> > > > > > > > And this would help with where to post it.
> > > > > > > > http://www.forth.org/svfig/
> > > > > > > Just for people who might not know the context:
> > > > > > >
> > > > > > > Would it not be nice to use VHDL on an FPGA to write to it directly in Forth.
> > > > > > > See the link to Testra where it has been done already.
> > > > > > > http://testra.com/Forth/VHDL.htm
> > > > > > >
> > > > > > > And hopefully there is more soon from Testra posted here..
> > > > > > Sorry, I don't follow. What are you describing by, "use VHDL on an FPGA to write to it directly in Forth"?
> > > > > >
> > > > > > If you are talking about a stack CPU, written in VHDL, running on an FPGA, that has been done many, many times, some published, many not published. It would seem to be a trivial exercise.
> > > > > >
> > > > > > --
> > > > > >
> > > > > > Rick C.
> > > > > >
> > > > > > --+ Get 1,000 miles of free Supercharging
> > > > > > --+ Tesla referral code - https://ts.la/richard11209
> > > > > You are proving again that you attention span is zero - or is it your reading capability?
> > > > >
> > > > > Designing logic with the Forth VHDL
> > > > >
> > > > > 1. Write a software simulation of the design.
> > > > > 2. Test the design.
> > > > > 3. Convert the software simulation into a hardware definition.
> > > > > 4. Compile the hardware definition into logic equations.
> > > > > 5. Fit the logic equations into the device.
> > > > > 6. Verify that the logic equations work correctly.
> > > > > 7. Route the signals and assign the I/O pins.
> > > > > 8. Convert the routed design into a fusemap.
> > > > "Forth VHDL"??? You are talking about a VHDL synthesis tool written in Forth??? No, that doesn't fit the description of what is going on. In fact, your description doesn't seem to relate to VHDL at all.
> > > >
> > > > I can't tell what you are talking about from this description,
> > > > but it sounds like it is for CPLDs, rather than FPGAs.
> > > Maybe we are hitting a language barrier.
> > > >
> > > > --
> > > >
> > > > Rick C.
> > > >
> > > > -+- Get 1,000 miles of free Supercharging
> > > > -+- Tesla referral code - https://ts.la/richard11209
> > > The linfo at Testra clearly states:
> > >
> > > Using Forth as a VHDL ( Virtual Hardware Definition Language )
> > > John R. Hart, Testra Corporation
> > Ah, so he's bastardizing the term VHDL. That's normally used as the name of a language for programming digital logic (VHSIC Hardware Description Language).
> > > They used it on a CPLD first, and on a Lattice FPGA 7k now.
> > > Hugh Aguilar was involved there.
> > >
> > > And with all of the knowledge and experience here or elsewhere
> > > it could probably be ported to
> > > other FPGA families.
> > >
> > > You have all of the advantages of Forth,
> > > and no need for the overhead of FPGA tools as I understand.
> > It's not quite that simple. To target an FPGA device, you have to know the bitstream format. The vendors don't typically provide that information. Some people have reverse engineered a very few of the Lattice parts. I was not aware that the X02-7000 had been reverse engineered, but it's possible.. Figuring out the bit map for other devices is not at all simple. It's tons of work.
> > > I am surprised this has not been of interest for the last many years,
> > > as the info on the Testra website was always there.
> > Open source tools have been of interest and exist. But not for many parts, for the reasons I've explained.
> > > But now we hopefully get the opportunity to see a full example.
> > "Full example"???
> >
> > It's a tool of little value in the FPGA world. Homebrew amateurs may find it interesting, but the FPGA world will simply yawn.
> >
> > I don't know how accurate your list of steps in using the tool is, but it sounds to me like a lot more work than the use of typical FPGA tools. Here's the steps required for designing FPGAs.
> >
> > 1. Write the design in VHDL or Verilog
> > 2. Write a test bench for the simulation stimulus and error checking.
> > 3. Simulate the design using conventional simulators.
> > 4. Synthesize the design for the target chip.
> > 5. Test on the target board.
> >
> > Done. The only "writing" of code is the design and the test bench for simulation. Everything else is a working tool.
> >
> > --
> >
> > Rick C.
> >
> > -++ Get 1,000 miles of free Supercharging
> > -++ Tesla referral code - https://ts.la/richard11209
> I am sorry, but your post does not make sense to me.
>
> Testra use this setup for many years in their products
> and it must make sense there,
> otherwise they would just use the standard Lattice tools.
>
> If it is not relevant to you - fine - I never asked you.
> Just like asking an experienced C programmer - why not Forth ...

LOL Yes, if one guy working in a corner of the room is using it, then it must be not only good, but GREAT!

The millions of users of VHDL and Verilog must have it wrong.

One of my early jobs involved designing a microprogrammed DMA controller using an off the shelf sequencer chip. The other, similar designs in the company all used the same assembler tool. I added a few macros and opcodes, in order to give my design additional self-test capabilities. One of the managers said that was a bad idea because no one else would know how to use this "different" tool. I realized that there are many times when standardization is preferred over technical advantages, because technical advantages are of no use if they make the design hard to work with or modify.

In this case, there is no real utility to this "special" design process and it actually appears to be much more complex and difficult to use.

Thank you for the information.

Rick C.

+-- Get 1,000 miles of free Supercharging
+-- Tesla referral code - https://ts.la/richard11209

Re: FPGA4th

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Subject: Re: FPGA4th
From: jpita...@gmail.com (Jurgen Pitaske)
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by: Jurgen Pitaske - Tue, 11 Oct 2022 13:54 UTC

On Monday, 10 October 2022 at 16:52:33 UTC+1, gnuarm.del...@gmail.com wrote:
> On Monday, October 10, 2022 at 11:19:41 AM UTC-4, jpit...@gmail.com wrote:
> > On Monday, 10 October 2022 at 08:35:40 UTC+1, gnuarm.del...@gmail.com wrote:
> > > On Monday, October 10, 2022 at 2:23:05 AM UTC-4, jpit...@gmail.com wrote:
> > > > On Sunday, 9 October 2022 at 20:15:22 UTC+1, gnuarm.del...@gmail.com wrote:
> > > > > On Sunday, October 9, 2022 at 1:54:54 PM UTC-4, jpit...@gmail.com wrote:
> > > > > > On Sunday, 9 October 2022 at 18:51:06 UTC+1, gnuarm.del...@gmail.com wrote:
> > > > > > > On Sunday, October 9, 2022 at 12:50:32 PM UTC-4, jpit...@gmail.com wrote:
> > > > > > > > On Sunday, 9 October 2022 at 09:18:58 UTC+1, Jurgen Pitaske wrote:
> > > > > > > > > On Sunday, 9 October 2022 at 07:37:50 UTC+1, johnro...@gmail.com wrote:
> > > > > > > > > > On Wednesday, January 12, 2022 at 3:35:17 AM UTC-7, jpit...@gmail.com wrote:
> > > > > > > > > > > On Wednesday, 12 January 2022 at 08:01:17 UTC, johnro....@gmail.com wrote:
> > > > > > > > > > > > On Thursday, November 25, 2021 at 2:39:20 AM UTC-7, jpit...@gmail.com wrote:
> > > > > > > > > > > > > On Thursday, 25 November 2021 at 07:06:47 UTC, johnro...@gmail.com wrote:
> > > > > > > > > > > > > > \ Op Code File for MFX. Generated by MAKE-OPS v13
> > > > > > > > > > The Logic Compiler is working and the modules for the processor are done and tested. After the mem interface module is complete we'll be ready to put the design into the fpga. We're using a X02-7000 but the design will work in any equivalent part.
> > > > > > > > > > jrh
> > > > > > > > > Looking forward to it.
> > > > > > > > > Posting and distributing it in different places including facembbok should be easy.
> > > > > > > > >
> > > > > > > > > An idea crossed my mind:
> > > > > > > > > Why not do a presentation during a FIG Zoom?
> > > > > > > > > And this would help with where to post it.
> > > > > > > > > http://www.forth.org/svfig/
> > > > > > > > Just for people who might not know the context:
> > > > > > > >
> > > > > > > > Would it not be nice to use VHDL on an FPGA to write to it directly in Forth.
> > > > > > > > See the link to Testra where it has been done already.
> > > > > > > > http://testra.com/Forth/VHDL.htm
> > > > > > > >
> > > > > > > > And hopefully there is more soon from Testra posted here..
> > > > > > > Sorry, I don't follow. What are you describing by, "use VHDL on an FPGA to write to it directly in Forth"?
> > > > > > >
> > > > > > > If you are talking about a stack CPU, written in VHDL, running on an FPGA, that has been done many, many times, some published, many not published. It would seem to be a trivial exercise.
> > > > > > >
> > > > > > > --
> > > > > > >
> > > > > > > Rick C.
> > > > > > >
> > > > > > > --+ Get 1,000 miles of free Supercharging
> > > > > > > --+ Tesla referral code - https://ts.la/richard11209
> > > > > > You are proving again that you attention span is zero - or is it your reading capability?
> > > > > >
> > > > > > Designing logic with the Forth VHDL
> > > > > >
> > > > > > 1. Write a software simulation of the design.
> > > > > > 2. Test the design.
> > > > > > 3. Convert the software simulation into a hardware definition.
> > > > > > 4. Compile the hardware definition into logic equations.
> > > > > > 5. Fit the logic equations into the device.
> > > > > > 6. Verify that the logic equations work correctly.
> > > > > > 7. Route the signals and assign the I/O pins.
> > > > > > 8. Convert the routed design into a fusemap.
> > > > > "Forth VHDL"??? You are talking about a VHDL synthesis tool written in Forth??? No, that doesn't fit the description of what is going on. In fact, your description doesn't seem to relate to VHDL at all.
> > > > >
> > > > > I can't tell what you are talking about from this description,
> > > > > but it sounds like it is for CPLDs, rather than FPGAs.
> > > > Maybe we are hitting a language barrier.
> > > > >
> > > > > --
> > > > >
> > > > > Rick C.
> > > > >
> > > > > -+- Get 1,000 miles of free Supercharging
> > > > > -+- Tesla referral code - https://ts.la/richard11209
> > > > The linfo at Testra clearly states:
> > > >
> > > > Using Forth as a VHDL ( Virtual Hardware Definition Language )
> > > > John R. Hart, Testra Corporation
> > > Ah, so he's bastardizing the term VHDL. That's normally used as the name of a language for programming digital logic (VHSIC Hardware Description Language).
> > > > They used it on a CPLD first, and on a Lattice FPGA 7k now.
> > > > Hugh Aguilar was involved there.
> > > >
> > > > And with all of the knowledge and experience here or elsewhere
> > > > it could probably be ported to
> > > > other FPGA families.
> > > >
> > > > You have all of the advantages of Forth,
> > > > and no need for the overhead of FPGA tools as I understand.
> > > It's not quite that simple. To target an FPGA device, you have to know the bitstream format. The vendors don't typically provide that information. Some people have reverse engineered a very few of the Lattice parts. I was not aware that the X02-7000 had been reverse engineered, but it's possible. Figuring out the bit map for other devices is not at all simple. It's tons of work.
> > > > I am surprised this has not been of interest for the last many years,
> > > > as the info on the Testra website was always there.
> > > Open source tools have been of interest and exist. But not for many parts, for the reasons I've explained.
> > > > But now we hopefully get the opportunity to see a full example.
> > > "Full example"???
> > >
> > > It's a tool of little value in the FPGA world. Homebrew amateurs may find it interesting, but the FPGA world will simply yawn.
> > >
> > > I don't know how accurate your list of steps in using the tool is, but it sounds to me like a lot more work than the use of typical FPGA tools. Here's the steps required for designing FPGAs.
> > >
> > > 1. Write the design in VHDL or Verilog
> > > 2. Write a test bench for the simulation stimulus and error checking.
> > > 3. Simulate the design using conventional simulators.
> > > 4. Synthesize the design for the target chip.
> > > 5. Test on the target board.
> > >
> > > Done. The only "writing" of code is the design and the test bench for simulation. Everything else is a working tool.
> > >
> > > --
> > >
> > > Rick C.
> > >
> > > -++ Get 1,000 miles of free Supercharging
> > > -++ Tesla referral code - https://ts.la/richard11209
> > I am sorry, but your post does not make sense to me.
> >
> > Testra use this setup for many years in their products
> > and it must make sense there,
> > otherwise they would just use the standard Lattice tools.
> >
> > If it is not relevant to you - fine - I never asked you.
> > Just like asking an experienced C programmer - why not Forth ...
> LOL Yes, if one guy working in a corner of the room is using it, then it must be not only good, but GREAT!
>
> The millions of users of VHDL and Verilog must have it wrong.
>
> One of my early jobs involved designing a microprogrammed DMA controller using an off the shelf sequencer chip. The other, similar designs in the company all used the same assembler tool. I added a few macros and opcodes, in order to give my design additional self-test capabilities. One of the managers said that was a bad idea because no one else would know how to use this "different" tool. I realized that there are many times when standardization is preferred over technical advantages, because technical advantages are of no use if they make the design hard to work with or modify.
>
> In this case, there is no real utility to this "special" design process and it actually appears to be much more complex and difficult to use.
>
> Thank you for the information.
>
> --
>
> Rick C.
>
> +-- Get 1,000 miles of free Supercharging
> +-- Tesla referral code - https://ts.la/richard11209

Click here to read the complete article

Re: FPGA4th

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Subject: Re: FPGA4th
From: gnuarm.d...@gmail.com (Lorem Ipsum)
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by: Lorem Ipsum - Tue, 11 Oct 2022 14:46 UTC

On Tuesday, October 11, 2022 at 9:54:49 AM UTC-4, jpit...@gmail.com wrote:
> On Monday, 10 October 2022 at 16:52:33 UTC+1, gnuarm.del...@gmail.com wrote:
> > On Monday, October 10, 2022 at 11:19:41 AM UTC-4, jpit...@gmail.com wrote:
> > > On Monday, 10 October 2022 at 08:35:40 UTC+1, gnuarm.del...@gmail.com wrote:
> > > > On Monday, October 10, 2022 at 2:23:05 AM UTC-4, jpit...@gmail.com wrote:
> > > > > On Sunday, 9 October 2022 at 20:15:22 UTC+1, gnuarm.del...@gmail.com wrote:
> > > > > > On Sunday, October 9, 2022 at 1:54:54 PM UTC-4, jpit...@gmail.com wrote:
> > > > > > > On Sunday, 9 October 2022 at 18:51:06 UTC+1, gnuarm.del...@gmail.com wrote:
> > > > > > > > On Sunday, October 9, 2022 at 12:50:32 PM UTC-4, jpit...@gmail.com wrote:
> > > > > > > > > On Sunday, 9 October 2022 at 09:18:58 UTC+1, Jurgen Pitaske wrote:
> > > > > > > > > > On Sunday, 9 October 2022 at 07:37:50 UTC+1, johnro...@gmail.com wrote:
> > > > > > > > > > > On Wednesday, January 12, 2022 at 3:35:17 AM UTC-7, jpit...@gmail.com wrote:
> > > > > > > > > > > > On Wednesday, 12 January 2022 at 08:01:17 UTC, johnro...@gmail.com wrote:
> > > > > > > > > > > > > On Thursday, November 25, 2021 at 2:39:20 AM UTC-7, jpit...@gmail.com wrote:
> > > > > > > > > > > > > > On Thursday, 25 November 2021 at 07:06:47 UTC, johnro...@gmail.com wrote:
> > > > > > > > > > > > > > > \ Op Code File for MFX. Generated by MAKE-OPS v13
> > > > > > > > > > > The Logic Compiler is working and the modules for the processor are done and tested. After the mem interface module is complete we'll be ready to put the design into the fpga. We're using a X02-7000 but the design will work in any equivalent part.
> > > > > > > > > > > jrh
> > > > > > > > > > Looking forward to it.
> > > > > > > > > > Posting and distributing it in different places including facembbok should be easy.
> > > > > > > > > >
> > > > > > > > > > An idea crossed my mind:
> > > > > > > > > > Why not do a presentation during a FIG Zoom?
> > > > > > > > > > And this would help with where to post it.
> > > > > > > > > > http://www.forth.org/svfig/
> > > > > > > > > Just for people who might not know the context:
> > > > > > > > >
> > > > > > > > > Would it not be nice to use VHDL on an FPGA to write to it directly in Forth.
> > > > > > > > > See the link to Testra where it has been done already.
> > > > > > > > > http://testra.com/Forth/VHDL.htm
> > > > > > > > >
> > > > > > > > > And hopefully there is more soon from Testra posted here...
> > > > > > > > Sorry, I don't follow. What are you describing by, "use VHDL on an FPGA to write to it directly in Forth"?
> > > > > > > >
> > > > > > > > If you are talking about a stack CPU, written in VHDL, running on an FPGA, that has been done many, many times, some published, many not published. It would seem to be a trivial exercise.
> > > > > > > >
> > > > > > > > --
> > > > > > > >
> > > > > > > > Rick C.
> > > > > > > >
> > > > > > > > --+ Get 1,000 miles of free Supercharging
> > > > > > > > --+ Tesla referral code - https://ts.la/richard11209
> > > > > > > You are proving again that you attention span is zero - or is it your reading capability?
> > > > > > >
> > > > > > > Designing logic with the Forth VHDL
> > > > > > >
> > > > > > > 1. Write a software simulation of the design.
> > > > > > > 2. Test the design.
> > > > > > > 3. Convert the software simulation into a hardware definition..
> > > > > > > 4. Compile the hardware definition into logic equations.
> > > > > > > 5. Fit the logic equations into the device.
> > > > > > > 6. Verify that the logic equations work correctly.
> > > > > > > 7. Route the signals and assign the I/O pins.
> > > > > > > 8. Convert the routed design into a fusemap.
> > > > > > "Forth VHDL"??? You are talking about a VHDL synthesis tool written in Forth??? No, that doesn't fit the description of what is going on. In fact, your description doesn't seem to relate to VHDL at all.
> > > > > >
> > > > > > I can't tell what you are talking about from this description,
> > > > > > but it sounds like it is for CPLDs, rather than FPGAs.
> > > > > Maybe we are hitting a language barrier.
> > > > > >
> > > > > > --
> > > > > >
> > > > > > Rick C.
> > > > > >
> > > > > > -+- Get 1,000 miles of free Supercharging
> > > > > > -+- Tesla referral code - https://ts.la/richard11209
> > > > > The linfo at Testra clearly states:
> > > > >
> > > > > Using Forth as a VHDL ( Virtual Hardware Definition Language )
> > > > > John R. Hart, Testra Corporation
> > > > Ah, so he's bastardizing the term VHDL. That's normally used as the name of a language for programming digital logic (VHSIC Hardware Description Language).
> > > > > They used it on a CPLD first, and on a Lattice FPGA 7k now.
> > > > > Hugh Aguilar was involved there.
> > > > >
> > > > > And with all of the knowledge and experience here or elsewhere
> > > > > it could probably be ported to
> > > > > other FPGA families.
> > > > >
> > > > > You have all of the advantages of Forth,
> > > > > and no need for the overhead of FPGA tools as I understand.
> > > > It's not quite that simple. To target an FPGA device, you have to know the bitstream format. The vendors don't typically provide that information. Some people have reverse engineered a very few of the Lattice parts. I was not aware that the X02-7000 had been reverse engineered, but it's possible. Figuring out the bit map for other devices is not at all simple. It's tons of work.
> > > > > I am surprised this has not been of interest for the last many years,
> > > > > as the info on the Testra website was always there.
> > > > Open source tools have been of interest and exist. But not for many parts, for the reasons I've explained.
> > > > > But now we hopefully get the opportunity to see a full example.
> > > > "Full example"???
> > > >
> > > > It's a tool of little value in the FPGA world. Homebrew amateurs may find it interesting, but the FPGA world will simply yawn.
> > > >
> > > > I don't know how accurate your list of steps in using the tool is, but it sounds to me like a lot more work than the use of typical FPGA tools.. Here's the steps required for designing FPGAs.
> > > >
> > > > 1. Write the design in VHDL or Verilog
> > > > 2. Write a test bench for the simulation stimulus and error checking.
> > > > 3. Simulate the design using conventional simulators.
> > > > 4. Synthesize the design for the target chip.
> > > > 5. Test on the target board.
> > > >
> > > > Done. The only "writing" of code is the design and the test bench for simulation. Everything else is a working tool.
> > > >
> > > > --
> > > >
> > > > Rick C.
> > > >
> > > > -++ Get 1,000 miles of free Supercharging
> > > > -++ Tesla referral code - https://ts.la/richard11209
> > > I am sorry, but your post does not make sense to me.
> > >
> > > Testra use this setup for many years in their products
> > > and it must make sense there,
> > > otherwise they would just use the standard Lattice tools.
> > >
> > > If it is not relevant to you - fine - I never asked you.
> > > Just like asking an experienced C programmer - why not Forth ...
> > LOL Yes, if one guy working in a corner of the room is using it, then it must be not only good, but GREAT!
> >
> > The millions of users of VHDL and Verilog must have it wrong.
> >
> > One of my early jobs involved designing a microprogrammed DMA controller using an off the shelf sequencer chip. The other, similar designs in the company all used the same assembler tool. I added a few macros and opcodes, in order to give my design additional self-test capabilities. One of the managers said that was a bad idea because no one else would know how to use this "different" tool. I realized that there are many times when standardization is preferred over technical advantages, because technical advantages are of no use if they make the design hard to work with or modify.
> >
> > In this case, there is no real utility to this "special" design process and it actually appears to be much more complex and difficult to use.
> >
> > Thank you for the information.
> >
> > --
> >
> > Rick C.
> >
> > +-- Get 1,000 miles of free Supercharging
> > +-- Tesla referral code - https://ts.la/richard11209
> It seems there are others working in the corner that are interested in this subject,
> see about 46.00 onwards, e.g. gelforth
> https://www.youtube.com/watch?v=ASgBoKisWac

Click here to read the complete article

Re: FPGA4th

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Subject: Re: FPGA4th
From: jpita...@gmail.com (Jurgen Pitaske)
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by: Jurgen Pitaske - Tue, 11 Oct 2022 14:52 UTC

On Tuesday, 11 October 2022 at 15:46:54 UTC+1, gnuarm.del...@gmail.com wrote:
> On Tuesday, October 11, 2022 at 9:54:49 AM UTC-4, jpit...@gmail.com wrote:
> > On Monday, 10 October 2022 at 16:52:33 UTC+1, gnuarm.del...@gmail.com wrote:
> > > On Monday, October 10, 2022 at 11:19:41 AM UTC-4, jpit...@gmail.com wrote:
> > > > On Monday, 10 October 2022 at 08:35:40 UTC+1, gnuarm.del...@gmail.com wrote:
> > > > > On Monday, October 10, 2022 at 2:23:05 AM UTC-4, jpit...@gmail.com wrote:
> > > > > > On Sunday, 9 October 2022 at 20:15:22 UTC+1, gnuarm.del...@gmail.com wrote:
> > > > > > > On Sunday, October 9, 2022 at 1:54:54 PM UTC-4, jpit...@gmail..com wrote:
> > > > > > > > On Sunday, 9 October 2022 at 18:51:06 UTC+1, gnuarm.del...@gmail.com wrote:
> > > > > > > > > On Sunday, October 9, 2022 at 12:50:32 PM UTC-4, jpit...@gmail.com wrote:
> > > > > > > > > > On Sunday, 9 October 2022 at 09:18:58 UTC+1, Jurgen Pitaske wrote:
> > > > > > > > > > > On Sunday, 9 October 2022 at 07:37:50 UTC+1, johnro....@gmail.com wrote:
> > > > > > > > > > > > On Wednesday, January 12, 2022 at 3:35:17 AM UTC-7, jpit...@gmail.com wrote:
> > > > > > > > > > > > > On Wednesday, 12 January 2022 at 08:01:17 UTC, johnro...@gmail.com wrote:
> > > > > > > > > > > > > > On Thursday, November 25, 2021 at 2:39:20 AM UTC-7, jpit...@gmail.com wrote:
> > > > > > > > > > > > > > > On Thursday, 25 November 2021 at 07:06:47 UTC, johnro...@gmail.com wrote:
> > > > > > > > > > > > > > > > \ Op Code File for MFX. Generated by MAKE-OPS v13
> > > > > > > > > > > > The Logic Compiler is working and the modules for the processor are done and tested. After the mem interface module is complete we'll be ready to put the design into the fpga. We're using a X02-7000 but the design will work in any equivalent part.
> > > > > > > > > > > > jrh
> > > > > > > > > > > Looking forward to it.
> > > > > > > > > > > Posting and distributing it in different places including facembbok should be easy.
> > > > > > > > > > >
> > > > > > > > > > > An idea crossed my mind:
> > > > > > > > > > > Why not do a presentation during a FIG Zoom?
> > > > > > > > > > > And this would help with where to post it.
> > > > > > > > > > > http://www.forth.org/svfig/
> > > > > > > > > > Just for people who might not know the context:
> > > > > > > > > >
> > > > > > > > > > Would it not be nice to use VHDL on an FPGA to write to it directly in Forth.
> > > > > > > > > > See the link to Testra where it has been done already.
> > > > > > > > > > http://testra.com/Forth/VHDL.htm
> > > > > > > > > >
> > > > > > > > > > And hopefully there is more soon from Testra posted here..
> > > > > > > > > Sorry, I don't follow. What are you describing by, "use VHDL on an FPGA to write to it directly in Forth"?
> > > > > > > > >
> > > > > > > > > If you are talking about a stack CPU, written in VHDL, running on an FPGA, that has been done many, many times, some published, many not published. It would seem to be a trivial exercise.
> > > > > > > > >
> > > > > > > > > --
> > > > > > > > >
> > > > > > > > > Rick C.
> > > > > > > > >
> > > > > > > > > --+ Get 1,000 miles of free Supercharging
> > > > > > > > > --+ Tesla referral code - https://ts.la/richard11209
> > > > > > > > You are proving again that you attention span is zero - or is it your reading capability?
> > > > > > > >
> > > > > > > > Designing logic with the Forth VHDL
> > > > > > > >
> > > > > > > > 1. Write a software simulation of the design.
> > > > > > > > 2. Test the design.
> > > > > > > > 3. Convert the software simulation into a hardware definition.
> > > > > > > > 4. Compile the hardware definition into logic equations.
> > > > > > > > 5. Fit the logic equations into the device.
> > > > > > > > 6. Verify that the logic equations work correctly.
> > > > > > > > 7. Route the signals and assign the I/O pins.
> > > > > > > > 8. Convert the routed design into a fusemap.
> > > > > > > "Forth VHDL"??? You are talking about a VHDL synthesis tool written in Forth??? No, that doesn't fit the description of what is going on.. In fact, your description doesn't seem to relate to VHDL at all.
> > > > > > >
> > > > > > > I can't tell what you are talking about from this description,
> > > > > > > but it sounds like it is for CPLDs, rather than FPGAs.
> > > > > > Maybe we are hitting a language barrier.
> > > > > > >
> > > > > > > --
> > > > > > >
> > > > > > > Rick C.
> > > > > > >
> > > > > > > -+- Get 1,000 miles of free Supercharging
> > > > > > > -+- Tesla referral code - https://ts.la/richard11209
> > > > > > The linfo at Testra clearly states:
> > > > > >
> > > > > > Using Forth as a VHDL ( Virtual Hardware Definition Language )
> > > > > > John R. Hart, Testra Corporation
> > > > > Ah, so he's bastardizing the term VHDL. That's normally used as the name of a language for programming digital logic (VHSIC Hardware Description Language).
> > > > > > They used it on a CPLD first, and on a Lattice FPGA 7k now.
> > > > > > Hugh Aguilar was involved there.
> > > > > >
> > > > > > And with all of the knowledge and experience here or elsewhere
> > > > > > it could probably be ported to
> > > > > > other FPGA families.
> > > > > >
> > > > > > You have all of the advantages of Forth,
> > > > > > and no need for the overhead of FPGA tools as I understand.
> > > > > It's not quite that simple. To target an FPGA device, you have to know the bitstream format. The vendors don't typically provide that information. Some people have reverse engineered a very few of the Lattice parts. I was not aware that the X02-7000 had been reverse engineered, but it's possible. Figuring out the bit map for other devices is not at all simple. It's tons of work.
> > > > > > I am surprised this has not been of interest for the last many years,
> > > > > > as the info on the Testra website was always there.
> > > > > Open source tools have been of interest and exist. But not for many parts, for the reasons I've explained.
> > > > > > But now we hopefully get the opportunity to see a full example.
> > > > > "Full example"???
> > > > >
> > > > > It's a tool of little value in the FPGA world. Homebrew amateurs may find it interesting, but the FPGA world will simply yawn.
> > > > >
> > > > > I don't know how accurate your list of steps in using the tool is, but it sounds to me like a lot more work than the use of typical FPGA tools. Here's the steps required for designing FPGAs.
> > > > >
> > > > > 1. Write the design in VHDL or Verilog
> > > > > 2. Write a test bench for the simulation stimulus and error checking.
> > > > > 3. Simulate the design using conventional simulators.
> > > > > 4. Synthesize the design for the target chip.
> > > > > 5. Test on the target board.
> > > > >
> > > > > Done. The only "writing" of code is the design and the test bench for simulation. Everything else is a working tool.
> > > > >
> > > > > --
> > > > >
> > > > > Rick C.
> > > > >
> > > > > -++ Get 1,000 miles of free Supercharging
> > > > > -++ Tesla referral code - https://ts.la/richard11209
> > > > I am sorry, but your post does not make sense to me.
> > > >
> > > > Testra use this setup for many years in their products
> > > > and it must make sense there,
> > > > otherwise they would just use the standard Lattice tools.
> > > >
> > > > If it is not relevant to you - fine - I never asked you.
> > > > Just like asking an experienced C programmer - why not Forth ...
> > > LOL Yes, if one guy working in a corner of the room is using it, then it must be not only good, but GREAT!
> > >
> > > The millions of users of VHDL and Verilog must have it wrong.
> > >
> > > One of my early jobs involved designing a microprogrammed DMA controller using an off the shelf sequencer chip. The other, similar designs in the company all used the same assembler tool. I added a few macros and opcodes, in order to give my design additional self-test capabilities. One of the managers said that was a bad idea because no one else would know how to use this "different" tool. I realized that there are many times when standardization is preferred over technical advantages, because technical advantages are of no use if they make the design hard to work with or modify.
> > >
> > > In this case, there is no real utility to this "special" design process and it actually appears to be much more complex and difficult to use.
> > >
> > > Thank you for the information.
> > >
> > > --
> > >
> > > Rick C.
> > >
> > > +-- Get 1,000 miles of free Supercharging
> > > +-- Tesla referral code - https://ts.la/richard11209
> > It seems there are others working in the corner that are interested in this subject,
> > see about 46.00 onwards, e.g. gelforth
> > https://www.youtube.com/watch?v=ASgBoKisWac
> "Others"??? You mean "other", I think.
>
> Trying to use Forth as the language to compose logic is solving a problem that doesn't exist. We have Verilog and VHDL as the mainstream languages for logic hardware design and they work well. There are efforts to use C for hardware logic design, which is seldom used. The main justification for using C is to have a common language for hardware and software, so the dividing line is easily moved, allowing one system design to be implemented in different ways with different performance levels. In reality, this is not at all simple to do. Hardware and software require interfaces. When you change the dividing line in the code for that interface and you have to redesign everything about that interface. So it is seldom used this way.
>
> I stand by my statement that using Forth for both software and hardware design is of little value. The fact that you found one guy, who, six years ago, worked on using Forth as a hardware description language, does not mean it is a good idea. If that were true, why has nothing happened with it in the last six years?
>
> People like to think that applying Forth to a problem, will make that problem simple to solve. Digital hardware logic design is not a simple task, not because of the tools used. The tools are complicated because the problem is complicated. The existing tools have simplified the work by hiding the complexity as much as possible. This works 99.9% of the time, allowing work to proceed with reasonable speed and accuracy. I can't see where Forth is going to help this at all.
>
> --
>
> Rick C.
>
> +-+ Get 1,000 miles of free Supercharging
> +-+ Tesla referral code - https://ts.la/richard11209

Click here to read the complete article

Re: FPGA4th

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Subject: Re: FPGA4th
From: johnroge...@gmail.com (John Hart)
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by: John Hart - Tue, 11 Oct 2022 20:01 UTC

> > > > > > It's a tool of little value in the FPGA world. Homebrew amateurs may find it interesting, but the FPGA world will...
> Well, there seems to be only "ONE PERSON" who does not like this.

Jurgen,

As I read Rick's response I had to smile. Not knowing it, he summed up the reasons why authoritarian systems don't work. The reason Forth is useful is its extensibility; can be turned into any tool one wants, including a verilog code generator. Then, even if the result isn't perfect, one can edit the output to one's heart's content, which of course is what I do.

A more difficult aspect of logic design is verifying it works. To do so one needs a reference to compare with. Forth, being extensible, is the ideal tool, especially when designing a Forth processor.

To create the new processor's software model took about a week, and it was easy to modify as the design progressed. The SW model provides the data needed by the hardware simulator to verify the verilog code is working. Rapid specific feedback is the key to perfecting complex logic designs.

jrh

Re: FPGA4th

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Subject: Re: FPGA4th
From: jpita...@gmail.com (Jurgen Pitaske)
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by: Jurgen Pitaske - Wed, 12 Oct 2022 06:23 UTC

On Tuesday, 11 October 2022 at 21:01:09 UTC+1, johnro...@gmail.com wrote:
> > > > > > > It's a tool of little value in the FPGA world. Homebrew amateurs may find it interesting, but the FPGA world will...
> > Well, there seems to be only "ONE PERSON" who does not like this.

> Jurgen,
>
> As I read Rick's response I had to smile.
> Not knowing it, he summed up the reasons why authoritarian systems don't work.
> The reason Forth is useful is its extensibility;
> can be turned into any tool one wants, including a verilog code generator.
> Then, even if the result isn't perfect, one can edit the output to one's heart's content, which of course is what I do.
>
> A more difficult aspect of logic design is verifying it works.
> To do so one needs a reference to compare with. Forth, being extensible, is the ideal tool, especially when designing a Forth processor.
>
> To create the new processor's software model took about a week,
> and it was easy to modify as the design progressed.
> The SW model provides the data needed by the hardware simulator to verify the verilog code is working.
> Rapid specific feedback is the key to perfecting complex logic designs.
>
> jrh

What a great post John.
You just sum up what this tool Forth can be adapted to for your requirements.
And you help to spread the message what your implementation can be used for as well.

Will it replace VHDL? No
Will it replace Verilog - probably not.
But it is an additional tool as you use it and describe it.
I have just enough knowledge in this area to see it can be useful.
And when I saw it the first time I was impressed.
I hope you will post more about your approach
so others can understand it better and take advantage of it in their work.

Just an idea:
I could convince Steve Teal to write the Minimum RISC in VHDL.
And as a bonus he added an eForth.
https://github.com/Steve-Teal/eforth-misc16

How difficult would it be to replicate this design using your tools and Forth as VHDL?
And use the same FPGA you use now?

This would be a way to show others a full design,
using standard tools on one side,
and then compare it with your tools.
Your tools could then probably more easily show how to add additional IOs.

Thanks again - and can we have more please.

Re: FPGA4th

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Subject: Re: FPGA4th
From: waynemor...@gmail.com (Wayne morellini)
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by: Wayne morellini - Sun, 16 Oct 2022 03:58 UTC

On Wednesday, October 12, 2022 at 6:01:09 AM UTC+10, johnro...@gmail.com wrote:
> > > > > > > It's a tool of little value in the FPGA world. Homebrew amateurs may find it interesting, but the FPGA world will...
> > Well, there seems to be only "ONE PERSON" who does not like this.
> Jurgen,
>
> As I read Rick's response I had to smile. Not knowing it, he summed up the reasons why authoritarian systems don't work. The reason Forth is useful is its extensibility; can be turned into any tool one wants, including a verilog code generator. Then, even if the result isn't perfect, one can edit the output to one's heart's content, which of course is what I do.
>
> A more difficult aspect of logic design is verifying it works. To do so one needs a reference to compare with. Forth, being extensible, is the ideal tool, especially when designing a Forth processor.
>
> To create the new processor's software model took about a week, and it was easy to modify as the design progressed. The SW model provides the data needed by the hardware simulator to verify the verilog code is working. Rapid specific feedback is the key to perfecting complex logic designs.
>
> jrh

John, thank you. Looks interesting.

Re: FPGA4th

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by: Myron Plichota - Sun, 16 Oct 2022 18:03 UTC

On Tuesday, October 11, 2022 at 10:52:55 AM UTC-4, jpit...@gmail.com wrote:
> On Tuesday, 11 October 2022 at 15:46:54 UTC+1, gnuarm.del...@gmail.com wrote:
> > On Tuesday, October 11, 2022 at 9:54:49 AM UTC-4, jpit...@gmail.com wrote:
> > > On Monday, 10 October 2022 at 16:52:33 UTC+1, gnuarm.del...@gmail.com wrote:
> > > > On Monday, October 10, 2022 at 11:19:41 AM UTC-4, jpit...@gmail.com wrote:
> > > > > On Monday, 10 October 2022 at 08:35:40 UTC+1, gnuarm.del...@gmail..com wrote:
> > > > > > On Monday, October 10, 2022 at 2:23:05 AM UTC-4, jpit...@gmail.com wrote:
> > > > > > > On Sunday, 9 October 2022 at 20:15:22 UTC+1, gnuarm.del...@gmail.com wrote:
> > > > > > > > On Sunday, October 9, 2022 at 1:54:54 PM UTC-4, jpit...@gmail.com wrote:
> > > > > > > > > On Sunday, 9 October 2022 at 18:51:06 UTC+1, gnuarm.del....@gmail.com wrote:
> > > > > > > > > > On Sunday, October 9, 2022 at 12:50:32 PM UTC-4, jpit....@gmail.com wrote:
> > > > > > > > > > > On Sunday, 9 October 2022 at 09:18:58 UTC+1, Jurgen Pitaske wrote:
> > > > > > > > > > > > On Sunday, 9 October 2022 at 07:37:50 UTC+1, johnro....@gmail.com wrote:
> > > > > > > > > > > > > On Wednesday, January 12, 2022 at 3:35:17 AM UTC-7, jpit...@gmail.com wrote:
> > > > > > > > > > > > > > On Wednesday, 12 January 2022 at 08:01:17 UTC, johnro...@gmail.com wrote:
> > > > > > > > > > > > > > > On Thursday, November 25, 2021 at 2:39:20 AM UTC-7, jpit...@gmail.com wrote:
> > > > > > > > > > > > > > > > On Thursday, 25 November 2021 at 07:06:47 UTC, johnro...@gmail.com wrote:
> > > > > > > > > > > > > > > > > \ Op Code File for MFX. Generated by MAKE-OPS v13
> > > > > > > > > > > > > The Logic Compiler is working and the modules for the processor are done and tested. After the mem interface module is complete we'll be ready to put the design into the fpga. We're using a X02-7000 but the design will work in any equivalent part.
> > > > > > > > > > > > > jrh
> > > > > > > > > > > > Looking forward to it.
> > > > > > > > > > > > Posting and distributing it in different places including facembbok should be easy.
> > > > > > > > > > > >
> > > > > > > > > > > > An idea crossed my mind:
> > > > > > > > > > > > Why not do a presentation during a FIG Zoom?
> > > > > > > > > > > > And this would help with where to post it.
> > > > > > > > > > > > http://www.forth.org/svfig/
> > > > > > > > > > > Just for people who might not know the context:
> > > > > > > > > > >
> > > > > > > > > > > Would it not be nice to use VHDL on an FPGA to write to it directly in Forth.
> > > > > > > > > > > See the link to Testra where it has been done already..
> > > > > > > > > > > http://testra.com/Forth/VHDL.htm
> > > > > > > > > > >
> > > > > > > > > > > And hopefully there is more soon from Testra posted here..
> > > > > > > > > > Sorry, I don't follow. What are you describing by, "use VHDL on an FPGA to write to it directly in Forth"?
> > > > > > > > > >
> > > > > > > > > > If you are talking about a stack CPU, written in VHDL, running on an FPGA, that has been done many, many times, some published, many not published. It would seem to be a trivial exercise.
> > > > > > > > > >
> > > > > > > > > > --
> > > > > > > > > >
> > > > > > > > > > Rick C.
> > > > > > > > > >
> > > > > > > > > > --+ Get 1,000 miles of free Supercharging
> > > > > > > > > > --+ Tesla referral code - https://ts.la/richard11209
> > > > > > > > > You are proving again that you attention span is zero - or is it your reading capability?
> > > > > > > > >
> > > > > > > > > Designing logic with the Forth VHDL
> > > > > > > > >
> > > > > > > > > 1. Write a software simulation of the design.
> > > > > > > > > 2. Test the design.
> > > > > > > > > 3. Convert the software simulation into a hardware definition.
> > > > > > > > > 4. Compile the hardware definition into logic equations.
> > > > > > > > > 5. Fit the logic equations into the device.
> > > > > > > > > 6. Verify that the logic equations work correctly.
> > > > > > > > > 7. Route the signals and assign the I/O pins.
> > > > > > > > > 8. Convert the routed design into a fusemap.
> > > > > > > > "Forth VHDL"??? You are talking about a VHDL synthesis tool written in Forth??? No, that doesn't fit the description of what is going on. In fact, your description doesn't seem to relate to VHDL at all.
> > > > > > > >
> > > > > > > > I can't tell what you are talking about from this description,
> > > > > > > > but it sounds like it is for CPLDs, rather than FPGAs.
> > > > > > > Maybe we are hitting a language barrier.
> > > > > > > >
> > > > > > > > --
> > > > > > > >
> > > > > > > > Rick C.
> > > > > > > >
> > > > > > > > -+- Get 1,000 miles of free Supercharging
> > > > > > > > -+- Tesla referral code - https://ts.la/richard11209
> > > > > > > The linfo at Testra clearly states:
> > > > > > >
> > > > > > > Using Forth as a VHDL ( Virtual Hardware Definition Language )
> > > > > > > John R. Hart, Testra Corporation
> > > > > > Ah, so he's bastardizing the term VHDL. That's normally used as the name of a language for programming digital logic (VHSIC Hardware Description Language).
> > > > > > > They used it on a CPLD first, and on a Lattice FPGA 7k now.
> > > > > > > Hugh Aguilar was involved there.
> > > > > > >
> > > > > > > And with all of the knowledge and experience here or elsewhere
> > > > > > > it could probably be ported to
> > > > > > > other FPGA families.
> > > > > > >
> > > > > > > You have all of the advantages of Forth,
> > > > > > > and no need for the overhead of FPGA tools as I understand.
> > > > > > It's not quite that simple. To target an FPGA device, you have to know the bitstream format. The vendors don't typically provide that information. Some people have reverse engineered a very few of the Lattice parts. I was not aware that the X02-7000 had been reverse engineered, but it's possible. Figuring out the bit map for other devices is not at all simple. It's tons of work.
> > > > > > > I am surprised this has not been of interest for the last many years,
> > > > > > > as the info on the Testra website was always there.
> > > > > > Open source tools have been of interest and exist. But not for many parts, for the reasons I've explained.
> > > > > > > But now we hopefully get the opportunity to see a full example.
> > > > > > "Full example"???
> > > > > >
> > > > > > It's a tool of little value in the FPGA world. Homebrew amateurs may find it interesting, but the FPGA world will simply yawn.
> > > > > >
> > > > > > I don't know how accurate your list of steps in using the tool is, but it sounds to me like a lot more work than the use of typical FPGA tools. Here's the steps required for designing FPGAs.
> > > > > >
> > > > > > 1. Write the design in VHDL or Verilog
> > > > > > 2. Write a test bench for the simulation stimulus and error checking.
> > > > > > 3. Simulate the design using conventional simulators.
> > > > > > 4. Synthesize the design for the target chip.
> > > > > > 5. Test on the target board.
> > > > > >
> > > > > > Done. The only "writing" of code is the design and the test bench for simulation. Everything else is a working tool.
> > > > > >
> > > > > > --
> > > > > >
> > > > > > Rick C.
> > > > > >
> > > > > > -++ Get 1,000 miles of free Supercharging
> > > > > > -++ Tesla referral code - https://ts.la/richard11209
> > > > > I am sorry, but your post does not make sense to me.
> > > > >
> > > > > Testra use this setup for many years in their products
> > > > > and it must make sense there,
> > > > > otherwise they would just use the standard Lattice tools.
> > > > >
> > > > > If it is not relevant to you - fine - I never asked you.
> > > > > Just like asking an experienced C programmer - why not Forth ...
> > > > LOL Yes, if one guy working in a corner of the room is using it, then it must be not only good, but GREAT!
> > > >
> > > > The millions of users of VHDL and Verilog must have it wrong.
> > > >
> > > > One of my early jobs involved designing a microprogrammed DMA controller using an off the shelf sequencer chip. The other, similar designs in the company all used the same assembler tool. I added a few macros and opcodes, in order to give my design additional self-test capabilities. One of the managers said that was a bad idea because no one else would know how to use this "different" tool. I realized that there are many times when standardization is preferred over technical advantages, because technical advantages are of no use if they make the design hard to work with or modify.
> > > >
> > > > In this case, there is no real utility to this "special" design process and it actually appears to be much more complex and difficult to use.
> > > >
> > > > Thank you for the information.
> > > >
> > > > --
> > > >
> > > > Rick C.
> > > >
> > > > +-- Get 1,000 miles of free Supercharging
> > > > +-- Tesla referral code - https://ts.la/richard11209
> > > It seems there are others working in the corner that are interested in this subject,
> > > see about 46.00 onwards, e.g. gelforth
> > > https://www.youtube.com/watch?v=ASgBoKisWac
> > "Others"??? You mean "other", I think.
> >
> > Trying to use Forth as the language to compose logic is solving a problem that doesn't exist. We have Verilog and VHDL as the mainstream languages for logic hardware design and they work well. There are efforts to use C for hardware logic design, which is seldom used. The main justification for using C is to have a common language for hardware and software, so the dividing line is easily moved, allowing one system design to be implemented in different ways with different performance levels. In reality, this is not at all simple to do. Hardware and software require interfaces. When you change the dividing line in the code for that interface and you have to redesign everything about that interface. So it is seldom used this way.
> >
> > I stand by my statement that using Forth for both software and hardware design is of little value. The fact that you found one guy, who, six years ago, worked on using Forth as a hardware description language, does not mean it is a good idea. If that were true, why has nothing happened with it in the last six years?
> >
> > People like to think that applying Forth to a problem, will make that problem simple to solve. Digital hardware logic design is not a simple task, not because of the tools used. The tools are complicated because the problem is complicated. The existing tools have simplified the work by hiding the complexity as much as possible. This works 99.9% of the time, allowing work to proceed with reasonable speed and accuracy. I can't see where Forth is going to help this at all.
> >
> > --
> >
> > Rick C.
> >
> > +-+ Get 1,000 miles of free Supercharging
> > +-+ Tesla referral code - https://ts.la/richard11209
> Well, there seems to be only "ONE PERSON" who does not like this.
> As there are 2 or three people who see it as interesting,
> your importance with your comments is going down to a third.
> AND:
> The number of your posts does NOT increase the importance or value.
> And there might be a Forth Person anyway ...
I respect Rick C's opinions on the art of FPGA design. IMHO his comments are incisive and reality-oriented. I'm pretty sure he has experience in the matter.

Click here to read the complete article

Re: FPGA4th

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Subject: Re: FPGA4th
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by: John Hart - Sun, 16 Oct 2022 20:22 UTC

\ Op Code File for MFX. Generated by MAKE-OPS v13
<clip>
> > > > > > > > > > > > > > The Logic Compiler is working and the modules for the processor are done and tested. After the mem interface module is complete we'll be ready to put the design into the fpga. We're using a X02-7000 but the design will work in any equivalent part.
<clip>
> > > > > > > > > > > Sorry, I don't follow. What are you describing by, "use VHDL on an FPGA to write to it directly in Forth"?
> > > > > > > > > > > If you are talking about a stack CPU, written in VHDL, running on an FPGA, that has been done
> > > > > > > > > > > many, many times, some published, many not published. It would seem to be a trivial exercise.
> > > > > > > > > > > Rick C.

Verilog, NOT VHDL. I found it to be too verbose.
And if you have a trivial solution to computer optimization, please post it!

(edited for clarity)
> > > > > > > > > > Designing logic with the Forth VHDL
> > > > > > > > > > 1. Write a software simulation of the design. (Forth with local varables and a MAP extension)
> > > > > > > > > > 2. Test the design. (test program, simple compiler and simulator written in Forth)
> > > > > > > > > > 3. Convert the simulation into a hardware definition. (ED-MGEN, ED-CTRL, ED-DFRW, ED-DCDM, ED-DSEL)
> > > > > > > > > > 4. Link instructions to modules. (EDIT-TRAN)
> > > > > > > > > > 5. Compile the hardware definition into logic equations.. (GEN-MAP, CTRL-MAP & DFRW-MAP programs}
> > > > > > > > > > 6. Verify the logic equations work correctly. (EDIT-DISP, SIM-R32)
> > > > > > > > > > 7. Assign the I/O pins. (ED-PINS, able to parse the csv pin file and combine it with the schematic foot print)
> > > > > > > > > > 8. Fit the logic equations into the device. (Diamond from Lattice Semi does this, and there are universal ones)
> > > > > > > > > > 9. Convert the routed design into a fusemap. (Diamond)
> > > > > > > > > > 10. Compile the OS using the OP code definition file. (MAKE-OPS)
<clip>
> > > > > > > > > "Forth VHDL"??? You are talking about a VHDL synthesis tool written in Forth???
> > > > > > > > > No, that doesn't fit the description of what is going on.
> > > > > > > > > In fact, your description doesn't seem to relate to VHDL at all.
> > > > > > > > > I can't tell what you are talking about from this description,
> > > > > > > > > but it sounds like it is for CPLDs, rather than FPGAs.
> > > > > > > > > Rick C.
Our first CNC product had three 8032 processors. One for motion, One to process files, and one for I/O.
We replaced the motion and file processors with the RACE, (Reduced Architecture Computation Engine)
in our new controller realased in 2000. The RACE and 4 motor controllers fit into a 1048 CPLD from Lattice.
In 2016 we moved the design to an X02-7000 and eliminated the 8032.
The design wasn't optomized for a LUT based part and the OS was getting too large for the address space
so it was obvious we needed to update the design.

Using verilog tools and IP express, provided by Diamond, it took about two years to move our IP to the X02,
I've designed a wide variety of IP from servo system to networks and developed tools along to way to
assist in making such devices. For example the software from Lattice used for the RACE could only
achieve 80% ultization, I devised a tool that allowed us to achieve 100%,

Designing and debuging the software for rapid processor evolution was more difficult than anticipated, as
usual, but necessary for a reconfigurable product that could be used by small business having to compete
with large corporate monopolies that have gained control of the regulatory bodies and are using their
power to crush competion!
> > > > > > > Ah, so he's bastardizing the term VHDL. (there's a little bit of Hugh in everyone)
> > > > > > > > They used it on a CPLD first, and on a Lattice FPGA 7k now.
> > > > > > > > Hugh Aguilar was involved there.
> > > > > > > > And with all of the knowledge and experience here or elsewhere
> > > > > > > > it could probably be ported to
> > > > > > > > other FPGA families.
<clip>
> > > > > One of my early jobs involved designing a microprogrammed DMA controller using an off the shelf sequencer chip. The other, similar designs in the company all used the same assembler tool. I added a few macros and opcodes, in order to give my design additional self-test capabilities. One of the managers said that was a bad idea because no one else would know how to use this "different" tool. I realized that there are many times when standardization is preferred over technical advantages, because technical advantages are of no use if they make the design hard to work with or modify.
> > > > >
> > > > > In this case, there is no real utility to this "special" design process and it actually appears to be much more complex and difficult to use..
> > > > >
<clip>
> > > Trying to use Forth as the language to compose logic is solving a problem that doesn't exist. We have Verilog and VHDL as the mainstream languages for logic hardware design and they work well. There are efforts to use C for hardware logic design, which is seldom used. The main justification for using C is to have a common language for hardware and software, so the dividing line is easily moved, allowing one system design to be implemented in different ways with different performance levels. In reality, this is not at all simple to do. Hardware and software require interfaces. When you change the dividing line in the code for that interface and you have to redesign everything about that interface. So it is seldom used this way.
> > >
> > > I stand by my statement that using Forth for both software and hardware design is of little value. The fact that you found one guy, who, six years ago, worked on using Forth as a hardware description language, does not mean it is a good idea. If that were true, why has nothing happened with it in the last six years?
> > >
> > > People like to think that applying Forth to a problem, will make that problem simple to solve. Digital hardware logic design is not a simple task, not because of the tools used. The tools are complicated because the problem is complicated. The existing tools have simplified the work by hiding the complexity as much as possible. This works 99.9% of the time, allowing work to proceed with reasonable speed and accuracy. I can't see where Forth is going to help this at all.

> > > Rick C.
Each to their own. I've spent too much time on this, got to get back to work.

> Verilog already describes *the desired behaviour of any number of parallel processes, clocked or flow-through*.
>I don't see a need for an exotic "Forth" front end (to generate what?).

I don't know. You tell me.

Re: FPGA4th

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by: Lorem Ipsum - Mon, 17 Oct 2022 00:32 UTC

On Sunday, October 16, 2022 at 4:22:36 PM UTC-4, johnro...@gmail.com wrote:
> \ Op Code File for MFX. Generated by MAKE-OPS v13
> <clip>
> > > > > > > > > > > > > > > The Logic Compiler is working and the modules for the processor are done and tested. After the mem interface module is complete we'll be ready to put the design into the fpga. We're using a X02-7000 but the design will work in any equivalent part.
> <clip>
> > > > > > > > > > > > Sorry, I don't follow. What are you describing by, "use VHDL on an FPGA to write to it directly in Forth"?
> > > > > > > > > > > > If you are talking about a stack CPU, written in VHDL, running on an FPGA, that has been done
> > > > > > > > > > > > many, many times, some published, many not published. It would seem to be a trivial exercise.
> > > > > > > > > > > > Rick C.
>
> Verilog, NOT VHDL. I found it to be too verbose.

If you think Verilog is verbose, don't even bother trying VHDL. Perhaps is it not you, but someone in the thread is using VHDL to stand for something other than its traditional meaning of VHSIC Hardware Description Language. This gets to be very confusing.

> And if you have a trivial solution to computer optimization, please post it!

Not sure what you are referring to.

> (edited for clarity)
> > > > > > > > > > > Designing logic with the Forth VHDL
> > > > > > > > > > > 1. Write a software simulation of the design. (Forth with local varables and a MAP extension)
> > > > > > > > > > > 2. Test the design. (test program, simple compiler and simulator written in Forth)
> > > > > > > > > > > 3. Convert the simulation into a hardware definition. (ED-MGEN, ED-CTRL, ED-DFRW, ED-DCDM, ED-DSEL)
> > > > > > > > > > > 4. Link instructions to modules. (EDIT-TRAN)
> > > > > > > > > > > 5. Compile the hardware definition into logic equations. (GEN-MAP, CTRL-MAP & DFRW-MAP programs}
> > > > > > > > > > > 6. Verify the logic equations work correctly. (EDIT-DISP, SIM-R32)
> > > > > > > > > > > 7. Assign the I/O pins. (ED-PINS, able to parse the csv pin file and combine it with the schematic foot print)
> > > > > > > > > > > 8. Fit the logic equations into the device. (Diamond from Lattice Semi does this, and there are universal ones)
> > > > > > > > > > > 9. Convert the routed design into a fusemap. (Diamond)
> > > > > > > > > > > 10. Compile the OS using the OP code definition file. (MAKE-OPS)
> <clip>
> > > > > > > > > > "Forth VHDL"??? You are talking about a VHDL synthesis tool written in Forth???
> > > > > > > > > > No, that doesn't fit the description of what is going on.
> > > > > > > > > > In fact, your description doesn't seem to relate to VHDL at all.
> > > > > > > > > > I can't tell what you are talking about from this description,
> > > > > > > > > > but it sounds like it is for CPLDs, rather than FPGAs.
> > > > > > > > > > Rick C.
> Our first CNC product had three 8032 processors. One for motion, One to process files, and one for I/O.
> We replaced the motion and file processors with the RACE, (Reduced Architecture Computation Engine)
> in our new controller realased in 2000. The RACE and 4 motor controllers fit into a 1048 CPLD from Lattice.
> In 2016 we moved the design to an X02-7000 and eliminated the 8032.
> The design wasn't optomized for a LUT based part and the OS was getting too large for the address space
> so it was obvious we needed to update the design.
>
> Using verilog tools and IP express, provided by Diamond, it took about two years to move our IP to the X02,
> I've designed a wide variety of IP from servo system to networks and developed tools along to way to
> assist in making such devices. For example the software from Lattice used for the RACE could only
> achieve 80% ultization, I devised a tool that allowed us to achieve 100%,

Silicon is relatively inexpensive, these days. A project has to be very, very high volume to justify such an effort of optimization. I'm currently working on a redesign because of component optimization and I'm happy with 100% overkill on a new part, because the chip cost is only $5 each. I could use a $3 part, but it is 4 kLUT and the previous design was using 90% of a 3 kLUT part. Since it is a change of not just family, but brand, I don't look forward to spending excessive time shoehorning a design into a device. That makes alterations in the design prohibitively expensive as well.

Still, with a volume of perhaps 50,000 pieces, I might go with the smaller chip as long as I can share the footprint with the larger part.

> Designing and debuging the software for rapid processor evolution was more difficult than anticipated, as
> usual, but necessary for a reconfigurable product that could be used by small business having to compete
> with large corporate monopolies that have gained control of the regulatory bodies and are using their
> power to crush competion!
>
> > > > > > > > Ah, so he's bastardizing the term VHDL. (there's a little bit of Hugh in everyone)
> > > > > > > > > They used it on a CPLD first, and on a Lattice FPGA 7k now.
> > > > > > > > > Hugh Aguilar was involved there.
> > > > > > > > > And with all of the knowledge and experience here or elsewhere
> > > > > > > > > it could probably be ported to
> > > > > > > > > other FPGA families.
> <clip>
> > > > > > One of my early jobs involved designing a microprogrammed DMA controller using an off the shelf sequencer chip. The other, similar designs in the company all used the same assembler tool. I added a few macros and opcodes, in order to give my design additional self-test capabilities. One of the managers said that was a bad idea because no one else would know how to use this "different" tool. I realized that there are many times when standardization is preferred over technical advantages, because technical advantages are of no use if they make the design hard to work with or modify.
> > > > > >
> > > > > > In this case, there is no real utility to this "special" design process and it actually appears to be much more complex and difficult to use.
> > > > > >
> <clip>
> > > > Trying to use Forth as the language to compose logic is solving a problem that doesn't exist. We have Verilog and VHDL as the mainstream languages for logic hardware design and they work well. There are efforts to use C for hardware logic design, which is seldom used. The main justification for using C is to have a common language for hardware and software, so the dividing line is easily moved, allowing one system design to be implemented in different ways with different performance levels. In reality, this is not at all simple to do. Hardware and software require interfaces. When you change the dividing line in the code for that interface and you have to redesign everything about that interface. So it is seldom used this way.
> > > >
> > > > I stand by my statement that using Forth for both software and hardware design is of little value. The fact that you found one guy, who, six years ago, worked on using Forth as a hardware description language, does not mean it is a good idea. If that were true, why has nothing happened with it in the last six years?
> > > >
> > > > People like to think that applying Forth to a problem, will make that problem simple to solve. Digital hardware logic design is not a simple task, not because of the tools used. The tools are complicated because the problem is complicated. The existing tools have simplified the work by hiding the complexity as much as possible. This works 99.9% of the time, allowing work to proceed with reasonable speed and accuracy. I can't see where Forth is going to help this at all.
> > > > Rick C.
> Each to their own. I've spent too much time on this, got to get back to work.
> > Verilog already describes *the desired behaviour of any number of parallel processes, clocked or flow-through*.
> >I don't see a need for an exotic "Forth" front end (to generate what?).
> I don't know. You tell me.

I haven't seen anything that would seem to be a Forth description of hardware in this thread, so I can't judge if it is better than one of the existing HDLs or not. But it would need to be pretty good to make it worth learning a new tool and then to try to get it to produce VHDL that commonly available tools can use optimally.

Click here to read the complete article

Re: FPGA4th

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Subject: Re: FPGA4th
From: jpita...@gmail.com (Jurgen Pitaske)
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by: Jurgen Pitaske - Mon, 17 Oct 2022 06:29 UTC

On Sunday, 16 October 2022 at 21:22:36 UTC+1, johnro...@gmail.com wrote:
> \ Op Code File for MFX. Generated by MAKE-OPS v13
> <clip>
> > > > > > > > > > > > > > > The Logic Compiler is working and the modules for the processor are done and tested. After the mem interface module is complete we'll be ready to put the design into the fpga. We're using a X02-7000 but the design will work in any equivalent part.
> <clip>
> > > > > > > > > > > > Sorry, I don't follow. What are you describing by, "use VHDL on an FPGA to write to it directly in Forth"?
> > > > > > > > > > > > If you are talking about a stack CPU, written in VHDL, running on an FPGA, that has been done
> > > > > > > > > > > > many, many times, some published, many not published. It would seem to be a trivial exercise.
> > > > > > > > > > > > Rick C.
>
> Verilog, NOT VHDL. I found it to be too verbose.
> And if you have a trivial solution to computer optimization, please post it!
>
> (edited for clarity)
> > > > > > > > > > > Designing logic with the Forth VHDL
> > > > > > > > > > > 1. Write a software simulation of the design. (Forth with local varables and a MAP extension)
> > > > > > > > > > > 2. Test the design. (test program, simple compiler and simulator written in Forth)
> > > > > > > > > > > 3. Convert the simulation into a hardware definition. (ED-MGEN, ED-CTRL, ED-DFRW, ED-DCDM, ED-DSEL)
> > > > > > > > > > > 4. Link instructions to modules. (EDIT-TRAN)
> > > > > > > > > > > 5. Compile the hardware definition into logic equations. (GEN-MAP, CTRL-MAP & DFRW-MAP programs}
> > > > > > > > > > > 6. Verify the logic equations work correctly. (EDIT-DISP, SIM-R32)
> > > > > > > > > > > 7. Assign the I/O pins. (ED-PINS, able to parse the csv pin file and combine it with the schematic foot print)
> > > > > > > > > > > 8. Fit the logic equations into the device. (Diamond from Lattice Semi does this, and there are universal ones)
> > > > > > > > > > > 9. Convert the routed design into a fusemap. (Diamond)
> > > > > > > > > > > 10. Compile the OS using the OP code definition file. (MAKE-OPS)
> <clip>
> > > > > > > > > > "Forth VHDL"??? You are talking about a VHDL synthesis tool written in Forth???
> > > > > > > > > > No, that doesn't fit the description of what is going on.
> > > > > > > > > > In fact, your description doesn't seem to relate to VHDL at all.
> > > > > > > > > > I can't tell what you are talking about from this description,
> > > > > > > > > > but it sounds like it is for CPLDs, rather than FPGAs.
> > > > > > > > > > Rick C.
> Our first CNC product had three 8032 processors. One for motion, One to process files, and one for I/O.
> We replaced the motion and file processors with the RACE, (Reduced Architecture Computation Engine)
> in our new controller realased in 2000. The RACE and 4 motor controllers fit into a 1048 CPLD from Lattice.
> In 2016 we moved the design to an X02-7000 and eliminated the 8032.
> The design wasn't optomized for a LUT based part and the OS was getting too large for the address space
> so it was obvious we needed to update the design.
>
> Using verilog tools and IP express, provided by Diamond, it took about two years to move our IP to the X02,
> I've designed a wide variety of IP from servo system to networks and developed tools along to way to
> assist in making such devices. For example the software from Lattice used for the RACE could only
> achieve 80% ultization, I devised a tool that allowed us to achieve 100%,
>
> Designing and debuging the software for rapid processor evolution was more difficult than anticipated, as
> usual, but necessary for a reconfigurable product that could be used by small business having to compete
> with large corporate monopolies that have gained control of the regulatory bodies and are using their
> power to crush competion!
>
> > > > > > > > Ah, so he's bastardizing the term VHDL. (there's a little bit of Hugh in everyone)
> > > > > > > > > They used it on a CPLD first, and on a Lattice FPGA 7k now.
> > > > > > > > > Hugh Aguilar was involved there.
> > > > > > > > > And with all of the knowledge and experience here or elsewhere
> > > > > > > > > it could probably be ported to
> > > > > > > > > other FPGA families.
> <clip>
> > > > > > One of my early jobs involved designing a microprogrammed DMA controller using an off the shelf sequencer chip. The other, similar designs in the company all used the same assembler tool. I added a few macros and opcodes, in order to give my design additional self-test capabilities. One of the managers said that was a bad idea because no one else would know how to use this "different" tool. I realized that there are many times when standardization is preferred over technical advantages, because technical advantages are of no use if they make the design hard to work with or modify.
> > > > > >
> > > > > > In this case, there is no real utility to this "special" design process and it actually appears to be much more complex and difficult to use.
> > > > > >
> <clip>
> > > > Trying to use Forth as the language to compose logic is solving a problem that doesn't exist. We have Verilog and VHDL as the mainstream languages for logic hardware design and they work well. There are efforts to use C for hardware logic design, which is seldom used. The main justification for using C is to have a common language for hardware and software, so the dividing line is easily moved, allowing one system design to be implemented in different ways with different performance levels. In reality, this is not at all simple to do. Hardware and software require interfaces. When you change the dividing line in the code for that interface and you have to redesign everything about that interface. So it is seldom used this way.
> > > >
> > > > I stand by my statement that using Forth for both software and hardware design is of little value. The fact that you found one guy, who, six years ago, worked on using Forth as a hardware description language, does not mean it is a good idea. If that were true, why has nothing happened with it in the last six years?
> > > >
> > > > People like to think that applying Forth to a problem, will make that problem simple to solve. Digital hardware logic design is not a simple task, not because of the tools used. The tools are complicated because the problem is complicated. The existing tools have simplified the work by hiding the complexity as much as possible. This works 99.9% of the time, allowing work to proceed with reasonable speed and accuracy. I can't see where Forth is going to help this at all.
> > > > Rick C.
> Each to their own. I've spent too much time on this, got to get back to work.
> > Verilog already describes *the desired behaviour of any number of parallel processes, clocked or flow-through*.
> >I don't see a need for an exotic "Forth" front end (to generate what?).
> I don't know. You tell me.

Thank you very much again for investing the time of your post.
It was a bit difficult to read on my screen, so I copied parts out and edited it into a PDF for easier reading.
So I can as well share it
The file Forth as VHDL v1 there
https://www.dropbox.com/sh/ah8umk0hgq1818s/AAC8nNEueZZcIYJ8uGP4F4wPa?dl=0

I find Rick's arrogance rather funny as he does not show competence anymore..
He admits he has not seen a design to look at
but critizises and kills it anyway.

His way of professional approach to design for his customers?
What a piece of BS.
If a new design approach is described, it cannot be finished, otherwise it would not ne new by definition.
Please tell us more, so people here ( except Rick obviously ) can better understand, appreciate or even replicate.

As you state you use parts of Diamond anyway - so you know this Lattice tool for your FPGAs,
but your approach must have the advantages you describe.

To avoid misunderstandings, you should probably say " Forth-to-Gates including some Diamond" - ForthHDL.
And HDL rather than VHDL.
I cannot understand Rick's obsession to get the VHSIC Hardware Description Language in again and again
https://en.wikipedia.org/wiki/VHDL
I wonder how many here would know what VHSIC means ...

Please show us more as you have time.

Click here to read the complete article

Re: FPGA4th

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Subject: Re: FPGA4th
From: waynemor...@gmail.com (Wayne morellini)
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by: Wayne morellini - Mon, 17 Oct 2022 06:51 UTC

On Monday, October 17, 2022 at 6:22:36 AM UTC+10, johnro...@gmail.com wrote:
> \ Op Code File for MFX. Generated by MAKE-OPS v13
...
> Each to their own. I've spent too much time on this, got to get back to work.
> > Verilog already describes *the desired behaviour of any number of parallel processes, clocked or flow-through*.
> >I don't see a need for an exotic "Forth" front end (to generate what?).
> I don't know. You tell me.

John. Wayne here. I can't really read what you have done, as I've had a covid induced toxoplasma neurological spread from low immune system. But I encourage you here, as it is always good to have people that can design something new and practical. These things may at first often not look so practical in the light of present standards, but time will tell. As I posted many years ago, I had a desire to make the first game system with a hardware description language extension, as a way to put it in performance competition at reduced price with major players. Of course, I heard the same objections. But, when you do a deal with the supplier to have a setup where you have software that allows description generation for the single type of fpga in the system, such objections do not apply. But, as a general fpga description language, this message s something fpga manufacturers can get behind. There was a big push before for such tools to take an C language program and convert to DSP, fpga and GPU etc, to distribute the functionality accross the computer environment. So, you are on the money there. A combination of a minimal CPU core and fpga is very dynamic, considering how little space such cpu can take up, and speed and low energy they can take up. So thinkers and solution finders welcome, for my part. It's much more exciting to hear how somebody conquered a new problem/solution then to listen to objections to trying to solve things in a new way. In the end such things can have unforseen/misunderstood benefits. Your practical success of the years, shows that the bulk of the work, from your intuition, was right from the beginning. Not trying to blow up your head or anything, but it is the principle of the inventive process that others do not get. Tesla, the great Japanese inventor )whoes name escapes me at the moment) etc got this, producing volumes of foundation in short periods I can't say the same for other popularised Business men, who were called "genius" for attaching their names to others work, who were really like the level skilled of lab assistants, able to practically build on others foundational work, but not able to really do very much foundational work themselves.

One day, we might get a developers think tank like forum up and running, and it would be good to have people such as yourself along, and some practical builders (please be warned though, we are thinking of inviting a certain member due to his passionate foresight). :)

We can all do more foundational work together than divided.

Thanks.

Save gas, don't use the shell.

devel / comp.lang.forth / Re: FPGA4th

Subject	Author
FPGA4th	John Hart
Re: FPGA4th	Jurgen Pitaske
Re: FPGA4th	A.T. Murray
Re: FPGA4th	Brian Fox
Re: FPGA4th	Hugh Aguilar
Re: FPGA4th	John Hart
Re: FPGA4th	Jurgen Pitaske
Re: FPGA4th	John Hart
Re: FPGA4th	Jurgen Pitaske
Re: FPGA4th	Jurgen Pitaske
Re: FPGA4th	Lorem Ipsum
Re: FPGA4th	Jurgen Pitaske
Re: FPGA4th	Lorem Ipsum
Re: FPGA4th	Jurgen Pitaske
Re: FPGA4th	Jurgen Pitaske
Re: FPGA4th	Lorem Ipsum
Re: FPGA4th	Jurgen Pitaske
Re: FPGA4th	Lorem Ipsum
Re: FPGA4th	Jurgen Pitaske
Re: FPGA4th	Lorem Ipsum
Re: FPGA4th	Jurgen Pitaske
Re: FPGA4th	John Hart
Re: FPGA4th	Jurgen Pitaske
Re: FPGA4th	Wayne morellini
Re: FPGA4th	Myron Plichota
Re: FPGA4th	John Hart
Re: FPGA4th	Lorem Ipsum
Re: FPGA4th	none
Re: FPGA4th	Lorem Ipsum
Re: FPGA4th	Jurgen Pitaske
Re: FPGA4th	dxforth
Re: FPGA4th	Lorem Ipsum
Re: FPGA4th	Wayne morellini
Re: FPGA4th	dxforth
Re: FPGA4th	Wayne morellini
Re: FPGA4th	dxforth
Re: FPGA4th	S
Re: FPGA4th	dxforth
Re: FPGA4th	S
Re: FPGA4th	dxforth
Re: FPGA4th	S 1
Re: FPGA4th	dxforth
Re: FPGA4th	S 1
Re: FPGA4th	dxforth
Re: FPGA4th	S
Re: FPGA4th	dxforth
Re: FPGA4th	Jurgen Pitaske
Re: FPGA4th	Wayne morellini
Re: FPGA4th	Wayne morellini
Re: FPGA4th	none
Re: FPGA4th	John Hart
Re: FPGA4th	Jurgen Pitaske
Re: FPGA4th	John Hart
Re: FPGA4th	Jurgen Pitaske
Re: FPGA4th	Lorem Ipsum
Re: FPGA4th	John Hart
Re: FPGA4th	Lorem Ipsum
Re: FPGA4th	Jurgen Pitaske
Re: FPGA4th	Lorem Ipsum
Re: FPGA4th	Jurgen Pitaske
Re: FPGA4th	John Hart
Re: FPGA4th	Hugh Aguilar
Re: FPGA4th	Jurgen Pitaske
Re: FPGA4th	none
Re: FPGA4th	S 1
Re: FPGA4th	John Hart
Re: FPGA4th	Hugh Aguilar
Re: FPGA4th	Jurgen Pitaske
Re: FPGA4th	John Hart
Re: FPGA4th	Jurgen Pitaske
Re: FPGA4th	Hugh Aguilar
Re: FPGA4th	Jurgen Pitaske
Re: FPGA4th	Jurgen Pitaske
Re: FPGA4th	Jurgen Pitaske
Re: FPGA4th	Lorem Ipsum
Re: FPGA4th	Jurgen Pitaske
Re: FPGA4th	dxforth
Re: FPGA4th	Jurgen Pitaske
Re: FPGA4th	Jurgen Pitaske
Re: FPGA4th	Hugh Aguilar
Re: FPGA4th	dxforth
Re: FPGA4th	Anton Ertl
Re: FPGA4th	dxforth
Re: FPGA4th	Anton Ertl
Re: FPGA4th	dxforth
Re: FPGA4th	Jurgen Pitaske
Re: FPGA4th	dxforth
Re: FPGA4th	Lorem Ipsum
Re: FPGA4th	John Hart
Re: FPGA4th	Lorem Ipsum
Re: FPGA4th	Hugh Aguilar
Re: FPGA4th	Jurgen Pitaske
Re: FPGA4th	John Hart
Re: FPGA4th	Lorem Ipsum
Re: FPGA4th	Jurgen Pitaske
Re: FPGA4th	John Hart
Re: FPGA4th	Jurgen Pitaske
Re: FPGA4th	Jurgen Pitaske
Re: FPGA4th	John Hart
Re: FPGA4th	Hugh Aguilar
Re: FPGA4th	Jurgen Pitaske
Re: FPGA4th	Hugh Aguilar
Re: FPGA4th	Hugh Aguilar