On Tuesday, April 25, 2023 at 10:21:10 AM UTC-7, Jurgen Pitaske wrote:
> On Tuesday, 25 April 2023 at 18:13:11 UTC+1, John Hart wrote:
> > On Thursday, November 25, 2021 at 2:39:20 AM UTC-7, Jurgen Pitaske wrote:
> > <clip>
> > > Thank you very much John - let's see what happens next.
> > > Just for the fun of it I formatted it slightly in a way that makes the blocks a bit clearer to me
> > > https://www.dropbox.com/sh/ah8umk0hgq1818s/AAC8nNEueZZcIYJ8uGP4F4wPa?dl=0
> >
> > Finally getting close to finishing the development system and the processor.
> >
> > The original design was for a FPLD not a FPGA. After we moved the design to a FPGA it became obvious
> > a major re-design was needed. PLD's are optimized for parallel operations and we were able to convert
> > forth code directly to logic for the design, but FPGA's require something more complex, so I decided to
> > build a map generator before beginning the project.
> Looking forward to more ...
>
> And I just checked the dropbox link - still works.
> I hope the formatting was helpful.

I might provide the current instruction set in a more useful form after our product is finished, if there's any
interest. It's a universal 16 axis motion control system with two syncronized PWM outputs for laser, plasma,
3D printer, etc control.

After the processor is finished I was thinking about releasing the development tool in an open source format.
To perfect it will require a joint effort. Reconfigurable Processors have many advantages over fixed ones and
a variable instruction set could provide a level of security that would be very difficult to crack.

On 27/04/2023 4:07 am, Hugh Aguilar wrote:
>
> I wrote MFX in 32-bit UR/Forth under a DOS-extender
> in 1994. I was told that Testra had the sign an NDA for Ray Duncan in order to
> obtain the UR/Forth source-code. Since that time, Testra has upgraded UR/Forth
> to run under Windows, so they could continue to use UR/Forth all the way to 2023.
> The NDA is still in effect. Testra can't distribute MFX or any of the other development
> tools to anybody who doesn't also sign the NDA for Ray Duncan.

It was true when they signed it. IP needs to be enforced and it's not clear who -
if anyone - owns LMI's IP today. Certainly no one other than yourself has come
forward to insist LMI's IP be respected. Much like the priest who speaks for a
God that can be seen or felt, threatening destruction if they don't get it.

On Wednesday, April 26, 2023 at 8:59:22 PM UTC-4, John Hart wrote:
> On Tuesday, April 25, 2023 at 6:23:15 PM UTC-7, Lorem Ipsum wrote:
> > On Tuesday, April 25, 2023 at 1:13:11 PM UTC-4, John Hart wrote:
> > > On Thursday, November 25, 2021 at 2:39:20 AM UTC-7, Jurgen Pitaske wrote:
> > > <clip>
> <clip>
> > > The original design was for a FPLD not a FPGA. After we moved the design to a FPGA it became obvious
> > > a major re-design was needed. PLD's are optimized for parallel operations and we were able to convert
> > > forth code directly to logic for the design, but FPGA's require something more complex, so I decided to
> > > build a map generator before beginning the project.
> > What additional complexity do FPGAs require over CPLD? I literally have no idea what that means. You can use the same HDL code that was written for a CPLD (assuming there's a compiler for it) and compile that for an FPGA.
> >
> > I can't think of anything that is harder to do in an FPGA than in a CPLD, unless CPLDs have something akin to "long lines" which FPGAs used to use, until they grew out of them with logic being faster.
> >
> > There is nothing about FPGAs to preclude or make harder parallel operations. FPGAs are the embodiment of parallel operations. Every component on an FPGA operates in parallel with all the others, unless you tie them to sequential operations in your code.
> > Rick C.
>
> The basic logic unit of a FPGA is a LUT, typically 4 or 5 inputs. The basic logic unit of a CPGA has 16 to 20 inputs.
> A 5 input LUT can decode all possible inputs, the basic logic unit of a FPGA, only 4 to 20. A large adder in a CPLD
> is next to impossible, in a FPGA a simple task and with carry logic, trivial. The ALU in our Forth CPLD processor was
> 4 bits. Todays FPGAs outperform CPLDs to the point they're obsolete.

I don't disagree with what you write. I just don't understand how it relates to the statement, "FPGA's require something more complex".

My understanding is that a CPLD is hard to program complex functions in, while is it much less difficult to do so in an FPGA. Are you trying to say that it's only worthwhile to use FPGAs for more complex logic?

--

Rick C.

--+- Get 1,000 miles of free Supercharging
--+- Tesla referral code - https://ts.la/richard11209

On Thursday, 27 April 2023 at 02:47:37 UTC+1, Lorem Ipsum wrote:
> On Wednesday, April 26, 2023 at 8:59:22 PM UTC-4, John Hart wrote:
> > On Tuesday, April 25, 2023 at 6:23:15 PM UTC-7, Lorem Ipsum wrote:
> > > On Tuesday, April 25, 2023 at 1:13:11 PM UTC-4, John Hart wrote:
> > > > On Thursday, November 25, 2021 at 2:39:20 AM UTC-7, Jurgen Pitaske wrote:
> > > > <clip>
> > <clip>
> > > > The original design was for a FPLD not a FPGA. After we moved the design to a FPGA it became obvious
> > > > a major re-design was needed. PLD's are optimized for parallel operations and we were able to convert
> > > > forth code directly to logic for the design, but FPGA's require something more complex, so I decided to
> > > > build a map generator before beginning the project.
> > > What additional complexity do FPGAs require over CPLD? I literally have no idea what that means. You can use the same HDL code that was written for a CPLD (assuming there's a compiler for it) and compile that for an FPGA.
> > >
> > > I can't think of anything that is harder to do in an FPGA than in a CPLD, unless CPLDs have something akin to "long lines" which FPGAs used to use, until they grew out of them with logic being faster.
> > >
> > > There is nothing about FPGAs to preclude or make harder parallel operations. FPGAs are the embodiment of parallel operations. Every component on an FPGA operates in parallel with all the others, unless you tie them to sequential operations in your code.
> > > Rick C.
> >
> > The basic logic unit of a FPGA is a LUT, typically 4 or 5 inputs. The basic logic unit of a CPGA has 16 to 20 inputs.
> > A 5 input LUT can decode all possible inputs, the basic logic unit of a FPGA, only 4 to 20. A large adder in a CPLD
> > is next to impossible, in a FPGA a simple task and with carry logic, trivial. The ALU in our Forth CPLD processor was
> > 4 bits. Todays FPGAs outperform CPLDs to the point they're obsolete.
> I don't disagree with what you write. I just don't understand how it relates to the statement, "FPGA's require something more complex".
>
> My understanding is that a CPLD is hard to program complex functions in, while is it much less difficult to do so in an FPGA. Are you trying to say that it's only worthwhile to use FPGAs for more complex logic?
>
> --
>
> Rick C.
>
> --+- Get 1,000 miles of free Supercharging
> --+- Tesla referral code - https://ts.la/richard11209

It is not clear to anybody here why you are just adding useless noise here ..

If you do not know what CPLD / FPGA means
- there is a so called internet where you can find the information and understanding you are missing.
Or build your own.
In hardware
as CPLD for practice
Or in FPGA - here go to NandLand invest the money and start programming
or dig out the TTLs you should still have and build your own
http://blog.notdot.net/2012/10/Build-your-own-FPGA

On Thursday, 27 April 2023 at 02:17:33 UTC+1, John Hart wrote:
> On Tuesday, April 25, 2023 at 10:21:10 AM UTC-7, Jurgen Pitaske wrote:
> > On Tuesday, 25 April 2023 at 18:13:11 UTC+1, John Hart wrote:
> > > On Thursday, November 25, 2021 at 2:39:20 AM UTC-7, Jurgen Pitaske wrote:
> > > <clip>
> > > > Thank you very much John - let's see what happens next.
> > > > Just for the fun of it I formatted it slightly in a way that makes the blocks a bit clearer to me
> > > > https://www.dropbox.com/sh/ah8umk0hgq1818s/AAC8nNEueZZcIYJ8uGP4F4wPa?dl=0
> > >
> > > Finally getting close to finishing the development system and the processor.
> > >
> > > The original design was for a FPLD not a FPGA. After we moved the design to a FPGA it became obvious
> > > a major re-design was needed. PLD's are optimized for parallel operations and we were able to convert
> > > forth code directly to logic for the design, but FPGA's require something more complex, so I decided to
> > > build a map generator before beginning the project.
> > Looking forward to more ...
> >
> > And I just checked the dropbox link - still works.
> > I hope the formatting was helpful.

> I might provide the current instruction set in a more useful form after our product is finished, if there's any
> interest. It's a universal 16 axis motion control system with two syncronized PWM outputs for laser, plasma,
> 3D printer, etc control.
>
> After the processor is finished I was thinking about releasing the development tool in an open source format.
> To perfect it will require a joint effort. Reconfigurable Processors have many advantages over fixed ones and
> a variable instruction set could provide a level of security that would be very difficult to crack.

An option might be to release the older CPLD version first,
which is probably not used anymore ( if the chip is still available )
as it is probably easier to understand.

I look really forward to more from you.
And this might as well enlighten the post on your website about Forth to FPGA

On Thursday, April 27, 2023 at 2:18:16 AM UTC-4, Jurgen Pitaske wrote:
> On Thursday, 27 April 2023 at 02:47:37 UTC+1, Lorem Ipsum wrote:
> > On Wednesday, April 26, 2023 at 8:59:22 PM UTC-4, John Hart wrote:
> > > On Tuesday, April 25, 2023 at 6:23:15 PM UTC-7, Lorem Ipsum wrote:
> > > > On Tuesday, April 25, 2023 at 1:13:11 PM UTC-4, John Hart wrote:
> > > > > On Thursday, November 25, 2021 at 2:39:20 AM UTC-7, Jurgen Pitaske wrote:
> > > > > <clip>
> > > <clip>
> > > > > The original design was for a FPLD not a FPGA. After we moved the design to a FPGA it became obvious
> > > > > a major re-design was needed. PLD's are optimized for parallel operations and we were able to convert
> > > > > forth code directly to logic for the design, but FPGA's require something more complex, so I decided to
> > > > > build a map generator before beginning the project.
> > > > What additional complexity do FPGAs require over CPLD? I literally have no idea what that means. You can use the same HDL code that was written for a CPLD (assuming there's a compiler for it) and compile that for an FPGA.
> > > >
> > > > I can't think of anything that is harder to do in an FPGA than in a CPLD, unless CPLDs have something akin to "long lines" which FPGAs used to use, until they grew out of them with logic being faster.
> > > >
> > > > There is nothing about FPGAs to preclude or make harder parallel operations. FPGAs are the embodiment of parallel operations. Every component on an FPGA operates in parallel with all the others, unless you tie them to sequential operations in your code.
> > > > Rick C.
> > >
> > > The basic logic unit of a FPGA is a LUT, typically 4 or 5 inputs. The basic logic unit of a CPGA has 16 to 20 inputs.
> > > A 5 input LUT can decode all possible inputs, the basic logic unit of a FPGA, only 4 to 20. A large adder in a CPLD
> > > is next to impossible, in a FPGA a simple task and with carry logic, trivial. The ALU in our Forth CPLD processor was
> > > 4 bits. Todays FPGAs outperform CPLDs to the point they're obsolete.
> > I don't disagree with what you write. I just don't understand how it relates to the statement, "FPGA's require something more complex".
> >
> > My understanding is that a CPLD is hard to program complex functions in, while is it much less difficult to do so in an FPGA. Are you trying to say that it's only worthwhile to use FPGAs for more complex logic?
> >
> > --
> >
> > Rick C.
> >
> > --+- Get 1,000 miles of free Supercharging
> > --+- Tesla referral code - https://ts.la/richard11209
> It is not clear to anybody here why you are just adding useless noise here .
>
> If you do not know what CPLD / FPGA means
> - there is a so called internet where you can find the information and understanding you are missing.
> Or build your own.
> In hardware
> as CPLD for practice
> Or in FPGA - here go to NandLand invest the money and start programming
> or dig out the TTLs you should still have and build your own
> http://blog.notdot.net/2012/10/Build-your-own-FPGA

Thank you for your kind words of support and encouragement. Everyone says how marvelous it is that we have you to guide us and teach us.

I feel wiser, just having read your remarks.

--

Rick C.

--++ Get 1,000 miles of free Supercharging
--++ Tesla referral code - https://ts.la/richard11209

On Wednesday, April 26, 2023 at 6:47:37 PM UTC-7, Lorem Ipsum wrote:
> On Wednesday, April 26, 2023 at 8:59:22 PM UTC-4, John Hart wrote:
> > On Tuesday, April 25, 2023 at 6:23:15 PM UTC-7, Lorem Ipsum wrote:
> > > On Tuesday, April 25, 2023 at 1:13:11 PM UTC-4, John Hart wrote:
> > > > On Thursday, November 25, 2021 at 2:39:20 AM UTC-7, Jurgen Pitaske wrote:
> > > > <clip>
> > <clip>
> > > > The original design was for a FPLD not a FPGA. After we moved the design to a FPGA it became obvious
> > > > a major re-design was needed. PLD's are optimized for parallel operations and we were able to convert
> > > > forth code directly to logic for the design, but FPGA's require something more complex, so I decided to
> > > > build a map generator before beginning the project.
> > > What additional complexity do FPGAs require over CPLD? I literally have no idea what that means. You can use the same HDL code that was written for a CPLD (assuming there's a compiler for it) and compile that for an FPGA.
> > >
> > > I can't think of anything that is harder to do in an FPGA than in a CPLD, unless CPLDs have something akin to "long lines" which FPGAs used to use, until they grew out of them with logic being faster.
> > >
> > > There is nothing about FPGAs to preclude or make harder parallel operations. FPGAs are the embodiment of parallel operations. Every component on an FPGA operates in parallel with all the others, unless you tie them to sequential operations in your code.
> > > Rick C.
> >
> > The basic logic unit of a FPGA is a LUT, typically 4 or 5 inputs. The basic logic unit of a CPGA has 16 to 20 inputs.
> > A 5 input LUT can decode all possible inputs, the basic logic unit of a FPGA, only 4 to 20. A large adder in a CPLD
> > is next to impossible, in a FPGA a simple task and with carry logic, trivial. The ALU in our Forth CPLD processor was
> > 4 bits. Todays FPGAs outperform CPLDs to the point they're obsolete.
> I don't disagree with what you write. I just don't understand how it relates to the statement, "FPGA's require something more complex".
>
> My understanding is that a CPLD is hard to program complex functions in, while is it much less difficult to do so in an FPGA. Are you trying to say that it's only worthwhile to use FPGAs for more complex logic?

> Rick C.
Not at all. Today FPGAs are better than PLDs for most everything, even small jobs. Our PLD based processer was written in Forth and mapped directly into logic equations that fit the format of the PLD. When we moved the design to the FPGA the
logic compiler had to factor the equations into pieces that would fit in LUTs. Optimization for a PLD is the opposite of
optimizastion for a FPGA. Minimizing terms, which was very important for the PLD, was completely useless. Compile time was long and it required hand optimization to reach the performance goal.

Our new processor is more complex and experience told me better tools would be necessary to complete the project, so
I spent more time on tools than the design at first. There are many parts to the FPGA4th system that produces
VERILOG code for data and control of modules , I/O pin assignments, and definition of the instruction set for the assembler.
The part that converts the instruction set into equations was the hardest and might be simplified by re-doing it without recursion.

On Thursday, 27 April 2023 at 07:33:08 UTC+1, Lorem Ipsum wrote:
> On Thursday, April 27, 2023 at 2:18:16 AM UTC-4, Jurgen Pitaske wrote:
> > On Thursday, 27 April 2023 at 02:47:37 UTC+1, Lorem Ipsum wrote:
> > > On Wednesday, April 26, 2023 at 8:59:22 PM UTC-4, John Hart wrote:
> > > > On Tuesday, April 25, 2023 at 6:23:15 PM UTC-7, Lorem Ipsum wrote:
> > > > > On Tuesday, April 25, 2023 at 1:13:11 PM UTC-4, John Hart wrote:
> > > > > > On Thursday, November 25, 2021 at 2:39:20 AM UTC-7, Jurgen Pitaske wrote:
> > > > > > <clip>
> > > > <clip>
> > > > > > The original design was for a FPLD not a FPGA. After we moved the design to a FPGA it became obvious
> > > > > > a major re-design was needed. PLD's are optimized for parallel operations and we were able to convert
> > > > > > forth code directly to logic for the design, but FPGA's require something more complex, so I decided to
> > > > > > build a map generator before beginning the project.
> > > > > What additional complexity do FPGAs require over CPLD? I literally have no idea what that means. You can use the same HDL code that was written for a CPLD (assuming there's a compiler for it) and compile that for an FPGA.
> > > > >
> > > > > I can't think of anything that is harder to do in an FPGA than in a CPLD, unless CPLDs have something akin to "long lines" which FPGAs used to use, until they grew out of them with logic being faster.
> > > > >
> > > > > There is nothing about FPGAs to preclude or make harder parallel operations. FPGAs are the embodiment of parallel operations. Every component on an FPGA operates in parallel with all the others, unless you tie them to sequential operations in your code.
> > > > > Rick C.
> > > >
> > > > The basic logic unit of a FPGA is a LUT, typically 4 or 5 inputs. The basic logic unit of a CPGA has 16 to 20 inputs.
> > > > A 5 input LUT can decode all possible inputs, the basic logic unit of a FPGA, only 4 to 20. A large adder in a CPLD
> > > > is next to impossible, in a FPGA a simple task and with carry logic, trivial. The ALU in our Forth CPLD processor was
> > > > 4 bits. Todays FPGAs outperform CPLDs to the point they're obsolete..
> > > I don't disagree with what you write. I just don't understand how it relates to the statement, "FPGA's require something more complex".
> > >
> > > My understanding is that a CPLD is hard to program complex functions in, while is it much less difficult to do so in an FPGA. Are you trying to say that it's only worthwhile to use FPGAs for more complex logic?
> > >
> > > --
> > >
> > > Rick C.
> > >
> > > --+- Get 1,000 miles of free Supercharging
> > > --+- Tesla referral code - https://ts.la/richard11209
> > It is not clear to anybody here why you are just adding useless noise here .
> >
> > If you do not know what CPLD / FPGA means
> > - there is a so called internet where you can find the information and understanding you are missing.
> > Or build your own.
> > In hardware
> > as CPLD for practice
> > Or in FPGA - here go to NandLand invest the money and start programming
> > or dig out the TTLs you should still have and build your own
> > http://blog.notdot.net/2012/10/Build-your-own-FPGA
> Thank you for your kind words of support and encouragement. Everyone says how marvelous it is that we have you to guide us and teach us.
>
> I feel wiser, just having read your remarks.
>
> --
>
> Rick C.
>
> --++ Get 1,000 miles of free Supercharging
> --++ Tesla referral code - https://ts.la/richard11209

I do appreciate your sarcasm.

But looking at Rick Collins on LinkedIN again now
https://www.linkedin.com/in/ariusinc/
it states there:

About
Digital and analog board level design and production with DSP and FPGA in Verlog/VHDL with embedded software.

A current design that Arius is producing for a major communications company is an IRIG-B/Audio interface for their IP networking equipment.
This product has passed acceptance testing and Arius, Inc is now producing these units for sale in our customer's equipment.

We utilize an optimal combination of tried and tested approaches with state of the art technology to deliver low cost solutions meeting our customer's cost, schedule and design goals.

Specialties: FPGA design (Xilinx, Altera, Lattice), VHDL, Verilog
High speed digital circuit board design
Analog circuit design
ARM7 and Cortex M3 software development
TMS320C6xxx and TMS320C5xxx processor design
Low Power
Miniaturization
Prototyping
Volume Production
Automated Testing

So, I hope you were able to understand that my post contsained a bit of sarcasm as well ...

On Wednesday, April 26, 2023 at 5:59:22 PM UTC-7, John Hart wrote:
> On Tuesday, April 25, 2023 at 6:23:15 PM UTC-7, Lorem Ipsum wrote:
> > I can't think of anything that is harder to do in an FPGA than in a CPLD,
> > unless CPLDs have something akin to "long lines" which FPGAs used to use,
> > until they grew out of them with logic being faster.
> >
> > There is nothing about FPGAs to preclude or make harder parallel operations.
> > FPGAs are the embodiment of parallel operations. Every component on an
> > FPGA operates in parallel with all the others, unless you tie them to sequential
> > operations in your code.
> > Rick C.
>
> The basic logic unit of a FPGA is a LUT, typically 4 or 5 inputs.
> The basic logic unit of a CPGA has 16 to 20 inputs.
> A 5 input LUT can decode all possible inputs, the basic logic unit of a FPGA,
> only 4 to 20.

The Lattice isp1048 PLD had a lot more connectivity than a modern FPGA.
This is why a VLIW design on the PLD was possible, but is impossible on an FPGA.
Rick Collins is a clown because he doesn't understand this. He says that a VLIW
is easy on an FPGA, although he has never done this. He's fantasizing.

The strength of an FPGA is that they "are the embodiment of parallel operations."
This has to be loosely-coupled parallelism to avoid the connectivity problem.
This is why all modern FPGA designs are multi-core systems.
John Hart is a clown because he doesn't because he doesn't understand this. He says
that his single-core RACE processor is relevant in modern times, but it isn't.

The MiniForth was pretty awesome in 1995 when it came out.
If I had continued building upon MFX I could have made it successful, at least for a while.
A VLIW processor is obsolete now (this might still be possible in an ASIC, though).

The truth that John Hart dodges is that I did write MFX.
He contributed only bad advice that I ignored (he expected the application programmer
to do the out-of-ordering, but I wrote MFX to do this automatically).
I was being a team player by succeeding at writing MFX despite the abysmally low pay,
lack of health insurance and lack of support (no advice whatsoever on how to do this).
Testra totally betrayed me by refusing to admit that I wrote MFX, telling everybody that
I was a stupid little maintenance programmer who pretends to have written MFX that I used
but that real programmers (John Hart and Steve Brault) actually wrote.
Nobody will ever hire a liar!

Nobody should hire Testra because Tom Hart and John Hart are liars.
The problem is not just that their single-core processor is obsolete in the 21st century,
the problem is that they betrayed their employee in 1995, and continue to do this today.
Nobody will ever agree to be their employee when the result is certain betrayal.

On Friday, 28 April 2023 at 03:44:11 UTC+1, Hugh Aguilar wrote:
> On Wednesday, April 26, 2023 at 5:59:22 PM UTC-7, John Hart wrote:
> > On Tuesday, April 25, 2023 at 6:23:15 PM UTC-7, Lorem Ipsum wrote:
> > > I can't think of anything that is harder to do in an FPGA than in a CPLD,
> > > unless CPLDs have something akin to "long lines" which FPGAs used to use,
> > > until they grew out of them with logic being faster.
> > >
> > > There is nothing about FPGAs to preclude or make harder parallel operations.
> > > FPGAs are the embodiment of parallel operations. Every component on an
> > > FPGA operates in parallel with all the others, unless you tie them to sequential
> > > operations in your code.
> > > Rick C.
> >
> > The basic logic unit of a FPGA is a LUT, typically 4 or 5 inputs.
> > The basic logic unit of a CPGA has 16 to 20 inputs.
> > A 5 input LUT can decode all possible inputs, the basic logic unit of a FPGA,
> > only 4 to 20.
> The Lattice isp1048 PLD had a lot more connectivity than a modern FPGA.
> This is why a VLIW design on the PLD was possible, but is impossible on an FPGA.
> Rick Collins is a clown because he doesn't understand this. He says that a VLIW
> is easy on an FPGA, although he has never done this. He's fantasizing.
>
> The strength of an FPGA is that they "are the embodiment of parallel operations."
> This has to be loosely-coupled parallelism to avoid the connectivity problem.
> This is why all modern FPGA designs are multi-core systems.
> John Hart is a clown because he doesn't because he doesn't understand this. He says
> that his single-core RACE processor is relevant in modern times, but it isn't.
>
> The MiniForth was pretty awesome in 1995 when it came out.
> If I had continued building upon MFX I could have made it successful, at least for a while.
> A VLIW processor is obsolete now (this might still be possible in an ASIC, though).
>
> The truth that John Hart dodges is that I did write MFX.
> He contributed only bad advice that I ignored (he expected the application programmer
> to do the out-of-ordering, but I wrote MFX to do this automatically).
> I was being a team player by succeeding at writing MFX despite the abysmally low pay,
> lack of health insurance and lack of support (no advice whatsoever on how to do this).
> Testra totally betrayed me by refusing to admit that I wrote MFX, telling everybody that
> I was a stupid little maintenance programmer who pretends to have written MFX that I used
> but that real programmers (John Hart and Steve Brault) actually wrote.
> Nobody will ever hire a liar!
>
> Nobody should hire Testra because Tom Hart and John Hart are liars.
> The problem is not just that their single-core processor is obsolete in the 21st century,
> the problem is that they betrayed their employee in 1995, and continue to do this today.
> Nobody will ever agree to be their employee when the result is certain betrayal.

Hugh, stop accusing others and call them liars without any proof,
and go back into your mental home.
And close the door behind you and lock it.
And throw the key through the window.

If their product is old or new does not matter
- does it do the job and do people buy it.
Customers did this over the last 30 yeears.

Testra is a company successful for 30 years at least now.
Accusing others is just your usual bullshit.

If they did not pay you enough?
Why did you not just leave and get double the salary elswhere.

You should get back into your taxi or drive the tractor. Or plumbing as you said.
This would make sure you do not waste our time here.
I AM PISSED OFF WITH YOUR CONTINUOUS BULLSHIT AND ACCUSATIONS.

In article <474678ef-ab80-411a-ae7f-60e2c3fe1f51n@googlegroups.com>,
Hugh Aguilar <hughaguilar96@gmail.com> wrote:
<SNIP>
>Nobody should hire Testra because Tom Hart and John Hart are liars.

Are that the Hart's you have worked for? The Hart's that keep a company
running for decennia while you were plumbing are tax-driving?

Groetjes Albert
--
Don't praise the day before the evening. One swallow doesn't make spring.
You must not say "hey" before you have crossed the bridge. Don't sell the
hide of the bear until you shot it. Better one bird in the hand than ten in
the air. First gain is a cat spinning. - the Wise from Antrim -

On Friday, 28 April 2023 at 12:44:11 pm UTC+10, Hugh Aguilar wrote:
> On Wednesday, April 26, 2023 at 5:59:22 PM UTC-7, John Hart wrote:
> > On Tuesday, April 25, 2023 at 6:23:15 PM UTC-7, Lorem Ipsum wrote:
> > > I can't think of anything that is harder to do in an FPGA than in a CPLD,
> > > unless CPLDs have something akin to "long lines" which FPGAs used to use,
> > > until they grew out of them with logic being faster.
> > >
> > > There is nothing about FPGAs to preclude or make harder parallel operations.
> > > FPGAs are the embodiment of parallel operations. Every component on an
> > > FPGA operates in parallel with all the others, unless you tie them to sequential
> > > operations in your code.
> > > Rick C.
> >
> > The basic logic unit of a FPGA is a LUT, typically 4 or 5 inputs.
> > The basic logic unit of a CPGA has 16 to 20 inputs.
> > A 5 input LUT can decode all possible inputs, the basic logic unit of a FPGA,
> > only 4 to 20.
> The Lattice isp1048 PLD had a lot more connectivity than a modern FPGA.
> This is why a VLIW design on the PLD was possible, but is impossible on an FPGA.
> Rick Collins is a clown because he doesn't understand this. He says that a VLIW
> is easy on an FPGA, although he has never done this. He's fantasizing.

What, are you saying that Rick is a clown who doesn't understand something?

But, normally in something like this, I would normally listen to Rick. Because he is supposed to know it, even though I seem to understand it better.

I remember being berated for thinking I could put a simple microprocessor on a pld like device, but now he admits it's doable and done.

>
> The strength of an FPGA is that they "are the embodiment of parallel operations."
> This has to be loosely-coupled parallelism to avoid the connectivity problem.
> This is why all modern FPGA designs are multi-core systems.
> John Hart is a clown because he doesn't because he doesn't understand this. He says
> that his single-core RACE processor is relevant in modern times, but it isn't.
>
> The MiniForth was pretty awesome in 1995 when it came out.
> If I had continued building upon MFX I could have made it successful, at least for a while.
> A VLIW processor is obsolete now (this might still be possible in an ASIC, though).
>
> The truth that John Hart dodges is that I did write MFX.
> He contributed only bad advice that I ignored (he expected the application programmer
> to do the out-of-ordering, but I wrote MFX to do this automatically).
> I was being a team player by succeeding at writing MFX despite the abysmally low pay,
> lack of health insurance and lack of support (no advice whatsoever on how to do this).
> Testra totally betrayed me by refusing to admit that I wrote MFX, telling everybody that
> I was a stupid little maintenance programmer who pretends to have written MFX that I used
> but that real programmers (John Hart and Steve Brault) actually wrote.
> Nobody will ever hire a liar!
>
> Nobody should hire Testra because Tom Hart and John Hart are liars.
> The problem is not just that their single-core processor is obsolete in the 21st century,
> the problem is that they betrayed their employee in 1995, and continue to do this today.
> Nobody will ever agree to be their employee when the result is certain betrayal.

On Thursday, April 27, 2023 at 7:44:11 PM UTC-7, Hugh Aguilar wrote:
> On Wednesday, April 26, 2023 at 5:59:22 PM UTC-7, John Hart wrote:
> > On Tuesday, April 25, 2023 at 6:23:15 PM UTC-7, Lorem Ipsum wrote:
> > > I can't think of anything that is harder to do in an FPGA than in a CPLD,
<clip>
> > > There is nothing about FPGAs to preclude or make harder parallel operations.
<clip>
> > > Rick C.
> >
> > The basic logic unit of a FPGA is a LUT, typically 4 or 5 inputs.
> > The basic logic unit of a CPGA has 16 to 20 inputs.
> > A 5 input LUT can decode all possible inputs, the basic logic unit of a FPGA,
> > only 4 to 20.
> The Lattice isp1048 PLD had a lot more connectivity than a modern FPGA.
Not true!
> This is why a VLIW design on the PLD was possible, but is impossible on an FPGA.
I don't know what a VLIW is, but I know anything possible on a PLD can be done better on a modern FPGA.
<ad hominem & nonsense clipped>

> A VLIW processor is obsolete now (this might still be possible in an ASIC, though).

Our original MSI LSI based processor (4S32) used in thousands ofTicketMaster terminals,
was a Harvard architecture with a 32 bit instruction (not sure if that qualifies as VLIW),
a 16 bit data path and 4 bit ALU. [An emulation of an Intel 286 (virtual PC) on it would
run a little faster than it. An emulation of a customers 16 bit processor ran 5 times faster.]

The Forth multi-user system we manufactured using the same CPU supported 7 users.
When we moved the design to the PLD ,the instruction width was shrunk to 16 bits, which
I'm sure doesn't qualify as a Very Large Instruction Width. The arithmetic part of the ALU
remained 4 bits but the logic part became 16.

The instruction word for the RACE32 is 18 bits, so it's not a VLIW either,
but the ALU and internal data path have been expanded to 32 bits, enabled by
the fast ripple carry feature of FPGAs.

The power of modern FPGA would blow people's minds, if they understood them..
Advanced supercomputer have tens of thousands of chips with thousands of processes
running in each one with more computing power than a PC. The fear about AAI taking
over the world is based on the reality of what can be done with this power
and how dangerous it would be if abused.

Restrictions won't reduce the danger, they'll make it more dangerous, more concentrated.
The solution to Big Tech having too much power is to empower people. Enable small business
to use robotics and automation to compete. Something like an open source platform programed
in Forth for automation would be the ideal tool to enable it. Focusing on solutions is the
only way out of the mess we're in, Attacks and flame wars are a DEAD END, they accomplish
NOTHING, and the din drowns out rational discourse.

HUGH WROTE MFX, never said he didn't. He was quite creative at the time.

<clip more ad hominem crap>

On Friday, April 28, 2023 at 11:56:23 AM UTC-7, John Hart wrote:
> On Thursday, April 27, 2023 at 7:44:11 PM UTC-7, Hugh Aguilar wrote:
> > On Wednesday, April 26, 2023 at 5:59:22 PM UTC-7, John Hart wrote:
> > > On Tuesday, April 25, 2023 at 6:23:15 PM UTC-7, Lorem Ipsum wrote:
> > > > I can't think of anything that is harder to do in an FPGA than in a CPLD,
> <clip>
> > > > There is nothing about FPGAs to preclude or make harder parallel operations.
> <clip>
> > > > Rick C.
> > >
> > > The basic logic unit of a FPGA is a LUT, typically 4 or 5 inputs.
> > > The basic logic unit of a CPGA has 16 to 20 inputs.
> > > A 5 input LUT can decode all possible inputs, the basic logic unit of a FPGA,
> > > only 4 to 20.
> > The Lattice isp1048 PLD had a lot more connectivity than a modern FPGA.
> Not true!
> > This is why a VLIW design on the PLD was possible, but is impossible on an FPGA.
> I don't know what a VLIW is, but I know anything possible on a PLD can be done better on a modern FPGA.

If you don't know what a VLIW is, then you presumably don't know what out-of-ordering
is either --- out-of-ordering is the distinctive feature of a VLIW.

You didn't know what out-of-ordering was in 1994 either.
You told me to write the assembler with each line representing one opcode, and all
five instructions that would be embedded in that opcode (and would execute
concurrently in a single clock cycle) on that line.
That was stupid!!! I remember at the time being stunned by the stupidity of your advice.
What I did was write the assembler so that the user would write his source-code as if
the instructions were executed sequentially, and my assembler would out-of-order
the instructions to pack them into the opcodes to minimize the number of NOP
instructions that had to be inserted while yet guaranteeing that the program did
the same thing as if the instructions were executed sequentially as they had been
written in the source-code. I got this idea from the Pentium with its U and V pipes.
MFX did the out-of-ordering at compile-time rather than run-time, so that was easier,
but the MiniForth had five instructions executing concurrently whereas the Pentium
only had two instructions executing concurrently (U and V), so that was more difficult.

You aren't any good at computer programming. You didn't understand out-of-ordering
in 1994, and you apparently still don't. All of your advice was stupid. I wrote all of the
code without any help at all, but now you take credit for writing it.

> The power of modern FPGA would blow people's minds, if they understood them.
> Advanced supercomputer have tens of thousands of chips with thousands of processes
> running in each one with more computing power than a PC. The fear about AAI taking
> over the world is based on the reality of what can be done with this power
> and how dangerous it would be if abused.

Only idiots watch the Terminator movies and take that nonsense seriously.
Apparently you are also a fan of the "Groundhog Day" movie.
This is a pathetic life. I recommend that you throw away your DVD player.

> HUGH WROTE MFX, never said he didn't. He was quite creative at the time.

You are lying, of course.
This is the first time that you have ever admitted in public that I wrote MFX.

I remember going to a job interview and the personnel lady called Testra on the
phone, and put it on speaker-phone so I could hear. The person who answered
at Testra identified himself as John Hart. He said that I had done "nothing"
in my time working there, and that I was not eligible for rehire.
Since then, you have claimed that this was actually Tom Hart impersonating you.
Maybe so! It doesn't matter though because you are 100% loyal to Tom Hart, so
when he puts words in your mouth those are your words, because you don't complain.
Note that this was at a time when you were trying to talk me into coming back to
work at Testra, so I was eligible for rehire. I think that your plan was to prevent me
from finding work elsewhere so that low finances would force me to return to Testra.
You didn't expect me to find out about this. I wouldn't have found out except that the
personnel lady put you on speaker phone, but that was unusual. As an example, I applied
at Lockheed Martin because they had a VLIW processor that they were using for
processing radar images. I went through two interviews and everything looked good.
I was told that they needed to verify at Testra, and then they would get back to me.
They got back to me and told me that I was disqualified for any job at Lockheed Martin.
Apparently you knew that Lockheed Martin would pay me more than $10/hour, and that
I wouldn't return to Testra, so you undermined my effort to get ahead in life.

After the incident with the speaker-phone, I never applied for work as a programmer again.
Writing MFX was my claim to fame. I needed that to get a job as a programmer.

Testra began attacking me on comp.lang.forth in 2019.
Tom Hart refused to admit that I wrote MFX (assembler/simulator and Forth cross-compiler).
Now in 2023 you finally admit that I wrote MFX, but you claim that you never
said that I didn't. Bullshit! You have been saying that you and Steve Brault wrote MFX
for the last three decades.

On Friday, September 13, 2019 at 9:08:59 AM UTC-7, Jurgen Pitaske wrote:
> The official answer from Tom Hart, their president,
> who agreed to have his answer to me published on clf:
>
> +++++++++++++++++++++++++++++++++++++++++++++++++++++++
> [Hugh] wrote our Forth compiler for the processor
> that we implemented in a Lattice PLD.
>
> He did a good job on it,
> we are still using it with a few bug fixes and minor modifications.
>
> He had nothing to do with the processor itself,
> that was all designed by John Hart and Steve Brault.
>
> The PLD version was based upon our original Forth Engine done long before
> we ever ran across Hugh.

Tom Hart is saying that MFX was written long before Testra ever ran across me.
Obviously, the assembler/simulator is an integral part of the MiniForth, so Tom Hart
is saying that I was never anything more than a stupid little maintenance programmer
who used MFX that was written by real programmers before I hired on.
He is effectively accusing me of lying when I say that I wrote MFX.

Tom Hart is giving me credit for writing the interactive Forth compiler. Bullshit!
That was written in MFX after I left. That required all of the assembly-language
to already be done because you can't have an assembler on the MiniForth due
to not being able to write to code-memory. Writing the interactive Forth compiler
would have been trivial because I had already written all of the primitives in
assembly-language. I also wrote the assembler.
When people read Tom Hart's lies they believe that there is no evidence to
indicate that I programmed in assembly-language, much less wrote the assembler.
They believe that I ported figForth over to the MiniForth. This is a lie, and you have
never contradicted your brother --- you have never stood up and told the truth.

Why did Testra attack me on comp.lang.forth with lies and insults?
Tom Hart made this attack on the command of Juergen Pintaske, the MPE salesman.
Apparently you were in negotiation with Stephen Pelc for him to buy the RACE processor,
and you believed that you had to obey Juergen Pintaske's commands to stay on
Stephen Pelc's good side. It is unlikely that Stephen Pelc was going to buy your RACE
processor. He was most likely just tugging your chain for the entertainment value of
getting you to attack your own employee on comp.lang.forth. You think that you can
totally crush me here on comp.lang.forth, but you harm yourself as much or more
than you harm me. Testra won't be considered to be a reputable company any more.
You have more to lose than I do. People who live in glass houses shouldn't throw stones!
Attacking me on comp.lang.forth was a bad idea. Was alcohol involved in this decision?

On Friday, April 28, 2023 at 2:56:23 PM UTC-4, John Hart wrote:
> On Thursday, April 27, 2023 at 7:44:11 PM UTC-7, Hugh Aguilar wrote:
> > On Wednesday, April 26, 2023 at 5:59:22 PM UTC-7, John Hart wrote:
> > > On Tuesday, April 25, 2023 at 6:23:15 PM UTC-7, Lorem Ipsum wrote:
> > > > I can't think of anything that is harder to do in an FPGA than in a CPLD,
> <clip>
> > > > There is nothing about FPGAs to preclude or make harder parallel operations.
> <clip>
> > > > Rick C.
> > >
> > > The basic logic unit of a FPGA is a LUT, typically 4 or 5 inputs.
> > > The basic logic unit of a CPGA has 16 to 20 inputs.
> > > A 5 input LUT can decode all possible inputs, the basic logic unit of a FPGA,
> > > only 4 to 20.
> > The Lattice isp1048 PLD had a lot more connectivity than a modern FPGA.
> Not true!
> > This is why a VLIW design on the PLD was possible, but is impossible on an FPGA.
> I don't know what a VLIW is, but I know anything possible on a PLD can be done better on a modern FPGA.

Hugh won't agree on this, but a VLIW (Very Long Instruction Word) processor has very little encoding of fields, with many control points in the processor having individual bits in the instruction word. This provides tons of flexibility in each instruction, rather than being limited to a fixed instruction set. In particular, this allows the maximum parallelism to be exploited.

TI used "VLIW" in their TMS320C6xxx DSP line, but it's not quite the same thing. They had multiple CPUs in the chip, which all had a core functionality, with enhanced features in a few. They simply aggregated the 32 bit instructions into a 256 bit main instruction word. The earlier versions of the processor were bandwidth limited because of the need for external program storage. Eventually, as semiconductor processing provide more and more, on-chip memory, they could keep all the processors running. They were essentially used with a few doing math operations, while others were DMA engines keeping the data moving. Still, not exactly, VLIW, in the traditional sense.

I worked on attached array processors, which were VLIW in the real sense, with over 100 bits in the ALU control store. There was a separate "storage-move" processor that managed moving the data between main memory, cache and the compute head register file. Lots of ECL gate arrays, and lots of power.

> <ad hominem & nonsense clipped>
> > A VLIW processor is obsolete now (this might still be possible in an ASIC, though).
> Our original MSI LSI based processor (4S32) used in thousands ofTicketMaster terminals,
> was a Harvard architecture with a 32 bit instruction (not sure if that qualifies as VLIW),

That's a standard processor design, I expect, with encoded fields.

> a 16 bit data path and 4 bit ALU. [An emulation of an Intel 286 (virtual PC) on it would
> run a little faster than it. An emulation of a customers 16 bit processor ran 5 times faster.]

Maybe I spoke too soon. To say if it was along the concept of VLIW would require considering what the fields in the instruction were doing. If they mostly directly controlled various functions in the CPU, rather than being encoded, that would be VLIW.

> The Forth multi-user system we manufactured using the same CPU supported 7 users.
> When we moved the design to the PLD ,the instruction width was shrunk to 16 bits, which
> I'm sure doesn't qualify as a Very Large Instruction Width. The arithmetic part of the ALU
> remained 4 bits but the logic part became 16.

It's not the number of bits in the instruction word, really. It's how they are used. If it has to be decoded, that's not VLIW. If individual bits directly control things like a mux select line or the selection of carry, etc, that's VLIW.

> The instruction word for the RACE32 is 18 bits, so it's not a VLIW either,
> but the ALU and internal data path have been expanded to 32 bits, enabled by
> the fast ripple carry feature of FPGAs.
>
> The power of modern FPGA would blow people's minds, if they understood them.
> Advanced supercomputer have tens of thousands of chips with thousands of processes
> running in each one with more computing power than a PC. The fear about AAI taking
> over the world is based on the reality of what can be done with this power
> and how dangerous it would be if abused.
>
> Restrictions won't reduce the danger, they'll make it more dangerous, more concentrated.
> The solution to Big Tech having too much power is to empower people. Enable small business
> to use robotics and automation to compete. Something like an open source platform programed
> in Forth for automation would be the ideal tool to enable it. Focusing on solutions is the
> only way out of the mess we're in, Attacks and flame wars are a DEAD END, they accomplish
> NOTHING, and the din drowns out rational discourse.

What mess??? I must have missed something.

> HUGH WROTE MFX, never said he didn't. He was quite creative at the time.
>
> <clip more ad hominem crap>

Yeah, he's definitely off the deep end these days. He used to be a regular ranter here... I mean, a regular contributor here. But he disappeared for some time. He's not back in full force. He used to go out of his way to argue with people. He seems much more restrained now.

--

Rick C.

-+-- Get 1,000 miles of free Supercharging
-+-- Tesla referral code - https://ts.la/richard11209

>
> Why did Testra attack me on comp.lang.forth with lies and insults?
> Tom Hart made this attack on the command of Juergen Pintaske, the MPE salesman.
> Apparently you were in negotiation with Stephen Pelc for him to buy the RACE processor,
> and you believed that you had to obey Juergen Pintaske's commands to stay on
> Stephen Pelc's good side. It is unlikely that Stephen Pelc was going to buy your RACE
> processor. He was most likely just tugging your chain for the entertainment value of
> getting you to attack your own employee on comp.lang.forth. You think that you can
> totally crush me here on comp.lang.forth, but you harm yourself as much or more
> than you harm me. Testra won't be considered to be a reputable company any more.
> You have more to lose than I do. People who live in glass houses shouldn't throw stones!
> Attacking me on comp.lang.forth was a bad idea. Was alcohol involved in this decision?

TYPICAL HUCK AQUILUX BULLSHIT AGAIN.

He insinuates things that were never planned nor happened,
just to be able to attack people again.
All of these attacked are professionals - in contrast to him and his behaviour here.
And to waste everybody's time.

HE IS INSANE AND PROBABLY A DANGER FOR THE PEOPLE AROUND HIM.

I had just asked Testra to kindly state his activities with Testra
as an answer to all of his accusations here.
- which they did under the condition their email is published in full - which I did.
If there are some differences in perceptions 30 years later - so what.
This is how life works.

On Friday, April 28, 2023 at 10:41:09 PM UTC-7, Jurgen Pitaske wrote:
> >
> > Why did Testra attack me on comp.lang.forth with lies and insults?

No one from Testra ever attacked anyone on comp.lang.forth
or any other news group ever.

A gifted programmer, with no experience was given a chance,
succeeded and was let go after he finished because there was
nothing for him to do.

> I had just asked Testra to kindly state his activities with Testra
Which indicated he was a creative individual and like many creative
individuals, might be difficult to work with. A truth that's easily verified
by reading posts on this and many other tech newsgroups.

Not referring to anyone specific, some people not only burn their bridges
they spend years taking the foundation down to bedrock with a jackhammer
until no evidence of what they accomplished remains.

Flame wars are not only counterproductive they're destructive. Most
people, if they knew then what they know now, would have done things
differently. It's also true that if wishes were horses, beggers would ride.

Learning from past mistakes is good, getting mired in them is not.

My purpose for writing is NOT to get sucked into a flame war,
it's to have a discussion about Forth being the ideal language for a
Reconfigurable Architecture Computation Engine, specifically the
RACE32, which we are in the process of completing,

A thousand such processors could run on one of the new FPGA chips,
but the main applications, automation and robotics, would require
only one and run on a low cost device.
jrh

On Friday, April 28, 2023 at 5:06:51 PM UTC-7, Lorem Ipsum wrote:
> On Friday, April 28, 2023 at 2:56:23 PM UTC-4, John Hart wrote:
> > On Thursday, April 27, 2023 at 7:44:11 PM UTC-7, Hugh Aguilar wrote:
> > > On Wednesday, April 26, 2023 at 5:59:22 PM UTC-7, John Hart wrote:
> > > > On Tuesday, April 25, 2023 at 6:23:15 PM UTC-7, Lorem Ipsum wrote:
> > > > > I can't think of anything that is harder to do in an FPGA than in a CPLD,
> > > > ><clip>

> What mess??? I must have missed something.
> Rick C.
Not your fault if you still rely on MSM for your news.
America is in sharp decline on many fronts and MSM has been working overtime
hiding it. The parts of our social economic system are strongly linked and
a series of errors by the current administration, as serious as the Titanic
hittting an iceberg, have occured. The only solution is to get productivity
growing faster than debt to prevent runaway inflation, and that's going
to require an autiomation revolution at the roots. The concentration of
wealth by the Elite, not only stifles innovation it's extremely dangerous.
After all, power corrupts and absolute power corrupts absolutely.

On Saturday, 29 April 2023 at 07:47:36 UTC+1, John Hart wrote:
> On Friday, April 28, 2023 at 10:41:09 PM UTC-7, Jurgen Pitaske wrote:
> > >
> > > Why did Testra attack me on comp.lang.forth with lies and insults?
> No one from Testra ever attacked anyone on comp.lang.forth
> or any other news group ever.
>
> A gifted programmer, with no experience was given a chance,
> succeeded and was let go after he finished because there was
> nothing for him to do.
> > I had just asked Testra to kindly state his activities with Testra
> Which indicated he was a creative individual and like many creative
> individuals, might be difficult to work with. A truth that's easily verified
> by reading posts on this and many other tech newsgroups.
>
> Not referring to anyone specific, some people not only burn their bridges
> they spend years taking the foundation down to bedrock with a jackhammer
> until no evidence of what they accomplished remains.
>
> Flame wars are not only counterproductive they're destructive. Most
> people, if they knew then what they know now, would have done things
> differently. It's also true that if wishes were horses, beggers would ride.
>
> Learning from past mistakes is good, getting mired in them is not.
>
> My purpose for writing is NOT to get sucked into a flame war,
> it's to have a discussion about Forth being the ideal language for a
> Reconfigurable Architecture Computation Engine, specifically the
> RACE32, which we are in the process of completing,
>
> A thousand such processors could run on one of the new FPGA chips,
> but the main applications, automation and robotics, would require
> only one and run on a low cost device.
> jrh

A great post - Thank You

On Saturday, April 29, 2023 at 3:07:22 AM UTC-4, John Hart wrote:
> On Friday, April 28, 2023 at 5:06:51 PM UTC-7, Lorem Ipsum wrote:
> > On Friday, April 28, 2023 at 2:56:23 PM UTC-4, John Hart wrote:
> > > On Thursday, April 27, 2023 at 7:44:11 PM UTC-7, Hugh Aguilar wrote:
> > > > On Wednesday, April 26, 2023 at 5:59:22 PM UTC-7, John Hart wrote:
> > > > > On Tuesday, April 25, 2023 at 6:23:15 PM UTC-7, Lorem Ipsum wrote:
> > > > > > I can't think of anything that is harder to do in an FPGA than in a CPLD,
> > > > > ><clip>
> > What mess??? I must have missed something.
> > Rick C.
> Not your fault if you still rely on MSM for your news.
> America is in sharp decline on many fronts and MSM has been working overtime
> hiding it. The parts of our social economic system are strongly linked and
> a series of errors by the current administration, as serious as the Titanic
> hittting an iceberg, have occured. The only solution is to get productivity
> growing faster than debt to prevent runaway inflation, and that's going
> to require an autiomation revolution at the roots. The concentration of
> wealth by the Elite, not only stifles innovation it's extremely dangerous..
> After all, power corrupts and absolute power corrupts absolutely.

Got it. I completely understand now. Thanks

--

Rick C.

-+-+ Get 1,000 miles of free Supercharging
-+-+ Tesla referral code - https://ts.la/richard11209

On Friday, April 28, 2023 at 11:47:36 PM UTC-7, John Hart wrote:
> On Friday, April 28, 2023 at 10:41:09 PM UTC-7, Jurgen Pitaske wrote:
> > >
> > > Why did Testra attack me on comp.lang.forth with lies and insults?
> No one from Testra ever attacked anyone on comp.lang.forth
> or any other news group ever.

Bullshit!
This entire thread was an unprovoked attack on me:
https://groups.google.com/g/comp.lang.forth/c/wydQr643gX0

Tom Hart was totally lying:
> I let him go myself,
> after I had given him a project to write a DXF converter to HPGL code.
> He would not take any direction.
> I scrapped the project.

I never even heard of HPGL before this attack. There was no HPGL project.
Also, I never got any direction in any of my work.
When I wrote the DXF to GCODE converter nobody told me about how
Bezier Splines might work. I didn't know about Bezier Splines, and I assume
that the reason I wasn't told about Bezier Splines is that Tom and John Hart
don't know about them either. Tom Hart would just angrily tell me:
"Just make a smooth line through all the tiny line segments!"
There was just a mish-mash of tiny line segments ranging from 1/1000 of an inch
to 20/1000 of an inch, and some longer. They pointed in every which direction. Some
weren't touching any other line segment and some touched other line segments.
I had no idea how to make a smooth line through this mess. I wished that I did
have some direction, but I never did. I wished that I had mind-reading ability
so that I could know what image the artist had intended with this mish-mash..
Tom Hart says that I'm too stupid to write a data-conversion program.
This isn't true. I was converting DXF code to GCODE within a couple of weeks
of starting the project. The problem was that the result was a mess.
When I started the project I was told that this was a simple data-conversion
program, so I felt confident that I could finish in a few weeks. If I had been told
that I had to make a smooth line through a big mess of tiny line-segments,
I would have refused the job. If I had been told that I needed Bezier Splines
I would have refused the job because I don't know anything about the subject.
(This is where the comp.lang.forth trolls can spring into action and say that
they could easily implement Bezier Splines, so they get to be big internet experts
without writing any code, as usual).

Tom Hart was totally lying:
> [Hugh] had nothing to do with the processor itself,
> that was all designed by John Hart and Steve Brault.
>
> The PLD version was based upon our original Forth Engine done long before
> we ever ran across Hugh.

The original Forth Engine was a bit-slice processor.
This is unrelated to the MiniForth that was a VLIW processor.
Tom Hart is saying that MFX was written for the bit-slice processor and then
was used on the MiniForth. Bullshit! I wrote MFX for the MiniForth (MFX means
Mini Forth Xcompiler). I never saw any of the code from the original Forth Engine.
All of that was written by John Perona who later wrote Multi-Edit. Even if there
had been some similarity between the original Forth Engine and the MiniForth,
I still wouldn't have looked at John Perona's code because I never look at other
people's code (that is like peering through a bedroom window to look at your
neighbor's wife). Also, as a practical matter John Perona is a typical C programmer
who writes multi-page functions. He doesn't factor code at all.

Testra was originally called Hartronics and they advertised their "Forth Engine"
in Forth Dimensions, in case anybody cares (I don't).

It was obvious that Juergen Pintaske wanted to denounce me on comp.lang.forth,
by saying that I am lying about writing MFX at Testra. Tom Hart totally complied by
providing Juergen Pintaske with support for this attack. All of Juergen Pintaske's
attacks on me over the last four years have been based on him obtaining 100%
support from Tom Hart.
It is very disingenuous for John Hart to now say:
> No one from Testra ever attacked anyone on comp.lang.forth
> or any other news group ever.
Bullshit! You could have ignored Juergen Pintaske. Everybody else in the world does!
Instead you provided Juergen Pintaske with 100% support for attacking me.
Juergen Pintaske is now Testra's mouthpiece, and he has Tom Hart's support in this.

> Not referring to anyone specific, some people not only burn their bridges
> they spend years taking the foundation down to bedrock with a jackhammer
> until no evidence of what they accomplished remains.

It was in the 1990s, less than five years after I left Testra, when I heard John Hart
(possibly Tom Hart doing an impersonation) say on speaker-phone that I had
accomplished "nothing" and that I was not eligible for rehire. Presumably Testra had
been saying this starting immediately after I left Testra but it was a few years later
when I caught them at this. So, it didn't take Tom Hart long to burn his bridge with me,
and jackhammer the foundation, to ensure that no evidence of accomplishment remains.
Tom Hart cares about loyalty! He expects employees to remain employed forever,
never asking for a raise or health insurance or anything else. Loyalty is a one-way street;
Tom Hart has no sense of loyalty to his employees and will attack them in public.

Why didn't Testra just tell me when I left that leaving was an act of disloyalty
and that I would never get a reference? I made a fool out of myself by going to
job interviews, such as at Lockheed Martin, and saying that I wrote MFX at Testra.
Most likely, Testra wanted me to go to these job interviews and describe MFX,
not for my benefit, but just as an advertisement for Testra's MiniForth processor.
They may have been hoping that Lockheed Martin would buy the MiniForth so
they could become wealthy, but they had no way to get Lockheed Martin's attention.
You can't just show up in the lobby of Lockheed Martin and tell the receptionist:
"Hi! I've got a super-awesome processor! Would you like to buy it?"
They may have believed (correctly) that for me to go to a job interview at
Lockheed Martin and describe MFX would be the only way that Lockheed Martin
would find out about the MiniForth --- but they would pull the rug out from under me
by telling Lockheed Martin that they wrote MFX --- they would explain to
Lockheed Martin that they are geniuses who deserve to get rich!

On Sunday, 30 April 2023 at 00:34:09 UTC+1, Hugh Aguilar wrote:
> On Friday, April 28, 2023 at 11:47:36 PM UTC-7, John Hart wrote:
> > On Friday, April 28, 2023 at 10:41:09 PM UTC-7, Jurgen Pitaske wrote:
> > > >
> > > > Why did Testra attack me on comp.lang.forth with lies and insults?
> > No one from Testra ever attacked anyone on comp.lang.forth
> > or any other news group ever.
> Bullshit!
> This entire thread was an unprovoked attack on me:
> https://groups.google.com/g/comp.lang.forth/c/wydQr643gX0
>
> Tom Hart was totally lying:
> > I let him go myself,
> > after I had given him a project to write a DXF converter to HPGL code.
> > He would not take any direction.
> > I scrapped the project.
>
> I never even heard of HPGL before this attack. There was no HPGL project.
> Also, I never got any direction in any of my work.
> When I wrote the DXF to GCODE converter nobody told me about how
> Bezier Splines might work. I didn't know about Bezier Splines, and I assume
> that the reason I wasn't told about Bezier Splines is that Tom and John Hart
> don't know about them either. Tom Hart would just angrily tell me:
> "Just make a smooth line through all the tiny line segments!"
> There was just a mish-mash of tiny line segments ranging from 1/1000 of an inch
> to 20/1000 of an inch, and some longer. They pointed in every which direction. Some
> weren't touching any other line segment and some touched other line segments.
> I had no idea how to make a smooth line through this mess. I wished that I did
> have some direction, but I never did. I wished that I had mind-reading ability
> so that I could know what image the artist had intended with this mish-mash.
> Tom Hart says that I'm too stupid to write a data-conversion program.
> This isn't true. I was converting DXF code to GCODE within a couple of weeks
> of starting the project. The problem was that the result was a mess.
> When I started the project I was told that this was a simple data-conversion
> program, so I felt confident that I could finish in a few weeks. If I had been told
> that I had to make a smooth line through a big mess of tiny line-segments,
> I would have refused the job. If I had been told that I needed Bezier Splines
> I would have refused the job because I don't know anything about the subject.
> (This is where the comp.lang.forth trolls can spring into action and say that
> they could easily implement Bezier Splines, so they get to be big internet experts
> without writing any code, as usual).
>
> Tom Hart was totally lying:
> > [Hugh] had nothing to do with the processor itself,
> > that was all designed by John Hart and Steve Brault.
> >
> > The PLD version was based upon our original Forth Engine done long before
> > we ever ran across Hugh.
> The original Forth Engine was a bit-slice processor.
> This is unrelated to the MiniForth that was a VLIW processor.
> Tom Hart is saying that MFX was written for the bit-slice processor and then
> was used on the MiniForth. Bullshit! I wrote MFX for the MiniForth (MFX means
> Mini Forth Xcompiler). I never saw any of the code from the original Forth Engine.
> All of that was written by John Perona who later wrote Multi-Edit. Even if there
> had been some similarity between the original Forth Engine and the MiniForth,
> I still wouldn't have looked at John Perona's code because I never look at other
> people's code (that is like peering through a bedroom window to look at your
> neighbor's wife). Also, as a practical matter John Perona is a typical C programmer
> who writes multi-page functions. He doesn't factor code at all.
>
> Testra was originally called Hartronics and they advertised their "Forth Engine"
> in Forth Dimensions, in case anybody cares (I don't).
>
> It was obvious that Juergen Pintaske wanted to denounce me on comp.lang.forth,
> by saying that I am lying about writing MFX at Testra. Tom Hart totally complied by
> providing Juergen Pintaske with support for this attack. All of Juergen Pintaske's
> attacks on me over the last four years have been based on him obtaining 100%
> support from Tom Hart.
> It is very disingenuous for John Hart to now say:
> > No one from Testra ever attacked anyone on comp.lang.forth
> > or any other news group ever.
> Bullshit! You could have ignored Juergen Pintaske. Everybody else in the world does!
> Instead you provided Juergen Pintaske with 100% support for attacking me.
> Juergen Pintaske is now Testra's mouthpiece, and he has Tom Hart's support in this.
> > Not referring to anyone specific, some people not only burn their bridges
> > they spend years taking the foundation down to bedrock with a jackhammer
> > until no evidence of what they accomplished remains.
> It was in the 1990s, less than five years after I left Testra, when I heard John Hart
> (possibly Tom Hart doing an impersonation) say on speaker-phone that I had
> accomplished "nothing" and that I was not eligible for rehire. Presumably Testra had
> been saying this starting immediately after I left Testra but it was a few years later
> when I caught them at this. So, it didn't take Tom Hart long to burn his bridge with me,
> and jackhammer the foundation, to ensure that no evidence of accomplishment remains.
> Tom Hart cares about loyalty! He expects employees to remain employed forever,
> never asking for a raise or health insurance or anything else. Loyalty is a one-way street;
> Tom Hart has no sense of loyalty to his employees and will attack them in public.
>
> Why didn't Testra just tell me when I left that leaving was an act of disloyalty
> and that I would never get a reference? I made a fool out of myself by going to
> job interviews, such as at Lockheed Martin, and saying that I wrote MFX at Testra.
> Most likely, Testra wanted me to go to these job interviews and describe MFX,
> not for my benefit, but just as an advertisement for Testra's MiniForth processor.
> They may have been hoping that Lockheed Martin would buy the MiniForth so
> they could become wealthy, but they had no way to get Lockheed Martin's attention.
> You can't just show up in the lobby of Lockheed Martin and tell the receptionist:
> "Hi! I've got a super-awesome processor! Would you like to buy it?"
> They may have believed (correctly) that for me to go to a job interview at
> Lockheed Martin and describe MFX would be the only way that Lockheed Martin
> would find out about the MiniForth --- but they would pull the rug out from under me
> by telling Lockheed Martin that they wrote MFX --- they would explain to
> Lockheed Martin that they are geniuses who deserve to get rich!

WHAT A MENTAL DESASTER AGAIN.

Everybody is a liar - which automatically leads to
HUGH AGUILAR IS an AGUILIAR as he is part of everybody.
GO BACK TO YOUR CAGE AND BARK OR NOT.

Another made up piece of lies - just to make you feel good.

I did my job at MPE as consultant,
which triggered tmy FORTH BOOKSHELF on amazon
https://www.amazon.co.uk/Juergen-Pintaske/e/B00N8HVEZM%3Fref=dbs_a_mng_rwt_scns_share
I convinced Steve to do the 1802 in FPGA and the FIG-Forth that goees with it on github.
And he did as well the MISC PROCESSOR I HAD INITIATED in FPGA plus a Forth that goes with it.
What have you contributed over the last 30 years
- except of often dayly rants and
accusations of probably everybody here.

On Sunday, 30 April 2023 at 07:14:16 UTC+1, Jurgen Pitaske wrote:
> On Sunday, 30 April 2023 at 00:34:09 UTC+1, Hugh Aguilar wrote:
> > On Friday, April 28, 2023 at 11:47:36 PM UTC-7, John Hart wrote:
> > > On Friday, April 28, 2023 at 10:41:09 PM UTC-7, Jurgen Pitaske wrote:
> > > > >
> > > > > Why did Testra attack me on comp.lang.forth with lies and insults?
> > > No one from Testra ever attacked anyone on comp.lang.forth
> > > or any other news group ever.
> > Bullshit!
> > This entire thread was an unprovoked attack on me:
> > https://groups.google.com/g/comp.lang.forth/c/wydQr643gX0
> >
> > Tom Hart was totally lying:
> > > I let him go myself,
> > > after I had given him a project to write a DXF converter to HPGL code..
> > > He would not take any direction.
> > > I scrapped the project.
> >
> > I never even heard of HPGL before this attack. There was no HPGL project.
> > Also, I never got any direction in any of my work.
> > When I wrote the DXF to GCODE converter nobody told me about how
> > Bezier Splines might work. I didn't know about Bezier Splines, and I assume
> > that the reason I wasn't told about Bezier Splines is that Tom and John Hart
> > don't know about them either. Tom Hart would just angrily tell me:
> > "Just make a smooth line through all the tiny line segments!"
> > There was just a mish-mash of tiny line segments ranging from 1/1000 of an inch
> > to 20/1000 of an inch, and some longer. They pointed in every which direction. Some
> > weren't touching any other line segment and some touched other line segments.
> > I had no idea how to make a smooth line through this mess. I wished that I did
> > have some direction, but I never did. I wished that I had mind-reading ability
> > so that I could know what image the artist had intended with this mish-mash.
> > Tom Hart says that I'm too stupid to write a data-conversion program.
> > This isn't true. I was converting DXF code to GCODE within a couple of weeks
> > of starting the project. The problem was that the result was a mess.
> > When I started the project I was told that this was a simple data-conversion
> > program, so I felt confident that I could finish in a few weeks. If I had been told
> > that I had to make a smooth line through a big mess of tiny line-segments,
> > I would have refused the job. If I had been told that I needed Bezier Splines
> > I would have refused the job because I don't know anything about the subject.
> > (This is where the comp.lang.forth trolls can spring into action and say that
> > they could easily implement Bezier Splines, so they get to be big internet experts
> > without writing any code, as usual).
> >
> > Tom Hart was totally lying:
> > > [Hugh] had nothing to do with the processor itself,
> > > that was all designed by John Hart and Steve Brault.
> > >
> > > The PLD version was based upon our original Forth Engine done long before
> > > we ever ran across Hugh.
> > The original Forth Engine was a bit-slice processor.
> > This is unrelated to the MiniForth that was a VLIW processor.
> > Tom Hart is saying that MFX was written for the bit-slice processor and then
> > was used on the MiniForth. Bullshit! I wrote MFX for the MiniForth (MFX means
> > Mini Forth Xcompiler). I never saw any of the code from the original Forth Engine.
> > All of that was written by John Perona who later wrote Multi-Edit. Even if there
> > had been some similarity between the original Forth Engine and the MiniForth,
> > I still wouldn't have looked at John Perona's code because I never look at other
> > people's code (that is like peering through a bedroom window to look at your
> > neighbor's wife). Also, as a practical matter John Perona is a typical C programmer
> > who writes multi-page functions. He doesn't factor code at all.
> >
> > Testra was originally called Hartronics and they advertised their "Forth Engine"
> > in Forth Dimensions, in case anybody cares (I don't).
> >
> > It was obvious that Juergen Pintaske wanted to denounce me on comp.lang..forth,
> > by saying that I am lying about writing MFX at Testra. Tom Hart totally complied by
> > providing Juergen Pintaske with support for this attack. All of Juergen Pintaske's
> > attacks on me over the last four years have been based on him obtaining 100%
> > support from Tom Hart.
> > It is very disingenuous for John Hart to now say:
> > > No one from Testra ever attacked anyone on comp.lang.forth
> > > or any other news group ever.
> > Bullshit! You could have ignored Juergen Pintaske. Everybody else in the world does!
> > Instead you provided Juergen Pintaske with 100% support for attacking me.
> > Juergen Pintaske is now Testra's mouthpiece, and he has Tom Hart's support in this.
> > > Not referring to anyone specific, some people not only burn their bridges
> > > they spend years taking the foundation down to bedrock with a jackhammer
> > > until no evidence of what they accomplished remains.
> > It was in the 1990s, less than five years after I left Testra, when I heard John Hart
> > (possibly Tom Hart doing an impersonation) say on speaker-phone that I had
> > accomplished "nothing" and that I was not eligible for rehire. Presumably Testra had
> > been saying this starting immediately after I left Testra but it was a few years later
> > when I caught them at this. So, it didn't take Tom Hart long to burn his bridge with me,
> > and jackhammer the foundation, to ensure that no evidence of accomplishment remains.
> > Tom Hart cares about loyalty! He expects employees to remain employed forever,
> > never asking for a raise or health insurance or anything else. Loyalty is a one-way street;
> > Tom Hart has no sense of loyalty to his employees and will attack them in public.
> >
> > Why didn't Testra just tell me when I left that leaving was an act of disloyalty
> > and that I would never get a reference? I made a fool out of myself by going to
> > job interviews, such as at Lockheed Martin, and saying that I wrote MFX at Testra.
> > Most likely, Testra wanted me to go to these job interviews and describe MFX,
> > not for my benefit, but just as an advertisement for Testra's MiniForth processor.
> > They may have been hoping that Lockheed Martin would buy the MiniForth so
> > they could become wealthy, but they had no way to get Lockheed Martin's attention.
> > You can't just show up in the lobby of Lockheed Martin and tell the receptionist:
> > "Hi! I've got a super-awesome processor! Would you like to buy it?"
> > They may have believed (correctly) that for me to go to a job interview at
> > Lockheed Martin and describe MFX would be the only way that Lockheed Martin
> > would find out about the MiniForth --- but they would pull the rug out from under me
> > by telling Lockheed Martin that they wrote MFX --- they would explain to
> > Lockheed Martin that they are geniuses who deserve to get rich!
> WHAT A MENTAL DESASTER AGAIN.
>
> Everybody is a liar - which automatically leads to
> HUGH AGUILAR IS an AGUILIAR as he is part of everybody.
> GO BACK TO YOUR CAGE AND BARK OR NOT.
>
> Another made up piece of lies - just to make you feel good.
>
> I did my job at MPE as consultant,
> which triggered tmy FORTH BOOKSHELF on amazon
> https://www.amazon.co.uk/Juergen-Pintaske/e/B00N8HVEZM%3Fref=dbs_a_mng_rwt_scns_share
> I convinced Steve to do the 1802 in FPGA and the FIG-Forth that goees with it on github.
> And he did as well the MISC PROCESSOR I HAD INITIATED in FPGA plus a Forth that goes with it.
> What have you contributed over the last 30 years
> - except of often dayly rants and
> accusations of probably everybody here.

LIAR LIAR LIAR - YOU ARE DOING WELL.
To state that my letter to Testra and the kind answer from there was started without reason
is the biggest lie you ever told.

You have attacked me over the last 10 years for no real reason
- it is all here on CLF so you can check
for no real reason.
So I wondered what Testra would say about you,
and it ended up in the probably most read post of CLF with about 4400 reads now.
https://groups.google.com/g/comp.lang.forth/c/wydQr643gX0
It will be 4444 soon -
You cannot get closer to fours.
Have a nice day,
and May The Fours Be With You.

On Sunday, 30 April 2023 at 07:22:12 UTC+1, Jurgen Pitaske wrote:
> On Sunday, 30 April 2023 at 07:14:16 UTC+1, Jurgen Pitaske wrote:
> > On Sunday, 30 April 2023 at 00:34:09 UTC+1, Hugh Aguilar wrote:
> > > On Friday, April 28, 2023 at 11:47:36 PM UTC-7, John Hart wrote:
> > > > On Friday, April 28, 2023 at 10:41:09 PM UTC-7, Jurgen Pitaske wrote:
> > > > > >
> > > > > > Why did Testra attack me on comp.lang.forth with lies and insults?
> > > > No one from Testra ever attacked anyone on comp.lang.forth
> > > > or any other news group ever.
> > > Bullshit!
> > > This entire thread was an unprovoked attack on me:
> > > https://groups.google.com/g/comp.lang.forth/c/wydQr643gX0
> > >
> > > Tom Hart was totally lying:
> > > > I let him go myself,
> > > > after I had given him a project to write a DXF converter to HPGL code.
> > > > He would not take any direction.
> > > > I scrapped the project.
> > >
> > > I never even heard of HPGL before this attack. There was no HPGL project.
> > > Also, I never got any direction in any of my work.
> > > When I wrote the DXF to GCODE converter nobody told me about how
> > > Bezier Splines might work. I didn't know about Bezier Splines, and I assume
> > > that the reason I wasn't told about Bezier Splines is that Tom and John Hart
> > > don't know about them either. Tom Hart would just angrily tell me:
> > > "Just make a smooth line through all the tiny line segments!"
> > > There was just a mish-mash of tiny line segments ranging from 1/1000 of an inch
> > > to 20/1000 of an inch, and some longer. They pointed in every which direction. Some
> > > weren't touching any other line segment and some touched other line segments.
> > > I had no idea how to make a smooth line through this mess. I wished that I did
> > > have some direction, but I never did. I wished that I had mind-reading ability
> > > so that I could know what image the artist had intended with this mish-mash.
> > > Tom Hart says that I'm too stupid to write a data-conversion program.
> > > This isn't true. I was converting DXF code to GCODE within a couple of weeks
> > > of starting the project. The problem was that the result was a mess.
> > > When I started the project I was told that this was a simple data-conversion
> > > program, so I felt confident that I could finish in a few weeks. If I had been told
> > > that I had to make a smooth line through a big mess of tiny line-segments,
> > > I would have refused the job. If I had been told that I needed Bezier Splines
> > > I would have refused the job because I don't know anything about the subject.
> > > (This is where the comp.lang.forth trolls can spring into action and say that
> > > they could easily implement Bezier Splines, so they get to be big internet experts
> > > without writing any code, as usual).
> > >
> > > Tom Hart was totally lying:
> > > > [Hugh] had nothing to do with the processor itself,
> > > > that was all designed by John Hart and Steve Brault.
> > > >
> > > > The PLD version was based upon our original Forth Engine done long before
> > > > we ever ran across Hugh.
> > > The original Forth Engine was a bit-slice processor.
> > > This is unrelated to the MiniForth that was a VLIW processor.
> > > Tom Hart is saying that MFX was written for the bit-slice processor and then
> > > was used on the MiniForth. Bullshit! I wrote MFX for the MiniForth (MFX means
> > > Mini Forth Xcompiler). I never saw any of the code from the original Forth Engine.
> > > All of that was written by John Perona who later wrote Multi-Edit. Even if there
> > > had been some similarity between the original Forth Engine and the MiniForth,
> > > I still wouldn't have looked at John Perona's code because I never look at other
> > > people's code (that is like peering through a bedroom window to look at your
> > > neighbor's wife). Also, as a practical matter John Perona is a typical C programmer
> > > who writes multi-page functions. He doesn't factor code at all.
> > >
> > > Testra was originally called Hartronics and they advertised their "Forth Engine"
> > > in Forth Dimensions, in case anybody cares (I don't).
> > >
> > > It was obvious that Juergen Pintaske wanted to denounce me on comp.lang.forth,
> > > by saying that I am lying about writing MFX at Testra. Tom Hart totally complied by
> > > providing Juergen Pintaske with support for this attack. All of Juergen Pintaske's
> > > attacks on me over the last four years have been based on him obtaining 100%
> > > support from Tom Hart.
> > > It is very disingenuous for John Hart to now say:
> > > > No one from Testra ever attacked anyone on comp.lang.forth
> > > > or any other news group ever.
> > > Bullshit! You could have ignored Juergen Pintaske. Everybody else in the world does!
> > > Instead you provided Juergen Pintaske with 100% support for attacking me.
> > > Juergen Pintaske is now Testra's mouthpiece, and he has Tom Hart's support in this.
> > > > Not referring to anyone specific, some people not only burn their bridges
> > > > they spend years taking the foundation down to bedrock with a jackhammer
> > > > until no evidence of what they accomplished remains.
> > > It was in the 1990s, less than five years after I left Testra, when I heard John Hart
> > > (possibly Tom Hart doing an impersonation) say on speaker-phone that I had
> > > accomplished "nothing" and that I was not eligible for rehire. Presumably Testra had
> > > been saying this starting immediately after I left Testra but it was a few years later
> > > when I caught them at this. So, it didn't take Tom Hart long to burn his bridge with me,
> > > and jackhammer the foundation, to ensure that no evidence of accomplishment remains.
> > > Tom Hart cares about loyalty! He expects employees to remain employed forever,
> > > never asking for a raise or health insurance or anything else. Loyalty is a one-way street;
> > > Tom Hart has no sense of loyalty to his employees and will attack them in public.
> > >
> > > Why didn't Testra just tell me when I left that leaving was an act of disloyalty
> > > and that I would never get a reference? I made a fool out of myself by going to
> > > job interviews, such as at Lockheed Martin, and saying that I wrote MFX at Testra.
> > > Most likely, Testra wanted me to go to these job interviews and describe MFX,
> > > not for my benefit, but just as an advertisement for Testra's MiniForth processor.
> > > They may have been hoping that Lockheed Martin would buy the MiniForth so
> > > they could become wealthy, but they had no way to get Lockheed Martin's attention.
> > > You can't just show up in the lobby of Lockheed Martin and tell the receptionist:
> > > "Hi! I've got a super-awesome processor! Would you like to buy it?"
> > > They may have believed (correctly) that for me to go to a job interview at
> > > Lockheed Martin and describe MFX would be the only way that Lockheed Martin
> > > would find out about the MiniForth --- but they would pull the rug out from under me
> > > by telling Lockheed Martin that they wrote MFX --- they would explain to
> > > Lockheed Martin that they are geniuses who deserve to get rich!
> > WHAT A MENTAL DESASTER AGAIN.
> >
> > Everybody is a liar - which automatically leads to
> > HUGH AGUILAR IS an AGUILIAR as he is part of everybody.
> > GO BACK TO YOUR CAGE AND BARK OR NOT.
> >
> > Another made up piece of lies - just to make you feel good.
> >
> > I did my job at MPE as consultant,
> > which triggered tmy FORTH BOOKSHELF on amazon
> > https://www.amazon.co.uk/Juergen-Pintaske/e/B00N8HVEZM%3Fref=dbs_a_mng_rwt_scns_share
> > I convinced Steve to do the 1802 in FPGA and the FIG-Forth that goees with it on github.
> > And he did as well the MISC PROCESSOR I HAD INITIATED in FPGA plus a Forth that goes with it.
> > What have you contributed over the last 30 years
> > - except of often dayly rants and
> > accusations of probably everybody here.
> LIAR LIAR LIAR - YOU ARE DOING WELL.
> To state that my letter to Testra and the kind answer from there was started without reason
> is the biggest lie you ever told.
>
> You have attacked me over the last 10 years for no real reason
> - it is all here on CLF so you can check
> for no real reason.
> So I wondered what Testra would say about you,
> and it ended up in the probably most read post of CLF with about 4400 reads now.
> https://groups.google.com/g/comp.lang.forth/c/wydQr643gX0
> It will be 4444 soon -
> You cannot get closer to fours.
> Have a nice day,
> and May The Fours Be With You.

On Sunday, 30 April 2023 at 07:22:12 UTC+1, Jurgen Pitaske wrote:
> On Sunday, 30 April 2023 at 07:14:16 UTC+1, Jurgen Pitaske wrote:
> > On Sunday, 30 April 2023 at 00:34:09 UTC+1, Hugh Aguilar wrote:
> > > On Friday, April 28, 2023 at 11:47:36 PM UTC-7, John Hart wrote:
> > > > On Friday, April 28, 2023 at 10:41:09 PM UTC-7, Jurgen Pitaske wrote:
> > > > > >
> > > > > > Why did Testra attack me on comp.lang.forth with lies and insults?
> > > > No one from Testra ever attacked anyone on comp.lang.forth
> > > > or any other news group ever.
> > > Bullshit!
> > > This entire thread was an unprovoked attack on me:
> > > https://groups.google.com/g/comp.lang.forth/c/wydQr643gX0
> > >
> > > Tom Hart was totally lying:
> > > > I let him go myself,
> > > > after I had given him a project to write a DXF converter to HPGL code.
> > > > He would not take any direction.
> > > > I scrapped the project.
> > >
> > > I never even heard of HPGL before this attack. There was no HPGL project.
> > > Also, I never got any direction in any of my work.
> > > When I wrote the DXF to GCODE converter nobody told me about how
> > > Bezier Splines might work. I didn't know about Bezier Splines, and I assume
> > > that the reason I wasn't told about Bezier Splines is that Tom and John Hart
> > > don't know about them either. Tom Hart would just angrily tell me:
> > > "Just make a smooth line through all the tiny line segments!"
> > > There was just a mish-mash of tiny line segments ranging from 1/1000 of an inch
> > > to 20/1000 of an inch, and some longer. They pointed in every which direction. Some
> > > weren't touching any other line segment and some touched other line segments.
> > > I had no idea how to make a smooth line through this mess. I wished that I did
> > > have some direction, but I never did. I wished that I had mind-reading ability
> > > so that I could know what image the artist had intended with this mish-mash.
> > > Tom Hart says that I'm too stupid to write a data-conversion program.
> > > This isn't true. I was converting DXF code to GCODE within a couple of weeks
> > > of starting the project. The problem was that the result was a mess.
> > > When I started the project I was told that this was a simple data-conversion
> > > program, so I felt confident that I could finish in a few weeks. If I had been told
> > > that I had to make a smooth line through a big mess of tiny line-segments,
> > > I would have refused the job. If I had been told that I needed Bezier Splines
> > > I would have refused the job because I don't know anything about the subject.
> > > (This is where the comp.lang.forth trolls can spring into action and say that
> > > they could easily implement Bezier Splines, so they get to be big internet experts
> > > without writing any code, as usual).
> > >
> > > Tom Hart was totally lying:
> > > > [Hugh] had nothing to do with the processor itself,
> > > > that was all designed by John Hart and Steve Brault.
> > > >
> > > > The PLD version was based upon our original Forth Engine done long before
> > > > we ever ran across Hugh.
> > > The original Forth Engine was a bit-slice processor.
> > > This is unrelated to the MiniForth that was a VLIW processor.
> > > Tom Hart is saying that MFX was written for the bit-slice processor and then
> > > was used on the MiniForth. Bullshit! I wrote MFX for the MiniForth (MFX means
> > > Mini Forth Xcompiler). I never saw any of the code from the original Forth Engine.
> > > All of that was written by John Perona who later wrote Multi-Edit. Even if there
> > > had been some similarity between the original Forth Engine and the MiniForth,
> > > I still wouldn't have looked at John Perona's code because I never look at other
> > > people's code (that is like peering through a bedroom window to look at your
> > > neighbor's wife). Also, as a practical matter John Perona is a typical C programmer
> > > who writes multi-page functions. He doesn't factor code at all.
> > >
> > > Testra was originally called Hartronics and they advertised their "Forth Engine"
> > > in Forth Dimensions, in case anybody cares (I don't).
> > >
> > > It was obvious that Juergen Pintaske wanted to denounce me on comp.lang.forth,
> > > by saying that I am lying about writing MFX at Testra. Tom Hart totally complied by
> > > providing Juergen Pintaske with support for this attack. All of Juergen Pintaske's
> > > attacks on me over the last four years have been based on him obtaining 100%
> > > support from Tom Hart.
> > > It is very disingenuous for John Hart to now say:
> > > > No one from Testra ever attacked anyone on comp.lang.forth
> > > > or any other news group ever.
> > > Bullshit! You could have ignored Juergen Pintaske. Everybody else in the world does!
> > > Instead you provided Juergen Pintaske with 100% support for attacking me.
> > > Juergen Pintaske is now Testra's mouthpiece, and he has Tom Hart's support in this.
> > > > Not referring to anyone specific, some people not only burn their bridges
> > > > they spend years taking the foundation down to bedrock with a jackhammer
> > > > until no evidence of what they accomplished remains.
> > > It was in the 1990s, less than five years after I left Testra, when I heard John Hart
> > > (possibly Tom Hart doing an impersonation) say on speaker-phone that I had
> > > accomplished "nothing" and that I was not eligible for rehire. Presumably Testra had
> > > been saying this starting immediately after I left Testra but it was a few years later
> > > when I caught them at this. So, it didn't take Tom Hart long to burn his bridge with me,
> > > and jackhammer the foundation, to ensure that no evidence of accomplishment remains.
> > > Tom Hart cares about loyalty! He expects employees to remain employed forever,
> > > never asking for a raise or health insurance or anything else. Loyalty is a one-way street;
> > > Tom Hart has no sense of loyalty to his employees and will attack them in public.
> > >
> > > Why didn't Testra just tell me when I left that leaving was an act of disloyalty
> > > and that I would never get a reference? I made a fool out of myself by going to
> > > job interviews, such as at Lockheed Martin, and saying that I wrote MFX at Testra.
> > > Most likely, Testra wanted me to go to these job interviews and describe MFX,
> > > not for my benefit, but just as an advertisement for Testra's MiniForth processor.
> > > They may have been hoping that Lockheed Martin would buy the MiniForth so
> > > they could become wealthy, but they had no way to get Lockheed Martin's attention.
> > > You can't just show up in the lobby of Lockheed Martin and tell the receptionist:
> > > "Hi! I've got a super-awesome processor! Would you like to buy it?"
> > > They may have believed (correctly) that for me to go to a job interview at
> > > Lockheed Martin and describe MFX would be the only way that Lockheed Martin
> > > would find out about the MiniForth --- but they would pull the rug out from under me
> > > by telling Lockheed Martin that they wrote MFX --- they would explain to
> > > Lockheed Martin that they are geniuses who deserve to get rich!
> > WHAT A MENTAL DESASTER AGAIN.
> >
> > Everybody is a liar - which automatically leads to
> > HUGH AGUILAR IS an AGUILIAR as he is part of everybody.
> > GO BACK TO YOUR CAGE AND BARK OR NOT.
> >
> > Another made up piece of lies - just to make you feel good.
> >
> > I did my job at MPE as consultant,
> > which triggered tmy FORTH BOOKSHELF on amazon
> > https://www.amazon.co.uk/Juergen-Pintaske/e/B00N8HVEZM%3Fref=dbs_a_mng_rwt_scns_share
> > I convinced Steve to do the 1802 in FPGA and the FIG-Forth that goees with it on github.
> > And he did as well the MISC PROCESSOR I HAD INITIATED in FPGA plus a Forth that goes with it.
> > What have you contributed over the last 30 years
> > - except of often dayly rants and
> > accusations of probably everybody here.
> LIAR LIAR LIAR - YOU ARE DOING WELL.
> To state that my letter to Testra and the kind answer from there was started without reason
> is the biggest lie you ever told.
>
> You have attacked me over the last 10 years for no real reason
> - it is all here on CLF so you can check
> for no real reason.
> So I wondered what Testra would say about you,
> and it ended up in the probably most read post of CLF with about 4400 reads now.
> https://groups.google.com/g/comp.lang.forth/c/wydQr643gX0
> It will be 4444 soon -
> You cannot get closer to fours.
> Have a nice day,
> and May The Fours Be With You.